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drm/radeon: add support for RS740 IGP chipsets.
[linux-2.6/linux-2.6-openrd.git] / drivers / gpu / drm / radeon / radeon_drv.h
blob9d752bc0602b16273aea475984f6d34934e14e8d
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20080528"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 * 1.26- Add support for variable size PCI(E) gart aperture
99 * 1.27- Add support for IGP GART
100 * 1.28- Add support for VBL on CRTC2
101 * 1.29- R500 3D cmd buffer support
102 */
103 #define DRIVER_MAJOR 1
104 #define DRIVER_MINOR 29
105 #define DRIVER_PATCHLEVEL 0
106
107 /*
108 * Radeon chip families
109 */
110 enum radeon_family {
111 CHIP_R100,
112 CHIP_RV100,
113 CHIP_RS100,
114 CHIP_RV200,
115 CHIP_RS200,
116 CHIP_R200,
117 CHIP_RV250,
118 CHIP_RS300,
119 CHIP_RV280,
120 CHIP_R300,
121 CHIP_R350,
122 CHIP_RV350,
123 CHIP_RV380,
124 CHIP_R420,
125 CHIP_RV410,
126 CHIP_RS480,
127 CHIP_RS690,
128 CHIP_RS740,
129 CHIP_RV515,
130 CHIP_R520,
131 CHIP_RV530,
132 CHIP_RV560,
133 CHIP_RV570,
134 CHIP_R580,
135 CHIP_LAST,
136 };
137
138 enum radeon_cp_microcode_version {
139 UCODE_R100,
140 UCODE_R200,
141 UCODE_R300,
142 };
143
144 /*
145 * Chip flags
146 */
147 enum radeon_chip_flags {
148 RADEON_FAMILY_MASK = 0x0000ffffUL,
149 RADEON_FLAGS_MASK = 0xffff0000UL,
150 RADEON_IS_MOBILITY = 0x00010000UL,
151 RADEON_IS_IGP = 0x00020000UL,
152 RADEON_SINGLE_CRTC = 0x00040000UL,
153 RADEON_IS_AGP = 0x00080000UL,
154 RADEON_HAS_HIERZ = 0x00100000UL,
155 RADEON_IS_PCIE = 0x00200000UL,
156 RADEON_NEW_MEMMAP = 0x00400000UL,
157 RADEON_IS_PCI = 0x00800000UL,
158 RADEON_IS_IGPGART = 0x01000000UL,
159 };
160
161 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
162 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
163 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
164
165 typedef struct drm_radeon_freelist {
166 unsigned int age;
167 struct drm_buf *buf;
168 struct drm_radeon_freelist *next;
169 struct drm_radeon_freelist *prev;
170 } drm_radeon_freelist_t;
171
172 typedef struct drm_radeon_ring_buffer {
173 u32 *start;
174 u32 *end;
175 int size;
176 int size_l2qw;
177
178 int rptr_update; /* Double Words */
179 int rptr_update_l2qw; /* log2 Quad Words */
180
181 int fetch_size; /* Double Words */
182 int fetch_size_l2ow; /* log2 Oct Words */
183
184 u32 tail;
185 u32 tail_mask;
186 int space;
187
188 int high_mark;
189 } drm_radeon_ring_buffer_t;
190
191 typedef struct drm_radeon_depth_clear_t {
192 u32 rb3d_cntl;
193 u32 rb3d_zstencilcntl;
194 u32 se_cntl;
195 } drm_radeon_depth_clear_t;
196
197 struct drm_radeon_driver_file_fields {
198 int64_t radeon_fb_delta;
199 };
200
201 struct mem_block {
202 struct mem_block *next;
203 struct mem_block *prev;
204 int start;
205 int size;
206 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
207 };
208
209 struct radeon_surface {
210 int refcount;
211 u32 lower;
212 u32 upper;
213 u32 flags;
214 };
215
216 struct radeon_virt_surface {
217 int surface_index;
218 u32 lower;
219 u32 upper;
220 u32 flags;
221 struct drm_file *file_priv;
222 };
223
224 #define RADEON_FLUSH_EMITED (1 < 0)
225 #define RADEON_PURGE_EMITED (1 < 1)
226
227 typedef struct drm_radeon_private {
228 drm_radeon_ring_buffer_t ring;
229 drm_radeon_sarea_t *sarea_priv;
230
231 u32 fb_location;
232 u32 fb_size;
233 int new_memmap;
234
235 int gart_size;
236 u32 gart_vm_start;
237 unsigned long gart_buffers_offset;
238
239 int cp_mode;
240 int cp_running;
241
242 drm_radeon_freelist_t *head;
243 drm_radeon_freelist_t *tail;
244 int last_buf;
245 volatile u32 *scratch;
246 int writeback_works;
247
248 int usec_timeout;
249
250 int microcode_version;
251
252 struct {
253 u32 boxes;
254 int freelist_timeouts;
255 int freelist_loops;
256 int requested_bufs;
257 int last_frame_reads;
258 int last_clear_reads;
259 int clears;
260 int texture_uploads;
261 } stats;
262
263 int do_boxes;
264 int page_flipping;
265
266 u32 color_fmt;
267 unsigned int front_offset;
268 unsigned int front_pitch;
269 unsigned int back_offset;
270 unsigned int back_pitch;
271
272 u32 depth_fmt;
273 unsigned int depth_offset;
274 unsigned int depth_pitch;
275
276 u32 front_pitch_offset;
277 u32 back_pitch_offset;
278 u32 depth_pitch_offset;
279
280 drm_radeon_depth_clear_t depth_clear;
281
282 unsigned long ring_offset;
283 unsigned long ring_rptr_offset;
284 unsigned long buffers_offset;
285 unsigned long gart_textures_offset;
286
287 drm_local_map_t *sarea;
288 drm_local_map_t *mmio;
289 drm_local_map_t *cp_ring;
290 drm_local_map_t *ring_rptr;
291 drm_local_map_t *gart_textures;
292
293 struct mem_block *gart_heap;
294 struct mem_block *fb_heap;
295
296 /* SW interrupt */
297 wait_queue_head_t swi_queue;
298 atomic_t swi_emitted;
299 int vblank_crtc;
300 uint32_t irq_enable_reg;
301 int irq_enabled;
302 uint32_t r500_disp_irq_reg;
303
304 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
305 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
306
307 unsigned long pcigart_offset;
308 unsigned int pcigart_offset_set;
309 struct drm_ati_pcigart_info gart_info;
310
311 u32 scratch_ages[5];
312
313 /* starting from here on, data is preserved accross an open */
314 uint32_t flags; /* see radeon_chip_flags */
315 unsigned long fb_aper_offset;
316
317 int num_gb_pipes;
318 int track_flush;
319 } drm_radeon_private_t;
320
321 typedef struct drm_radeon_buf_priv {
322 u32 age;
323 } drm_radeon_buf_priv_t;
324
325 typedef struct drm_radeon_kcmd_buffer {
326 int bufsz;
327 char *buf;
328 int nbox;
329 struct drm_clip_rect __user *boxes;
330 } drm_radeon_kcmd_buffer_t;
331
332 extern int radeon_no_wb;
333 extern struct drm_ioctl_desc radeon_ioctls[];
334 extern int radeon_max_ioctl;
335
336 /* Check whether the given hardware address is inside the framebuffer or the
337 * GART area.
338 */
339 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
340 u64 off)
341 {
342 u32 fb_start = dev_priv->fb_location;
343 u32 fb_end = fb_start + dev_priv->fb_size - 1;
344 u32 gart_start = dev_priv->gart_vm_start;
345 u32 gart_end = gart_start + dev_priv->gart_size - 1;
346
347 return ((off >= fb_start && off <= fb_end) ||
348 (off >= gart_start && off <= gart_end));
349 }
350
351 /* radeon_cp.c */
352 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
353 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
354 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
355 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
356 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
357 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
358 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
359 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
360 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
361 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
362
363 extern void radeon_freelist_reset(struct drm_device * dev);
364 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
365
366 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
367
368 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
369
370 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
371 extern int radeon_presetup(struct drm_device *dev);
372 extern int radeon_driver_postcleanup(struct drm_device *dev);
373
374 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
375 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
376 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
377 extern void radeon_mem_takedown(struct mem_block **heap);
378 extern void radeon_mem_release(struct drm_file *file_priv,
379 struct mem_block *heap);
380
381 /* radeon_irq.c */
382 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
383 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
384 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
385
386 extern void radeon_do_release(struct drm_device * dev);
387 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc);
388 extern int radeon_enable_vblank(struct drm_device *dev, int crtc);
389 extern void radeon_disable_vblank(struct drm_device *dev, int crtc);
390 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
391 extern void radeon_driver_irq_preinstall(struct drm_device * dev);
392 extern int radeon_driver_irq_postinstall(struct drm_device *dev);
393 extern void radeon_driver_irq_uninstall(struct drm_device * dev);
394 extern void radeon_enable_interrupt(struct drm_device *dev);
395 extern int radeon_vblank_crtc_get(struct drm_device *dev);
396 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
397
398 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
399 extern int radeon_driver_unload(struct drm_device *dev);
400 extern int radeon_driver_firstopen(struct drm_device *dev);
401 extern void radeon_driver_preclose(struct drm_device *dev,
402 struct drm_file *file_priv);
403 extern void radeon_driver_postclose(struct drm_device *dev,
404 struct drm_file *file_priv);
405 extern void radeon_driver_lastclose(struct drm_device * dev);
406 extern int radeon_driver_open(struct drm_device *dev,
407 struct drm_file *file_priv);
408 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
409 unsigned long arg);
410
411 /* r300_cmdbuf.c */
412 extern void r300_init_reg_flags(struct drm_device *dev);
413
414 extern int r300_do_cp_cmdbuf(struct drm_device *dev,
415 struct drm_file *file_priv,
416 drm_radeon_kcmd_buffer_t *cmdbuf);
417
418 /* Flags for stats.boxes
419 */
420 #define RADEON_BOX_DMA_IDLE 0x1
421 #define RADEON_BOX_RING_FULL 0x2
422 #define RADEON_BOX_FLIP 0x4
423 #define RADEON_BOX_WAIT_IDLE 0x8
424 #define RADEON_BOX_TEXTURE_LOAD 0x10
425
426 /* Register definitions, register access macros and drmAddMap constants
427 * for Radeon kernel driver.
428 */
429
430 #define RADEON_AGP_COMMAND 0x0f60
431 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
432 # define RADEON_AGP_ENABLE (1<<8)
433 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
434 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
435 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
436 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
437 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
438 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
439 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
440
441 #define RADEON_BUS_CNTL 0x0030
442 # define RADEON_BUS_MASTER_DIS (1 << 6)
443
444 #define RADEON_CLOCK_CNTL_DATA 0x000c
445 # define RADEON_PLL_WR_EN (1 << 7)
446 #define RADEON_CLOCK_CNTL_INDEX 0x0008
447 #define RADEON_CONFIG_APER_SIZE 0x0108
448 #define RADEON_CONFIG_MEMSIZE 0x00f8
449 #define RADEON_CRTC_OFFSET 0x0224
450 #define RADEON_CRTC_OFFSET_CNTL 0x0228
451 # define RADEON_CRTC_TILE_EN (1 << 15)
452 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
453 #define RADEON_CRTC2_OFFSET 0x0324
454 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
455
456 #define RADEON_PCIE_INDEX 0x0030
457 #define RADEON_PCIE_DATA 0x0034
458 #define RADEON_PCIE_TX_GART_CNTL 0x10
459 # define RADEON_PCIE_TX_GART_EN (1 << 0)
460 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
461 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
462 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
463 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
464 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
465 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
466 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
467 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
468 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
469 #define RADEON_PCIE_TX_GART_BASE 0x13
470 #define RADEON_PCIE_TX_GART_START_LO 0x14
471 #define RADEON_PCIE_TX_GART_START_HI 0x15
472 #define RADEON_PCIE_TX_GART_END_LO 0x16
473 #define RADEON_PCIE_TX_GART_END_HI 0x17
474
475 #define RS480_NB_MC_INDEX 0x168
476 # define RS480_NB_MC_IND_WR_EN (1 << 8)
477 #define RS480_NB_MC_DATA 0x16c
478
479 #define RS690_MC_INDEX 0x78
480 # define RS690_MC_INDEX_MASK 0x1ff
481 # define RS690_MC_INDEX_WR_EN (1 << 9)
482 # define RS690_MC_INDEX_WR_ACK 0x7f
483 #define RS690_MC_DATA 0x7c
484
485 /* MC indirect registers */
486 #define RS480_MC_MISC_CNTL 0x18
487 # define RS480_DISABLE_GTW (1 << 1)
488 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
489 # define RS480_GART_INDEX_REG_EN (1 << 12)
490 # define RS690_BLOCK_GFX_D3_EN (1 << 14)
491 #define RS480_K8_FB_LOCATION 0x1e
492 #define RS480_GART_FEATURE_ID 0x2b
493 # define RS480_HANG_EN (1 << 11)
494 # define RS480_TLB_ENABLE (1 << 18)
495 # define RS480_P2P_ENABLE (1 << 19)
496 # define RS480_GTW_LAC_EN (1 << 25)
497 # define RS480_2LEVEL_GART (0 << 30)
498 # define RS480_1LEVEL_GART (1 << 30)
499 # define RS480_PDC_EN (1 << 31)
500 #define RS480_GART_BASE 0x2c
501 #define RS480_GART_CACHE_CNTRL 0x2e
502 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
503 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
504 # define RS480_GART_EN (1 << 0)
505 # define RS480_VA_SIZE_32MB (0 << 1)
506 # define RS480_VA_SIZE_64MB (1 << 1)
507 # define RS480_VA_SIZE_128MB (2 << 1)
508 # define RS480_VA_SIZE_256MB (3 << 1)
509 # define RS480_VA_SIZE_512MB (4 << 1)
510 # define RS480_VA_SIZE_1GB (5 << 1)
511 # define RS480_VA_SIZE_2GB (6 << 1)
512 #define RS480_AGP_MODE_CNTL 0x39
513 # define RS480_POST_GART_Q_SIZE (1 << 18)
514 # define RS480_NONGART_SNOOP (1 << 19)
515 # define RS480_AGP_RD_BUF_SIZE (1 << 20)
516 # define RS480_REQ_TYPE_SNOOP_SHIFT 22
517 # define RS480_REQ_TYPE_SNOOP_MASK 0x3
518 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
519 #define RS480_MC_MISC_UMA_CNTL 0x5f
520 #define RS480_MC_MCLK_CNTL 0x7a
521 #define RS480_MC_UMA_DUALCH_CNTL 0x86
522
523 #define RS690_MC_FB_LOCATION 0x100
524 #define RS690_MC_AGP_LOCATION 0x101
525 #define RS690_MC_AGP_BASE 0x102
526 #define RS690_MC_AGP_BASE_2 0x103
527
528 #define R520_MC_IND_INDEX 0x70
529 #define R520_MC_IND_WR_EN (1 << 24)
530 #define R520_MC_IND_DATA 0x74
531
532 #define RV515_MC_FB_LOCATION 0x01
533 #define RV515_MC_AGP_LOCATION 0x02
534 #define RV515_MC_AGP_BASE 0x03
535 #define RV515_MC_AGP_BASE_2 0x04
536
537 #define R520_MC_FB_LOCATION 0x04
538 #define R520_MC_AGP_LOCATION 0x05
539 #define R520_MC_AGP_BASE 0x06
540 #define R520_MC_AGP_BASE_2 0x07
541
542 #define RADEON_MPP_TB_CONFIG 0x01c0
543 #define RADEON_MEM_CNTL 0x0140
544 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
545 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
546 #define RS480_AGP_BASE_2 0x0164
547 #define RADEON_AGP_BASE 0x0170
548
549 /* pipe config regs */
550 #define R400_GB_PIPE_SELECT 0x402c
551 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
552 #define R500_SU_REG_DEST 0x42c8
553 #define R300_GB_TILE_CONFIG 0x4018
554 # define R300_ENABLE_TILING (1 << 0)
555 # define R300_PIPE_COUNT_RV350 (0 << 1)
556 # define R300_PIPE_COUNT_R300 (3 << 1)
557 # define R300_PIPE_COUNT_R420_3P (6 << 1)
558 # define R300_PIPE_COUNT_R420 (7 << 1)
559 # define R300_TILE_SIZE_8 (0 << 4)
560 # define R300_TILE_SIZE_16 (1 << 4)
561 # define R300_TILE_SIZE_32 (2 << 4)
562 # define R300_SUBPIXEL_1_12 (0 << 16)
563 # define R300_SUBPIXEL_1_16 (1 << 16)
564 #define R300_DST_PIPE_CONFIG 0x170c
565 # define R300_PIPE_AUTO_CONFIG (1 << 31)
566 #define R300_RB2D_DSTCACHE_MODE 0x3428
567 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
568 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
569
570 #define RADEON_RB3D_COLOROFFSET 0x1c40
571 #define RADEON_RB3D_COLORPITCH 0x1c48
572
573 #define RADEON_SRC_X_Y 0x1590
574
575 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
576 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
577 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
578 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
579 # define RADEON_GMC_BRUSH_NONE (15 << 4)
580 # define RADEON_GMC_DST_16BPP (4 << 8)
581 # define RADEON_GMC_DST_24BPP (5 << 8)
582 # define RADEON_GMC_DST_32BPP (6 << 8)
583 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
584 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
585 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
586 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
587 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
588 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
589 # define RADEON_ROP3_S 0x00cc0000
590 # define RADEON_ROP3_P 0x00f00000
591 #define RADEON_DP_WRITE_MASK 0x16cc
592 #define RADEON_SRC_PITCH_OFFSET 0x1428
593 #define RADEON_DST_PITCH_OFFSET 0x142c
594 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
595 # define RADEON_DST_TILE_LINEAR (0 << 30)
596 # define RADEON_DST_TILE_MACRO (1 << 30)
597 # define RADEON_DST_TILE_MICRO (2 << 30)
598 # define RADEON_DST_TILE_BOTH (3 << 30)
599
600 #define RADEON_SCRATCH_REG0 0x15e0
601 #define RADEON_SCRATCH_REG1 0x15e4
602 #define RADEON_SCRATCH_REG2 0x15e8
603 #define RADEON_SCRATCH_REG3 0x15ec
604 #define RADEON_SCRATCH_REG4 0x15f0
605 #define RADEON_SCRATCH_REG5 0x15f4
606 #define RADEON_SCRATCH_UMSK 0x0770
607 #define RADEON_SCRATCH_ADDR 0x0774
608
609 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
610
611 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
612 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
613 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
614
615 #define RADEON_GEN_INT_CNTL 0x0040
616 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
617 # define RADEON_CRTC2_VBLANK_MASK (1 << 9)
618 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
619 # define RADEON_SW_INT_ENABLE (1 << 25)
620
621 #define RADEON_GEN_INT_STATUS 0x0044
622 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
623 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
624 # define RADEON_CRTC2_VBLANK_STAT (1 << 9)
625 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
626 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
627 # define RADEON_SW_INT_TEST (1 << 25)
628 # define RADEON_SW_INT_TEST_ACK (1 << 25)
629 # define RADEON_SW_INT_FIRE (1 << 26)
630 # define R500_DISPLAY_INT_STATUS (1 << 0)
631
632 #define RADEON_HOST_PATH_CNTL 0x0130
633 # define RADEON_HDP_SOFT_RESET (1 << 26)
634 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
635 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
636
637 #define RADEON_ISYNC_CNTL 0x1724
638 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
639 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
640 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
641 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
642 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
643 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
644
645 #define RADEON_RBBM_GUICNTL 0x172c
646 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
647 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
648 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
649 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
650
651 #define RADEON_MC_AGP_LOCATION 0x014c
652 #define RADEON_MC_FB_LOCATION 0x0148
653 #define RADEON_MCLK_CNTL 0x0012
654 # define RADEON_FORCEON_MCLKA (1 << 16)
655 # define RADEON_FORCEON_MCLKB (1 << 17)
656 # define RADEON_FORCEON_YCLKA (1 << 18)
657 # define RADEON_FORCEON_YCLKB (1 << 19)
658 # define RADEON_FORCEON_MC (1 << 20)
659 # define RADEON_FORCEON_AIC (1 << 21)
660
661 #define RADEON_PP_BORDER_COLOR_0 0x1d40
662 #define RADEON_PP_BORDER_COLOR_1 0x1d44
663 #define RADEON_PP_BORDER_COLOR_2 0x1d48
664 #define RADEON_PP_CNTL 0x1c38
665 # define RADEON_SCISSOR_ENABLE (1 << 1)
666 #define RADEON_PP_LUM_MATRIX 0x1d00
667 #define RADEON_PP_MISC 0x1c14
668 #define RADEON_PP_ROT_MATRIX_0 0x1d58
669 #define RADEON_PP_TXFILTER_0 0x1c54
670 #define RADEON_PP_TXOFFSET_0 0x1c5c
671 #define RADEON_PP_TXFILTER_1 0x1c6c
672 #define RADEON_PP_TXFILTER_2 0x1c84
673
674 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
675 #define R300_DSTCACHE_CTLSTAT 0x1714
676 # define R300_RB2D_DC_FLUSH (3 << 0)
677 # define R300_RB2D_DC_FREE (3 << 2)
678 # define R300_RB2D_DC_FLUSH_ALL 0xf
679 # define R300_RB2D_DC_BUSY (1 << 31)
680 #define RADEON_RB3D_CNTL 0x1c3c
681 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
682 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
683 # define RADEON_DITHER_ENABLE (1 << 2)
684 # define RADEON_ROUND_ENABLE (1 << 3)
685 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
686 # define RADEON_DITHER_INIT (1 << 5)
687 # define RADEON_ROP_ENABLE (1 << 6)
688 # define RADEON_STENCIL_ENABLE (1 << 7)
689 # define RADEON_Z_ENABLE (1 << 8)
690 # define RADEON_ZBLOCK16 (1 << 15)
691 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
692 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
693 #define RADEON_RB3D_DEPTHPITCH 0x1c28
694 #define RADEON_RB3D_PLANEMASK 0x1d84
695 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
696 #define RADEON_RB3D_ZCACHE_MODE 0x3250
697 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
698 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
699 # define RADEON_RB3D_ZC_FREE (1 << 2)
700 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
701 # define RADEON_RB3D_ZC_BUSY (1 << 31)
702 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18
703 # define R300_ZC_FLUSH (1 << 0)
704 # define R300_ZC_FREE (1 << 1)
705 # define R300_ZC_BUSY (1 << 31)
706 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
707 # define RADEON_RB3D_DC_FLUSH (3 << 0)
708 # define RADEON_RB3D_DC_FREE (3 << 2)
709 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
710 # define RADEON_RB3D_DC_BUSY (1 << 31)
711 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
712 # define R300_RB3D_DC_FLUSH (2 << 0)
713 # define R300_RB3D_DC_FREE (2 << 2)
714 # define R300_RB3D_DC_FINISH (1 << 4)
715 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
716 # define RADEON_Z_TEST_MASK (7 << 4)
717 # define RADEON_Z_TEST_ALWAYS (7 << 4)
718 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
719 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
720 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
721 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
722 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
723 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
724 # define RADEON_FORCE_Z_DIRTY (1 << 29)
725 # define RADEON_Z_WRITE_ENABLE (1 << 30)
726 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
727 #define RADEON_RBBM_SOFT_RESET 0x00f0
728 # define RADEON_SOFT_RESET_CP (1 << 0)
729 # define RADEON_SOFT_RESET_HI (1 << 1)
730 # define RADEON_SOFT_RESET_SE (1 << 2)
731 # define RADEON_SOFT_RESET_RE (1 << 3)
732 # define RADEON_SOFT_RESET_PP (1 << 4)
733 # define RADEON_SOFT_RESET_E2 (1 << 5)
734 # define RADEON_SOFT_RESET_RB (1 << 6)
735 # define RADEON_SOFT_RESET_HDP (1 << 7)
736 /*
737 * 6:0 Available slots in the FIFO
738 * 8 Host Interface active
739 * 9 CP request active
740 * 10 FIFO request active
741 * 11 Host Interface retry active
742 * 12 CP retry active
743 * 13 FIFO retry active
744 * 14 FIFO pipeline busy
745 * 15 Event engine busy
746 * 16 CP command stream busy
747 * 17 2D engine busy
748 * 18 2D portion of render backend busy
749 * 20 3D setup engine busy
750 * 26 GA engine busy
751 * 27 CBA 2D engine busy
752 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
753 * command stream queue not empty or Ring Buffer not empty
754 */
755 #define RADEON_RBBM_STATUS 0x0e40
756 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
757 /* #define RADEON_RBBM_STATUS 0x1740 */
758 /* bits 6:0 are dword slots available in the cmd fifo */
759 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
760 # define RADEON_HIRQ_ON_RBB (1 << 8)
761 # define RADEON_CPRQ_ON_RBB (1 << 9)
762 # define RADEON_CFRQ_ON_RBB (1 << 10)
763 # define RADEON_HIRQ_IN_RTBUF (1 << 11)
764 # define RADEON_CPRQ_IN_RTBUF (1 << 12)
765 # define RADEON_CFRQ_IN_RTBUF (1 << 13)
766 # define RADEON_PIPE_BUSY (1 << 14)
767 # define RADEON_ENG_EV_BUSY (1 << 15)
768 # define RADEON_CP_CMDSTRM_BUSY (1 << 16)
769 # define RADEON_E2_BUSY (1 << 17)
770 # define RADEON_RB2D_BUSY (1 << 18)
771 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
772 # define RADEON_VAP_BUSY (1 << 20)
773 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
774 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
775 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
776 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
777 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
778 # define RADEON_GA_BUSY (1 << 26)
779 # define RADEON_CBA2D_BUSY (1 << 27)
780 # define RADEON_RBBM_ACTIVE (1 << 31)
781 #define RADEON_RE_LINE_PATTERN 0x1cd0
782 #define RADEON_RE_MISC 0x26c4
783 #define RADEON_RE_TOP_LEFT 0x26c0
784 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
785 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
786 #define RADEON_RE_STIPPLE_DATA 0x1ccc
787
788 #define RADEON_SCISSOR_TL_0 0x1cd8
789 #define RADEON_SCISSOR_BR_0 0x1cdc
790 #define RADEON_SCISSOR_TL_1 0x1ce0
791 #define RADEON_SCISSOR_BR_1 0x1ce4
792 #define RADEON_SCISSOR_TL_2 0x1ce8
793 #define RADEON_SCISSOR_BR_2 0x1cec
794 #define RADEON_SE_COORD_FMT 0x1c50
795 #define RADEON_SE_CNTL 0x1c4c
796 # define RADEON_FFACE_CULL_CW (0 << 0)
797 # define RADEON_BFACE_SOLID (3 << 1)
798 # define RADEON_FFACE_SOLID (3 << 3)
799 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
800 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
801 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
802 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
803 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
804 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
805 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
806 # define RADEON_FOG_SHADE_FLAT (1 << 14)
807 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
808 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
809 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
810 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
811 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
812 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
813 #define RADEON_SE_CNTL_STATUS 0x2140
814 #define RADEON_SE_LINE_WIDTH 0x1db8
815 #define RADEON_SE_VPORT_XSCALE 0x1d98
816 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
817 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
818 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
819 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
820 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
821 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
822 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
823 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
824 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
825 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
826 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
827 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
828 #define RADEON_SURFACE_CNTL 0x0b00
829 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
830 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
831 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
832 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
833 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
834 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
835 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
836 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
837 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
838 #define RADEON_SURFACE0_INFO 0x0b0c
839 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
840 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
841 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
842 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
843 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
844 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
845 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
846 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
847 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
848 #define RADEON_SURFACE1_INFO 0x0b1c
849 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
850 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
851 #define RADEON_SURFACE2_INFO 0x0b2c
852 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
853 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
854 #define RADEON_SURFACE3_INFO 0x0b3c
855 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
856 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
857 #define RADEON_SURFACE4_INFO 0x0b4c
858 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
859 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
860 #define RADEON_SURFACE5_INFO 0x0b5c
861 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
862 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
863 #define RADEON_SURFACE6_INFO 0x0b6c
864 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
865 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
866 #define RADEON_SURFACE7_INFO 0x0b7c
867 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
868 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
869 #define RADEON_SW_SEMAPHORE 0x013c
870
871 #define RADEON_WAIT_UNTIL 0x1720
872 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
873 # define RADEON_WAIT_2D_IDLE (1 << 14)
874 # define RADEON_WAIT_3D_IDLE (1 << 15)
875 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
876 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
877 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
878
879 #define RADEON_RB3D_ZMASKOFFSET 0x3234
880 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
881 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
882 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
883
884 /* CP registers */
885 #define RADEON_CP_ME_RAM_ADDR 0x07d4
886 #define RADEON_CP_ME_RAM_RADDR 0x07d8
887 #define RADEON_CP_ME_RAM_DATAH 0x07dc
888 #define RADEON_CP_ME_RAM_DATAL 0x07e0
889
890 #define RADEON_CP_RB_BASE 0x0700
891 #define RADEON_CP_RB_CNTL 0x0704
892 # define RADEON_BUF_SWAP_32BIT (2 << 16)
893 # define RADEON_RB_NO_UPDATE (1 << 27)
894 #define RADEON_CP_RB_RPTR_ADDR 0x070c
895 #define RADEON_CP_RB_RPTR 0x0710
896 #define RADEON_CP_RB_WPTR 0x0714
897
898 #define RADEON_CP_RB_WPTR_DELAY 0x0718
899 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
900 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
901
902 #define RADEON_CP_IB_BASE 0x0738
903
904 #define RADEON_CP_CSQ_CNTL 0x0740
905 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
906 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
907 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
908 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
909 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
910 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
911 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
912
913 #define RADEON_AIC_CNTL 0x01d0
914 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
915 #define RADEON_AIC_STAT 0x01d4
916 #define RADEON_AIC_PT_BASE 0x01d8
917 #define RADEON_AIC_LO_ADDR 0x01dc
918 #define RADEON_AIC_HI_ADDR 0x01e0
919 #define RADEON_AIC_TLB_ADDR 0x01e4
920 #define RADEON_AIC_TLB_DATA 0x01e8
921
922 /* CP command packets */
923 #define RADEON_CP_PACKET0 0x00000000
924 # define RADEON_ONE_REG_WR (1 << 15)
925 #define RADEON_CP_PACKET1 0x40000000
926 #define RADEON_CP_PACKET2 0x80000000
927 #define RADEON_CP_PACKET3 0xC0000000
928 # define RADEON_CP_NOP 0x00001000
929 # define RADEON_CP_NEXT_CHAR 0x00001900
930 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
931 # define RADEON_CP_SET_SCISSORS 0x00001E00
932 /* GEN_INDX_PRIM is unsupported starting with R300 */
933 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
934 # define RADEON_WAIT_FOR_IDLE 0x00002600
935 # define RADEON_3D_DRAW_VBUF 0x00002800
936 # define RADEON_3D_DRAW_IMMD 0x00002900
937 # define RADEON_3D_DRAW_INDX 0x00002A00
938 # define RADEON_CP_LOAD_PALETTE 0x00002C00
939 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
940 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
941 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
942 # define RADEON_3D_CLEAR_ZMASK 0x00003200
943 # define RADEON_CP_INDX_BUFFER 0x00003300
944 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
945 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
946 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
947 # define RADEON_3D_CLEAR_HIZ 0x00003700
948 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
949 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
950 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
951 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
952 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
953
954 #define RADEON_CP_PACKET_MASK 0xC0000000
955 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
956 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
957 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
958 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
959
960 #define RADEON_VTX_Z_PRESENT (1 << 31)
961 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
962
963 #define RADEON_PRIM_TYPE_NONE (0 << 0)
964 #define RADEON_PRIM_TYPE_POINT (1 << 0)
965 #define RADEON_PRIM_TYPE_LINE (2 << 0)
966 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
967 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
968 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
969 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
970 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
971 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
972 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
973 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
974 #define RADEON_PRIM_TYPE_MASK 0xf
975 #define RADEON_PRIM_WALK_IND (1 << 4)
976 #define RADEON_PRIM_WALK_LIST (2 << 4)
977 #define RADEON_PRIM_WALK_RING (3 << 4)
978 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
979 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
980 #define RADEON_MAOS_ENABLE (1 << 7)
981 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
982 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
983 #define RADEON_NUM_VERTICES_SHIFT 16
984
985 #define RADEON_COLOR_FORMAT_CI8 2
986 #define RADEON_COLOR_FORMAT_ARGB1555 3
987 #define RADEON_COLOR_FORMAT_RGB565 4
988 #define RADEON_COLOR_FORMAT_ARGB8888 6
989 #define RADEON_COLOR_FORMAT_RGB332 7
990 #define RADEON_COLOR_FORMAT_RGB8 9
991 #define RADEON_COLOR_FORMAT_ARGB4444 15
992
993 #define RADEON_TXFORMAT_I8 0
994 #define RADEON_TXFORMAT_AI88 1
995 #define RADEON_TXFORMAT_RGB332 2
996 #define RADEON_TXFORMAT_ARGB1555 3
997 #define RADEON_TXFORMAT_RGB565 4
998 #define RADEON_TXFORMAT_ARGB4444 5
999 #define RADEON_TXFORMAT_ARGB8888 6
1000 #define RADEON_TXFORMAT_RGBA8888 7
1001 #define RADEON_TXFORMAT_Y8 8
1002 #define RADEON_TXFORMAT_VYUY422 10
1003 #define RADEON_TXFORMAT_YVYU422 11
1004 #define RADEON_TXFORMAT_DXT1 12
1005 #define RADEON_TXFORMAT_DXT23 14
1006 #define RADEON_TXFORMAT_DXT45 15
1007
1008 #define R200_PP_TXCBLEND_0 0x2f00
1009 #define R200_PP_TXCBLEND_1 0x2f10
1010 #define R200_PP_TXCBLEND_2 0x2f20
1011 #define R200_PP_TXCBLEND_3 0x2f30
1012 #define R200_PP_TXCBLEND_4 0x2f40
1013 #define R200_PP_TXCBLEND_5 0x2f50
1014 #define R200_PP_TXCBLEND_6 0x2f60
1015 #define R200_PP_TXCBLEND_7 0x2f70
1016 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1017 #define R200_PP_TFACTOR_0 0x2ee0
1018 #define R200_SE_VTX_FMT_0 0x2088
1019 #define R200_SE_VAP_CNTL 0x2080
1020 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
1021 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1022 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1023 #define R200_PP_TXFILTER_5 0x2ca0
1024 #define R200_PP_TXFILTER_4 0x2c80
1025 #define R200_PP_TXFILTER_3 0x2c60
1026 #define R200_PP_TXFILTER_2 0x2c40
1027 #define R200_PP_TXFILTER_1 0x2c20
1028 #define R200_PP_TXFILTER_0 0x2c00
1029 #define R200_PP_TXOFFSET_5 0x2d78
1030 #define R200_PP_TXOFFSET_4 0x2d60
1031 #define R200_PP_TXOFFSET_3 0x2d48
1032 #define R200_PP_TXOFFSET_2 0x2d30
1033 #define R200_PP_TXOFFSET_1 0x2d18
1034 #define R200_PP_TXOFFSET_0 0x2d00
1035
1036 #define R200_PP_CUBIC_FACES_0 0x2c18
1037 #define R200_PP_CUBIC_FACES_1 0x2c38
1038 #define R200_PP_CUBIC_FACES_2 0x2c58
1039 #define R200_PP_CUBIC_FACES_3 0x2c78
1040 #define R200_PP_CUBIC_FACES_4 0x2c98
1041 #define R200_PP_CUBIC_FACES_5 0x2cb8
1042 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1043 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1044 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1045 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1046 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1047 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1048 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1049 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1050 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1051 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1052 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1053 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1054 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1055 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1056 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1057 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1058 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1059 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1060 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1061 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1062 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1063 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1064 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1065 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1066 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1067 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1068 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1069 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1070 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1071 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1072
1073 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1074 #define R200_SE_VTE_CNTL 0x20b0
1075 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1076 #define R200_PP_TAM_DEBUG3 0x2d9c
1077 #define R200_PP_CNTL_X 0x2cc4
1078 #define R200_SE_VAP_CNTL_STATUS 0x2140
1079 #define R200_RE_SCISSOR_TL_0 0x1cd8
1080 #define R200_RE_SCISSOR_TL_1 0x1ce0
1081 #define R200_RE_SCISSOR_TL_2 0x1ce8
1082 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1083 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1084 #define R200_SE_VTX_STATE_CNTL 0x2180
1085 #define R200_RE_POINTSIZE 0x2648
1086 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1087
1088 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1089 #define RADEON_PP_TEX_SIZE_1 0x1d0c
1090 #define RADEON_PP_TEX_SIZE_2 0x1d14
1091
1092 #define RADEON_PP_CUBIC_FACES_0 0x1d24
1093 #define RADEON_PP_CUBIC_FACES_1 0x1d28
1094 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
1095 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1096 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1097 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1098
1099 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
1100
1101 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1102 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1103 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1104 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1105 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1106 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1107 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1108 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1109 #define R200_3D_DRAW_IMMD_2 0xC0003500
1110 #define R200_SE_VTX_FMT_1 0x208c
1111 #define R200_RE_CNTL 0x1c50
1112
1113 #define R200_RB3D_BLENDCOLOR 0x3218
1114
1115 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1116
1117 #define R200_PP_TRI_PERF 0x2cf8
1118
1119 #define R200_PP_AFS_0 0x2f80
1120 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1121
1122 #define R200_VAP_PVS_CNTL_1 0x22D0
1123
1124 #define RADEON_CRTC_CRNT_FRAME 0x0214
1125 #define RADEON_CRTC2_CRNT_FRAME 0x0314
1126
1127 #define R500_D1CRTC_STATUS 0x609c
1128 #define R500_D2CRTC_STATUS 0x689c
1129 #define R500_CRTC_V_BLANK (1<<0)
1130
1131 #define R500_D1CRTC_FRAME_COUNT 0x60a4
1132 #define R500_D2CRTC_FRAME_COUNT 0x68a4
1133
1134 #define R500_D1MODE_V_COUNTER 0x6530
1135 #define R500_D2MODE_V_COUNTER 0x6d30
1136
1137 #define R500_D1MODE_VBLANK_STATUS 0x6534
1138 #define R500_D2MODE_VBLANK_STATUS 0x6d34
1139 #define R500_VBLANK_OCCURED (1<<0)
1140 #define R500_VBLANK_ACK (1<<4)
1141 #define R500_VBLANK_STAT (1<<12)
1142 #define R500_VBLANK_INT (1<<16)
1143
1144 #define R500_DxMODE_INT_MASK 0x6540
1145 #define R500_D1MODE_INT_MASK (1<<0)
1146 #define R500_D2MODE_INT_MASK (1<<8)
1147
1148 #define R500_DISP_INTERRUPT_STATUS 0x7edc
1149 #define R500_D1_VBLANK_INTERRUPT (1 << 4)
1150 #define R500_D2_VBLANK_INTERRUPT (1 << 5)
1151
1152 /* Constants */
1153 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1154
1155 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1156 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1157 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1158 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1159 #define RADEON_LAST_DISPATCH 1
1160
1161 #define RADEON_MAX_VB_AGE 0x7fffffff
1162 #define RADEON_MAX_VB_VERTS (0xffff)
1163
1164 #define RADEON_RING_HIGH_MARK 128
1165
1166 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
1167
1168 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1169 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
1170 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1171 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1172
1173 #define RADEON_WRITE_PLL(addr, val) \
1174 do { \
1175 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1176 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1177 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1178 } while (0)
1179
1180 #define RADEON_WRITE_PCIE(addr, val) \
1181 do { \
1182 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1183 ((addr) & 0xff)); \
1184 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1185 } while (0)
1186
1187 #define R500_WRITE_MCIND(addr, val) \
1188 do { \
1189 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1190 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1191 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1192 } while (0)
1193
1194 #define RS480_WRITE_MCIND(addr, val) \
1195 do { \
1196 RADEON_WRITE(RS480_NB_MC_INDEX, \
1197 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1198 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1199 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1200 } while (0)
1201
1202 #define RS690_WRITE_MCIND(addr, val) \
1203 do { \
1204 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1205 RADEON_WRITE(RS690_MC_DATA, val); \
1206 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1207 } while (0)
1208
1209 #define IGP_WRITE_MCIND(addr, val) \
1210 do { \
1211 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1212 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1213 RS690_WRITE_MCIND(addr, val); \
1214 else \
1215 RS480_WRITE_MCIND(addr, val); \
1216 } while (0)
1217
1218 #define CP_PACKET0( reg, n ) \
1219 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1220 #define CP_PACKET0_TABLE( reg, n ) \
1221 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1222 #define CP_PACKET1( reg0, reg1 ) \
1223 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1224 #define CP_PACKET2() \
1225 (RADEON_CP_PACKET2)
1226 #define CP_PACKET3( pkt, n ) \
1227 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1228
1229 /* ================================================================
1230 * Engine control helper macros
1231 */
1232
1233 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1234 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1235 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1236 RADEON_WAIT_HOST_IDLECLEAN) ); \
1237 } while (0)
1238
1239 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1240 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1241 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1242 RADEON_WAIT_HOST_IDLECLEAN) ); \
1243 } while (0)
1244
1245 #define RADEON_WAIT_UNTIL_IDLE() do { \
1246 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1247 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1248 RADEON_WAIT_3D_IDLECLEAN | \
1249 RADEON_WAIT_HOST_IDLECLEAN) ); \
1250 } while (0)
1251
1252 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1253 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1254 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1255 } while (0)
1256
1257 #define RADEON_FLUSH_CACHE() do { \
1258 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1259 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1260 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1261 } else { \
1262 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1263 OUT_RING(R300_RB3D_DC_FLUSH); \
1264 } \
1265 } while (0)
1266
1267 #define RADEON_PURGE_CACHE() do { \
1268 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1269 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1270 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1271 } else { \
1272 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1273 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1274 } \
1275 } while (0)
1276
1277 #define RADEON_FLUSH_ZCACHE() do { \
1278 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1279 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1280 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1281 } else { \
1282 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1283 OUT_RING(R300_ZC_FLUSH); \
1284 } \
1285 } while (0)
1286
1287 #define RADEON_PURGE_ZCACHE() do { \
1288 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1289 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1290 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1291 } else { \
1292 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1293 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1294 } \
1295 } while (0)
1296
1297 /* ================================================================
1298 * Misc helper macros
1299 */
1300
1301 /* Perfbox functionality only.
1302 */
1303 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1304 do { \
1305 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1306 u32 head = GET_RING_HEAD( dev_priv ); \
1307 if (head == dev_priv->ring.tail) \
1308 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1309 } \
1310 } while (0)
1311
1312 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1313 do { \
1314 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1315 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1316 int __ret = radeon_do_cp_idle( dev_priv ); \
1317 if ( __ret ) return __ret; \
1318 sarea_priv->last_dispatch = 0; \
1319 radeon_freelist_reset( dev ); \
1320 } \
1321 } while (0)
1322
1323 #define RADEON_DISPATCH_AGE( age ) do { \
1324 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1325 OUT_RING( age ); \
1326 } while (0)
1327
1328 #define RADEON_FRAME_AGE( age ) do { \
1329 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1330 OUT_RING( age ); \
1331 } while (0)
1332
1333 #define RADEON_CLEAR_AGE( age ) do { \
1334 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1335 OUT_RING( age ); \
1336 } while (0)
1337
1338 /* ================================================================
1339 * Ring control
1340 */
1341
1342 #define RADEON_VERBOSE 0
1343
1344 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1345
1346 #define BEGIN_RING( n ) do { \
1347 if ( RADEON_VERBOSE ) { \
1348 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
1349 } \
1350 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1351 COMMIT_RING(); \
1352 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1353 } \
1354 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1355 ring = dev_priv->ring.start; \
1356 write = dev_priv->ring.tail; \
1357 mask = dev_priv->ring.tail_mask; \
1358 } while (0)
1359
1360 #define ADVANCE_RING() do { \
1361 if ( RADEON_VERBOSE ) { \
1362 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1363 write, dev_priv->ring.tail ); \
1364 } \
1365 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1366 DRM_ERROR( \
1367 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1368 ((dev_priv->ring.tail + _nr) & mask), \
1369 write, __LINE__); \
1370 } else \
1371 dev_priv->ring.tail = write; \
1372 } while (0)
1373
1374 #define COMMIT_RING() do { \
1375 /* Flush writes to ring */ \
1376 DRM_MEMORYBARRIER(); \
1377 GET_RING_HEAD( dev_priv ); \
1378 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1379 /* read from PCI bus to ensure correct posting */ \
1380 RADEON_READ( RADEON_CP_RB_RPTR ); \
1381 } while (0)
1382
1383 #define OUT_RING( x ) do { \
1384 if ( RADEON_VERBOSE ) { \
1385 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1386 (unsigned int)(x), write ); \
1387 } \
1388 ring[write++] = (x); \
1389 write &= mask; \
1390 } while (0)
1391
1392 #define OUT_RING_REG( reg, val ) do { \
1393 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1394 OUT_RING( val ); \
1395 } while (0)
1396
1397 #define OUT_RING_TABLE( tab, sz ) do { \
1398 int _size = (sz); \
1399 int *_tab = (int *)(tab); \
1400 \
1401 if (write + _size > mask) { \
1402 int _i = (mask+1) - write; \
1403 _size -= _i; \
1404 while (_i > 0 ) { \
1405 *(int *)(ring + write) = *_tab++; \
1406 write++; \
1407 _i--; \
1408 } \
1409 write = 0; \
1410 _tab += _i; \
1411 } \
1412 while (_size > 0) { \
1413 *(ring + write) = *_tab++; \
1414 write++; \
1415 _size--; \
1416 } \
1417 write &= mask; \
1418 } while (0)
1419
1420 #endif /* __RADEON_DRV_H__ */
linux 2.6 git repository for openrd