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mpc52xx/wdt: merge WDT code into the GPT driver
[linux-2.6/linux-2.6-openrd.git] / arch / powerpc / include / asm / mpc52xx.h
blobb664ce79a172cb91be4ef79486dbf59c3700fb44
1 /*
2 * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
3 * May need to be cleaned as the port goes on ...
4 *
5 * Copyright (C) 2004-2005 Sylvain Munaut <tnt@246tNt.com>
6 * Copyright (C) 2003 MontaVista, Software, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13 #ifndef __ASM_POWERPC_MPC52xx_H__
14 #define __ASM_POWERPC_MPC52xx_H__
15
16 #ifndef __ASSEMBLY__
17 #include <asm/types.h>
18 #include <asm/prom.h>
19 #include <asm/mpc5xxx.h>
20 #endif /* __ASSEMBLY__ */
21
22 #include <linux/suspend.h>
23
24 /* Variants of the 5200(B) */
25 #define MPC5200_SVR 0x80110010
26 #define MPC5200_SVR_MASK 0xfffffff0
27 #define MPC5200B_SVR 0x80110020
28 #define MPC5200B_SVR_MASK 0xfffffff0
29
30 /* ======================================================================== */
31 /* Structures mapping of some unit register set */
32 /* ======================================================================== */
33
34 #ifndef __ASSEMBLY__
35
36 /* Memory Mapping Control */
37 struct mpc52xx_mmap_ctl {
38 u32 mbar; /* MMAP_CTRL + 0x00 */
39
40 u32 cs0_start; /* MMAP_CTRL + 0x04 */
41 u32 cs0_stop; /* MMAP_CTRL + 0x08 */
42 u32 cs1_start; /* MMAP_CTRL + 0x0c */
43 u32 cs1_stop; /* MMAP_CTRL + 0x10 */
44 u32 cs2_start; /* MMAP_CTRL + 0x14 */
45 u32 cs2_stop; /* MMAP_CTRL + 0x18 */
46 u32 cs3_start; /* MMAP_CTRL + 0x1c */
47 u32 cs3_stop; /* MMAP_CTRL + 0x20 */
48 u32 cs4_start; /* MMAP_CTRL + 0x24 */
49 u32 cs4_stop; /* MMAP_CTRL + 0x28 */
50 u32 cs5_start; /* MMAP_CTRL + 0x2c */
51 u32 cs5_stop; /* MMAP_CTRL + 0x30 */
52
53 u32 sdram0; /* MMAP_CTRL + 0x34 */
54 u32 sdram1; /* MMAP_CTRL + 0X38 */
55
56 u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
57
58 u32 boot_start; /* MMAP_CTRL + 0x4c */
59 u32 boot_stop; /* MMAP_CTRL + 0x50 */
60
61 u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
62
63 u32 cs6_start; /* MMAP_CTRL + 0x58 */
64 u32 cs6_stop; /* MMAP_CTRL + 0x5c */
65 u32 cs7_start; /* MMAP_CTRL + 0x60 */
66 u32 cs7_stop; /* MMAP_CTRL + 0x64 */
67 };
68
69 /* SDRAM control */
70 struct mpc52xx_sdram {
71 u32 mode; /* SDRAM + 0x00 */
72 u32 ctrl; /* SDRAM + 0x04 */
73 u32 config1; /* SDRAM + 0x08 */
74 u32 config2; /* SDRAM + 0x0c */
75 };
76
77 /* SDMA */
78 struct mpc52xx_sdma {
79 u32 taskBar; /* SDMA + 0x00 */
80 u32 currentPointer; /* SDMA + 0x04 */
81 u32 endPointer; /* SDMA + 0x08 */
82 u32 variablePointer; /* SDMA + 0x0c */
83
84 u8 IntVect1; /* SDMA + 0x10 */
85 u8 IntVect2; /* SDMA + 0x11 */
86 u16 PtdCntrl; /* SDMA + 0x12 */
87
88 u32 IntPend; /* SDMA + 0x14 */
89 u32 IntMask; /* SDMA + 0x18 */
90
91 u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
92
93 u8 ipr[32]; /* SDMA + 0x3c .. 0x5b */
94
95 u32 cReqSelect; /* SDMA + 0x5c */
96 u32 task_size0; /* SDMA + 0x60 */
97 u32 task_size1; /* SDMA + 0x64 */
98 u32 MDEDebug; /* SDMA + 0x68 */
99 u32 ADSDebug; /* SDMA + 0x6c */
100 u32 Value1; /* SDMA + 0x70 */
101 u32 Value2; /* SDMA + 0x74 */
102 u32 Control; /* SDMA + 0x78 */
103 u32 Status; /* SDMA + 0x7c */
104 u32 PTDDebug; /* SDMA + 0x80 */
105 };
106
107 /* GPT */
108 struct mpc52xx_gpt {
109 u32 mode; /* GPTx + 0x00 */
110 u32 count; /* GPTx + 0x04 */
111 u32 pwm; /* GPTx + 0x08 */
112 u32 status; /* GPTx + 0X0c */
113 };
114
115 /* GPIO */
116 struct mpc52xx_gpio {
117 u32 port_config; /* GPIO + 0x00 */
118 u32 simple_gpioe; /* GPIO + 0x04 */
119 u32 simple_ode; /* GPIO + 0x08 */
120 u32 simple_ddr; /* GPIO + 0x0c */
121 u32 simple_dvo; /* GPIO + 0x10 */
122 u32 simple_ival; /* GPIO + 0x14 */
123 u8 outo_gpioe; /* GPIO + 0x18 */
124 u8 reserved1[3]; /* GPIO + 0x19 */
125 u8 outo_dvo; /* GPIO + 0x1c */
126 u8 reserved2[3]; /* GPIO + 0x1d */
127 u8 sint_gpioe; /* GPIO + 0x20 */
128 u8 reserved3[3]; /* GPIO + 0x21 */
129 u8 sint_ode; /* GPIO + 0x24 */
130 u8 reserved4[3]; /* GPIO + 0x25 */
131 u8 sint_ddr; /* GPIO + 0x28 */
132 u8 reserved5[3]; /* GPIO + 0x29 */
133 u8 sint_dvo; /* GPIO + 0x2c */
134 u8 reserved6[3]; /* GPIO + 0x2d */
135 u8 sint_inten; /* GPIO + 0x30 */
136 u8 reserved7[3]; /* GPIO + 0x31 */
137 u16 sint_itype; /* GPIO + 0x34 */
138 u16 reserved8; /* GPIO + 0x36 */
139 u8 gpio_control; /* GPIO + 0x38 */
140 u8 reserved9[3]; /* GPIO + 0x39 */
141 u8 sint_istat; /* GPIO + 0x3c */
142 u8 sint_ival; /* GPIO + 0x3d */
143 u8 bus_errs; /* GPIO + 0x3e */
144 u8 reserved10; /* GPIO + 0x3f */
145 };
146
147 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
148 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
149 #define MPC52xx_GPIO_PCI_DIS (1<<15)
150
151 /* GPIO with WakeUp*/
152 struct mpc52xx_gpio_wkup {
153 u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
154 u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
155 u8 wkup_ode; /* GPIO_WKUP + 0x04 */
156 u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
157 u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
158 u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
159 u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
160 u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
161 u8 wkup_inten; /* GPIO_WKUP + 0x10 */
162 u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
163 u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
164 u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
165 u16 wkup_itype; /* GPIO_WKUP + 0x18 */
166 u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
167 u8 wkup_maste; /* GPIO_WKUP + 0x1C */
168 u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
169 u8 wkup_ival; /* GPIO_WKUP + 0x20 */
170 u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
171 u8 wkup_istat; /* GPIO_WKUP + 0x24 */
172 u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
173 };
174
175 /* XLB Bus control */
176 struct mpc52xx_xlb {
177 u8 reserved[0x40];
178 u32 config; /* XLB + 0x40 */
179 u32 version; /* XLB + 0x44 */
180 u32 status; /* XLB + 0x48 */
181 u32 int_enable; /* XLB + 0x4c */
182 u32 addr_capture; /* XLB + 0x50 */
183 u32 bus_sig_capture; /* XLB + 0x54 */
184 u32 addr_timeout; /* XLB + 0x58 */
185 u32 data_timeout; /* XLB + 0x5c */
186 u32 bus_act_timeout; /* XLB + 0x60 */
187 u32 master_pri_enable; /* XLB + 0x64 */
188 u32 master_priority; /* XLB + 0x68 */
189 u32 base_address; /* XLB + 0x6c */
190 u32 snoop_window; /* XLB + 0x70 */
191 };
192
193 #define MPC52xx_XLB_CFG_PLDIS (1 << 31)
194 #define MPC52xx_XLB_CFG_SNOOP (1 << 15)
195
196 /* Clock Distribution control */
197 struct mpc52xx_cdm {
198 u32 jtag_id; /* CDM + 0x00 reg0 read only */
199 u32 rstcfg; /* CDM + 0x04 reg1 read only */
200 u32 breadcrumb; /* CDM + 0x08 reg2 */
201
202 u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
203 u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
204 u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
205 u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
206
207 u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
208 u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
209 u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
210
211 u32 clk_enables; /* CDM + 0x14 reg5 */
212
213 u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
214 u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
215
216 u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
217 u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
218 u8 reserved1; /* CDM + 0x1e reg7 byte2 */
219 u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
220
221 u8 soft_reset; /* CDM + 0x20 u8 byte0 */
222 u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
223 u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
224
225 u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
226 u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
227 u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
228 u8 reserved3; /* CDM + 0x27 reg9 byte3 */
229
230 u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
231 u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
232
233 u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
234 u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
235
236 u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
237 u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
238
239 u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
240 u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
241 };
242
243 /* Interrupt controller Register set */
244 struct mpc52xx_intr {
245 u32 per_mask; /* INTR + 0x00 */
246 u32 per_pri1; /* INTR + 0x04 */
247 u32 per_pri2; /* INTR + 0x08 */
248 u32 per_pri3; /* INTR + 0x0c */
249 u32 ctrl; /* INTR + 0x10 */
250 u32 main_mask; /* INTR + 0x14 */
251 u32 main_pri1; /* INTR + 0x18 */
252 u32 main_pri2; /* INTR + 0x1c */
253 u32 reserved1; /* INTR + 0x20 */
254 u32 enc_status; /* INTR + 0x24 */
255 u32 crit_status; /* INTR + 0x28 */
256 u32 main_status; /* INTR + 0x2c */
257 u32 per_status; /* INTR + 0x30 */
258 u32 reserved2; /* INTR + 0x34 */
259 u32 per_error; /* INTR + 0x38 */
260 };
261
262 #endif /* __ASSEMBLY__ */
263
264
265 /* ========================================================================= */
266 /* Prototypes for MPC52xx sysdev */
267 /* ========================================================================= */
268
269 #ifndef __ASSEMBLY__
270
271 /* mpc52xx_common.c */
272 extern void mpc5200_setup_xlb_arbiter(void);
273 extern void mpc52xx_declare_of_platform_devices(void);
274 extern void mpc52xx_map_common_devices(void);
275 extern int mpc52xx_set_psc_clkdiv(int psc_id, int clkdiv);
276 extern unsigned int mpc52xx_get_xtal_freq(struct device_node *node);
277 extern void mpc52xx_restart(char *cmd);
278
279 /* mpc52xx_gpt.c */
280 struct mpc52xx_gpt_priv;
281 extern struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq);
282 extern int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
283 int continuous);
284 extern u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt);
285 extern int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt);
286
287 /* mpc52xx_lpbfifo.c */
288 #define MPC52XX_LPBFIFO_FLAG_READ (0)
289 #define MPC52XX_LPBFIFO_FLAG_WRITE (1<<0)
290 #define MPC52XX_LPBFIFO_FLAG_NO_INCREMENT (1<<1)
291 #define MPC52XX_LPBFIFO_FLAG_NO_DMA (1<<2)
292 #define MPC52XX_LPBFIFO_FLAG_POLL_DMA (1<<3)
293
294 struct mpc52xx_lpbfifo_request {
295 struct list_head list;
296
297 /* localplus bus address */
298 unsigned int cs;
299 size_t offset;
300
301 /* Memory address */
302 void *data;
303 phys_addr_t data_phys;
304
305 /* Details of transfer */
306 size_t size;
307 size_t pos; /* current position of transfer */
308 int flags;
309
310 /* What to do when finished */
311 void (*callback)(struct mpc52xx_lpbfifo_request *);
312
313 void *priv; /* Driver private data */
314
315 /* statistics */
316 int irq_count;
317 int irq_ticks;
318 u8 last_byte;
319 int buffer_not_done_cnt;
320 };
321
322 extern int mpc52xx_lpbfifo_submit(struct mpc52xx_lpbfifo_request *req);
323 extern void mpc52xx_lpbfifo_abort(struct mpc52xx_lpbfifo_request *req);
324 extern void mpc52xx_lpbfifo_poll(void);
325
326 /* mpc52xx_pic.c */
327 extern void mpc52xx_init_irq(void);
328 extern unsigned int mpc52xx_get_irq(void);
329
330 /* mpc52xx_pci.c */
331 #ifdef CONFIG_PCI
332 extern int __init mpc52xx_add_bridge(struct device_node *node);
333 extern void __init mpc52xx_setup_pci(void);
334 #else
335 static inline void mpc52xx_setup_pci(void) { }
336 #endif
337
338 #endif /* __ASSEMBLY__ */
339
340 #ifdef CONFIG_PM
341 struct mpc52xx_suspend {
342 void (*board_suspend_prepare)(void __iomem *mbar);
343 void (*board_resume_finish)(void __iomem *mbar);
344 };
345
346 extern struct mpc52xx_suspend mpc52xx_suspend;
347 extern int __init mpc52xx_pm_init(void);
348 extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
349
350 #ifdef CONFIG_PPC_LITE5200
351 extern int __init lite5200_pm_init(void);
352
353 /* lite5200 calls mpc5200 suspend functions, so here they are */
354 extern int mpc52xx_pm_prepare(void);
355 extern int mpc52xx_pm_enter(suspend_state_t);
356 extern void mpc52xx_pm_finish(void);
357 extern char saved_sram[0x4000]; /* reuse buffer from mpc52xx suspend */
358 #endif
359 #endif /* CONFIG_PM */
360
361 #endif /* __ASM_POWERPC_MPC52xx_H__ */
362
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