2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/spinlock.h>
34 #include <asm/system.h>
36 #ifdef CONFIG_PPC_PMAC
37 #include <asm/pmac_feature.h>
41 #include "fw-transaction.h"
43 #define DESCRIPTOR_OUTPUT_MORE 0
44 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
45 #define DESCRIPTOR_INPUT_MORE (2 << 12)
46 #define DESCRIPTOR_INPUT_LAST (3 << 12)
47 #define DESCRIPTOR_STATUS (1 << 11)
48 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
49 #define DESCRIPTOR_PING (1 << 7)
50 #define DESCRIPTOR_YY (1 << 6)
51 #define DESCRIPTOR_NO_IRQ (0 << 4)
52 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
53 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
54 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
55 #define DESCRIPTOR_WAIT (3 << 0)
61 __le32 branch_address
;
63 __le16 transfer_status
;
64 } __attribute__((aligned(16)));
66 struct db_descriptor
{
69 __le16 second_req_count
;
70 __le16 first_req_count
;
71 __le32 branch_address
;
72 __le16 second_res_count
;
73 __le16 first_res_count
;
78 } __attribute__((aligned(16)));
80 #define CONTROL_SET(regs) (regs)
81 #define CONTROL_CLEAR(regs) ((regs) + 4)
82 #define COMMAND_PTR(regs) ((regs) + 12)
83 #define CONTEXT_MATCH(regs) ((regs) + 16)
86 struct descriptor descriptor
;
87 struct ar_buffer
*next
;
93 struct ar_buffer
*current_buffer
;
94 struct ar_buffer
*last_buffer
;
97 struct tasklet_struct tasklet
;
102 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
103 struct descriptor
*d
,
104 struct descriptor
*last
);
107 * A buffer that contains a block of DMA-able coherent memory used for
108 * storing a portion of a DMA descriptor program.
110 struct descriptor_buffer
{
111 struct list_head list
;
112 dma_addr_t buffer_bus
;
115 struct descriptor buffer
[0];
119 struct fw_ohci
*ohci
;
121 int total_allocation
;
124 * List of page-sized buffers for storing DMA descriptors.
125 * Head of list contains buffers in use and tail of list contains
128 struct list_head buffer_list
;
131 * Pointer to a buffer inside buffer_list that contains the tail
132 * end of the current DMA program.
134 struct descriptor_buffer
*buffer_tail
;
137 * The descriptor containing the branch address of the first
138 * descriptor that has not yet been filled by the device.
140 struct descriptor
*last
;
143 * The last descriptor in the DMA program. It contains the branch
144 * address that must be updated upon appending a new descriptor.
146 struct descriptor
*prev
;
148 descriptor_callback_t callback
;
150 struct tasklet_struct tasklet
;
153 #define IT_HEADER_SY(v) ((v) << 0)
154 #define IT_HEADER_TCODE(v) ((v) << 4)
155 #define IT_HEADER_CHANNEL(v) ((v) << 8)
156 #define IT_HEADER_TAG(v) ((v) << 14)
157 #define IT_HEADER_SPEED(v) ((v) << 16)
158 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
161 struct fw_iso_context base
;
162 struct context context
;
165 size_t header_length
;
168 #define CONFIG_ROM_SIZE 1024
174 __iomem
char *registers
;
175 dma_addr_t self_id_bus
;
177 struct tasklet_struct bus_reset_tasklet
;
180 int request_generation
;
184 * Spinlock for accessing fw_ohci data. Never call out of
185 * this driver with this lock held.
188 u32 self_id_buffer
[512];
190 /* Config rom buffers */
192 dma_addr_t config_rom_bus
;
193 __be32
*next_config_rom
;
194 dma_addr_t next_config_rom_bus
;
197 struct ar_context ar_request_ctx
;
198 struct ar_context ar_response_ctx
;
199 struct context at_request_ctx
;
200 struct context at_response_ctx
;
203 struct iso_context
*it_context_list
;
205 struct iso_context
*ir_context_list
;
208 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
210 return container_of(card
, struct fw_ohci
, card
);
213 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
214 #define IR_CONTEXT_BUFFER_FILL 0x80000000
215 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
216 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
217 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
218 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
220 #define CONTEXT_RUN 0x8000
221 #define CONTEXT_WAKE 0x1000
222 #define CONTEXT_DEAD 0x0800
223 #define CONTEXT_ACTIVE 0x0400
225 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
226 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
227 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
229 #define FW_OHCI_MAJOR 240
230 #define OHCI1394_REGISTER_SIZE 0x800
231 #define OHCI_LOOP_COUNT 500
232 #define OHCI1394_PCI_HCI_Control 0x40
233 #define SELF_ID_BUF_SIZE 0x800
234 #define OHCI_TCODE_PHY_PACKET 0x0e
235 #define OHCI_VERSION_1_1 0x010010
237 static char ohci_driver_name
[] = KBUILD_MODNAME
;
239 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
241 writel(data
, ohci
->registers
+ offset
);
244 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
246 return readl(ohci
->registers
+ offset
);
249 static inline void flush_writes(const struct fw_ohci
*ohci
)
251 /* Do a dummy read to flush writes. */
252 reg_read(ohci
, OHCI1394_Version
);
256 ohci_update_phy_reg(struct fw_card
*card
, int addr
,
257 int clear_bits
, int set_bits
)
259 struct fw_ohci
*ohci
= fw_ohci(card
);
262 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
265 val
= reg_read(ohci
, OHCI1394_PhyControl
);
266 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
267 fw_error("failed to set phy reg bits.\n");
271 old
= OHCI1394_PhyControl_ReadData(val
);
272 old
= (old
& ~clear_bits
) | set_bits
;
273 reg_write(ohci
, OHCI1394_PhyControl
,
274 OHCI1394_PhyControl_Write(addr
, old
));
279 static int ar_context_add_page(struct ar_context
*ctx
)
281 struct device
*dev
= ctx
->ohci
->card
.device
;
282 struct ar_buffer
*ab
;
286 ab
= (struct ar_buffer
*) __get_free_page(GFP_ATOMIC
);
290 ab_bus
= dma_map_single(dev
, ab
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
291 if (dma_mapping_error(ab_bus
)) {
292 free_page((unsigned long) ab
);
296 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
297 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
299 DESCRIPTOR_BRANCH_ALWAYS
);
300 offset
= offsetof(struct ar_buffer
, data
);
301 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
302 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
303 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
304 ab
->descriptor
.branch_address
= 0;
306 dma_sync_single_for_device(dev
, ab_bus
, PAGE_SIZE
, DMA_BIDIRECTIONAL
);
308 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
309 ctx
->last_buffer
->next
= ab
;
310 ctx
->last_buffer
= ab
;
312 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
313 flush_writes(ctx
->ohci
);
318 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
320 struct fw_ohci
*ohci
= ctx
->ohci
;
322 u32 status
, length
, tcode
;
324 p
.header
[0] = le32_to_cpu(buffer
[0]);
325 p
.header
[1] = le32_to_cpu(buffer
[1]);
326 p
.header
[2] = le32_to_cpu(buffer
[2]);
328 tcode
= (p
.header
[0] >> 4) & 0x0f;
330 case TCODE_WRITE_QUADLET_REQUEST
:
331 case TCODE_READ_QUADLET_RESPONSE
:
332 p
.header
[3] = (__force __u32
) buffer
[3];
333 p
.header_length
= 16;
334 p
.payload_length
= 0;
337 case TCODE_READ_BLOCK_REQUEST
:
338 p
.header
[3] = le32_to_cpu(buffer
[3]);
339 p
.header_length
= 16;
340 p
.payload_length
= 0;
343 case TCODE_WRITE_BLOCK_REQUEST
:
344 case TCODE_READ_BLOCK_RESPONSE
:
345 case TCODE_LOCK_REQUEST
:
346 case TCODE_LOCK_RESPONSE
:
347 p
.header
[3] = le32_to_cpu(buffer
[3]);
348 p
.header_length
= 16;
349 p
.payload_length
= p
.header
[3] >> 16;
352 case TCODE_WRITE_RESPONSE
:
353 case TCODE_READ_QUADLET_REQUEST
:
354 case OHCI_TCODE_PHY_PACKET
:
355 p
.header_length
= 12;
356 p
.payload_length
= 0;
360 p
.payload
= (void *) buffer
+ p
.header_length
;
362 /* FIXME: What to do about evt_* errors? */
363 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
364 status
= le32_to_cpu(buffer
[length
]);
366 p
.ack
= ((status
>> 16) & 0x1f) - 16;
367 p
.speed
= (status
>> 21) & 0x7;
368 p
.timestamp
= status
& 0xffff;
369 p
.generation
= ohci
->request_generation
;
372 * The OHCI bus reset handler synthesizes a phy packet with
373 * the new generation number when a bus reset happens (see
374 * section 8.4.2.3). This helps us determine when a request
375 * was received and make sure we send the response in the same
376 * generation. We only need this for requests; for responses
377 * we use the unique tlabel for finding the matching
381 if (p
.ack
+ 16 == 0x09)
382 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
383 else if (ctx
== &ohci
->ar_request_ctx
)
384 fw_core_handle_request(&ohci
->card
, &p
);
386 fw_core_handle_response(&ohci
->card
, &p
);
388 return buffer
+ length
+ 1;
391 static void ar_context_tasklet(unsigned long data
)
393 struct ar_context
*ctx
= (struct ar_context
*)data
;
394 struct fw_ohci
*ohci
= ctx
->ohci
;
395 struct ar_buffer
*ab
;
396 struct descriptor
*d
;
399 ab
= ctx
->current_buffer
;
402 if (d
->res_count
== 0) {
403 size_t size
, rest
, offset
;
406 * This descriptor is finished and we may have a
407 * packet split across this and the next buffer. We
408 * reuse the page for reassembling the split packet.
411 offset
= offsetof(struct ar_buffer
, data
);
412 dma_unmap_single(ohci
->card
.device
,
413 le32_to_cpu(ab
->descriptor
.data_address
) - offset
,
414 PAGE_SIZE
, DMA_BIDIRECTIONAL
);
419 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
420 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
421 memmove(buffer
, ctx
->pointer
, size
);
422 memcpy(buffer
+ size
, ab
->data
, rest
);
423 ctx
->current_buffer
= ab
;
424 ctx
->pointer
= (void *) ab
->data
+ rest
;
425 end
= buffer
+ size
+ rest
;
428 buffer
= handle_ar_packet(ctx
, buffer
);
430 free_page((unsigned long)buffer
);
431 ar_context_add_page(ctx
);
433 buffer
= ctx
->pointer
;
435 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
438 buffer
= handle_ar_packet(ctx
, buffer
);
443 ar_context_init(struct ar_context
*ctx
, struct fw_ohci
*ohci
, u32 regs
)
449 ctx
->last_buffer
= &ab
;
450 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
452 ar_context_add_page(ctx
);
453 ar_context_add_page(ctx
);
454 ctx
->current_buffer
= ab
.next
;
455 ctx
->pointer
= ctx
->current_buffer
->data
;
460 static void ar_context_run(struct ar_context
*ctx
)
462 struct ar_buffer
*ab
= ctx
->current_buffer
;
466 offset
= offsetof(struct ar_buffer
, data
);
467 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
469 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
470 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
471 flush_writes(ctx
->ohci
);
474 static struct descriptor
*
475 find_branch_descriptor(struct descriptor
*d
, int z
)
479 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
480 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
482 /* figure out which descriptor the branch address goes in */
483 if (z
== 2 && (b
== 3 || key
== 2))
489 static void context_tasklet(unsigned long data
)
491 struct context
*ctx
= (struct context
*) data
;
492 struct descriptor
*d
, *last
;
495 struct descriptor_buffer
*desc
;
497 desc
= list_entry(ctx
->buffer_list
.next
,
498 struct descriptor_buffer
, list
);
500 while (last
->branch_address
!= 0) {
501 struct descriptor_buffer
*old_desc
= desc
;
502 address
= le32_to_cpu(last
->branch_address
);
506 /* If the branch address points to a buffer outside of the
507 * current buffer, advance to the next buffer. */
508 if (address
< desc
->buffer_bus
||
509 address
>= desc
->buffer_bus
+ desc
->used
)
510 desc
= list_entry(desc
->list
.next
,
511 struct descriptor_buffer
, list
);
512 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
513 last
= find_branch_descriptor(d
, z
);
515 if (!ctx
->callback(ctx
, d
, last
))
518 if (old_desc
!= desc
) {
519 /* If we've advanced to the next buffer, move the
520 * previous buffer to the free list. */
523 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
524 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
525 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
532 * Allocate a new buffer and add it to the list of free buffers for this
533 * context. Must be called with ohci->lock held.
536 context_add_buffer(struct context
*ctx
)
538 struct descriptor_buffer
*desc
;
543 * 16MB of descriptors should be far more than enough for any DMA
544 * program. This will catch run-away userspace or DoS attacks.
546 if (ctx
->total_allocation
>= 16*1024*1024)
549 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
550 &bus_addr
, GFP_ATOMIC
);
554 offset
= (void *)&desc
->buffer
- (void *)desc
;
555 desc
->buffer_size
= PAGE_SIZE
- offset
;
556 desc
->buffer_bus
= bus_addr
+ offset
;
559 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
560 ctx
->total_allocation
+= PAGE_SIZE
;
566 context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
567 u32 regs
, descriptor_callback_t callback
)
571 ctx
->total_allocation
= 0;
573 INIT_LIST_HEAD(&ctx
->buffer_list
);
574 if (context_add_buffer(ctx
) < 0)
577 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
578 struct descriptor_buffer
, list
);
580 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
581 ctx
->callback
= callback
;
584 * We put a dummy descriptor in the buffer that has a NULL
585 * branch address and looks like it's been sent. That way we
586 * have a descriptor to append DMA programs to.
588 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
589 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
590 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
591 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
592 ctx
->last
= ctx
->buffer_tail
->buffer
;
593 ctx
->prev
= ctx
->buffer_tail
->buffer
;
599 context_release(struct context
*ctx
)
601 struct fw_card
*card
= &ctx
->ohci
->card
;
602 struct descriptor_buffer
*desc
, *tmp
;
604 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
605 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
607 ((void *)&desc
->buffer
- (void *)desc
));
610 /* Must be called with ohci->lock held */
611 static struct descriptor
*
612 context_get_descriptors(struct context
*ctx
, int z
, dma_addr_t
*d_bus
)
614 struct descriptor
*d
= NULL
;
615 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
617 if (z
* sizeof(*d
) > desc
->buffer_size
)
620 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
621 /* No room for the descriptor in this buffer, so advance to the
624 if (desc
->list
.next
== &ctx
->buffer_list
) {
625 /* If there is no free buffer next in the list,
627 if (context_add_buffer(ctx
) < 0)
630 desc
= list_entry(desc
->list
.next
,
631 struct descriptor_buffer
, list
);
632 ctx
->buffer_tail
= desc
;
635 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
636 memset(d
, 0, z
* sizeof(*d
));
637 *d_bus
= desc
->buffer_bus
+ desc
->used
;
642 static void context_run(struct context
*ctx
, u32 extra
)
644 struct fw_ohci
*ohci
= ctx
->ohci
;
646 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
647 le32_to_cpu(ctx
->last
->branch_address
));
648 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
649 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
653 static void context_append(struct context
*ctx
,
654 struct descriptor
*d
, int z
, int extra
)
657 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
659 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
661 desc
->used
+= (z
+ extra
) * sizeof(*d
);
662 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
663 ctx
->prev
= find_branch_descriptor(d
, z
);
665 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
666 flush_writes(ctx
->ohci
);
669 static void context_stop(struct context
*ctx
)
674 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
675 flush_writes(ctx
->ohci
);
677 for (i
= 0; i
< 10; i
++) {
678 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
679 if ((reg
& CONTEXT_ACTIVE
) == 0)
682 fw_notify("context_stop: still active (0x%08x)\n", reg
);
688 struct fw_packet
*packet
;
692 * This function apppends a packet to the DMA queue for transmission.
693 * Must always be called with the ochi->lock held to ensure proper
694 * generation handling and locking around packet queue manipulation.
697 at_context_queue_packet(struct context
*ctx
, struct fw_packet
*packet
)
699 struct fw_ohci
*ohci
= ctx
->ohci
;
700 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
701 struct driver_data
*driver_data
;
702 struct descriptor
*d
, *last
;
707 d
= context_get_descriptors(ctx
, 4, &d_bus
);
709 packet
->ack
= RCODE_SEND_ERROR
;
713 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
714 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
717 * The DMA format for asyncronous link packets is different
718 * from the IEEE1394 layout, so shift the fields around
719 * accordingly. If header_length is 8, it's a PHY packet, to
720 * which we need to prepend an extra quadlet.
723 header
= (__le32
*) &d
[1];
724 if (packet
->header_length
> 8) {
725 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
726 (packet
->speed
<< 16));
727 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
728 (packet
->header
[0] & 0xffff0000));
729 header
[2] = cpu_to_le32(packet
->header
[2]);
731 tcode
= (packet
->header
[0] >> 4) & 0x0f;
732 if (TCODE_IS_BLOCK_PACKET(tcode
))
733 header
[3] = cpu_to_le32(packet
->header
[3]);
735 header
[3] = (__force __le32
) packet
->header
[3];
737 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
739 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
740 (packet
->speed
<< 16));
741 header
[1] = cpu_to_le32(packet
->header
[0]);
742 header
[2] = cpu_to_le32(packet
->header
[1]);
743 d
[0].req_count
= cpu_to_le16(12);
746 driver_data
= (struct driver_data
*) &d
[3];
747 driver_data
->packet
= packet
;
748 packet
->driver_data
= driver_data
;
750 if (packet
->payload_length
> 0) {
752 dma_map_single(ohci
->card
.device
, packet
->payload
,
753 packet
->payload_length
, DMA_TO_DEVICE
);
754 if (dma_mapping_error(payload_bus
)) {
755 packet
->ack
= RCODE_SEND_ERROR
;
759 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
760 d
[2].data_address
= cpu_to_le32(payload_bus
);
768 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
769 DESCRIPTOR_IRQ_ALWAYS
|
770 DESCRIPTOR_BRANCH_ALWAYS
);
772 /* FIXME: Document how the locking works. */
773 if (ohci
->generation
!= packet
->generation
) {
774 if (packet
->payload_length
> 0)
775 dma_unmap_single(ohci
->card
.device
, payload_bus
,
776 packet
->payload_length
, DMA_TO_DEVICE
);
777 packet
->ack
= RCODE_GENERATION
;
781 context_append(ctx
, d
, z
, 4 - z
);
783 /* If the context isn't already running, start it up. */
784 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
785 if ((reg
& CONTEXT_RUN
) == 0)
791 static int handle_at_packet(struct context
*context
,
792 struct descriptor
*d
,
793 struct descriptor
*last
)
795 struct driver_data
*driver_data
;
796 struct fw_packet
*packet
;
797 struct fw_ohci
*ohci
= context
->ohci
;
798 dma_addr_t payload_bus
;
801 if (last
->transfer_status
== 0)
802 /* This descriptor isn't done yet, stop iteration. */
805 driver_data
= (struct driver_data
*) &d
[3];
806 packet
= driver_data
->packet
;
808 /* This packet was cancelled, just continue. */
811 payload_bus
= le32_to_cpu(last
->data_address
);
812 if (payload_bus
!= 0)
813 dma_unmap_single(ohci
->card
.device
, payload_bus
,
814 packet
->payload_length
, DMA_TO_DEVICE
);
816 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
817 packet
->timestamp
= le16_to_cpu(last
->res_count
);
820 case OHCI1394_evt_timeout
:
821 /* Async response transmit timed out. */
822 packet
->ack
= RCODE_CANCELLED
;
825 case OHCI1394_evt_flushed
:
827 * The packet was flushed should give same error as
828 * when we try to use a stale generation count.
830 packet
->ack
= RCODE_GENERATION
;
833 case OHCI1394_evt_missing_ack
:
835 * Using a valid (current) generation count, but the
836 * node is not on the bus or not sending acks.
838 packet
->ack
= RCODE_NO_ACK
;
841 case ACK_COMPLETE
+ 0x10:
842 case ACK_PENDING
+ 0x10:
843 case ACK_BUSY_X
+ 0x10:
844 case ACK_BUSY_A
+ 0x10:
845 case ACK_BUSY_B
+ 0x10:
846 case ACK_DATA_ERROR
+ 0x10:
847 case ACK_TYPE_ERROR
+ 0x10:
848 packet
->ack
= evt
- 0x10;
852 packet
->ack
= RCODE_SEND_ERROR
;
856 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
861 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
862 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
863 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
864 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
865 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
868 handle_local_rom(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
870 struct fw_packet response
;
871 int tcode
, length
, i
;
873 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
874 if (TCODE_IS_BLOCK_PACKET(tcode
))
875 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
879 i
= csr
- CSR_CONFIG_ROM
;
880 if (i
+ length
> CONFIG_ROM_SIZE
) {
881 fw_fill_response(&response
, packet
->header
,
882 RCODE_ADDRESS_ERROR
, NULL
, 0);
883 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
884 fw_fill_response(&response
, packet
->header
,
885 RCODE_TYPE_ERROR
, NULL
, 0);
887 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
888 (void *) ohci
->config_rom
+ i
, length
);
891 fw_core_handle_response(&ohci
->card
, &response
);
895 handle_local_lock(struct fw_ohci
*ohci
, struct fw_packet
*packet
, u32 csr
)
897 struct fw_packet response
;
898 int tcode
, length
, ext_tcode
, sel
;
899 __be32
*payload
, lock_old
;
900 u32 lock_arg
, lock_data
;
902 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
903 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
904 payload
= packet
->payload
;
905 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
907 if (tcode
== TCODE_LOCK_REQUEST
&&
908 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
909 lock_arg
= be32_to_cpu(payload
[0]);
910 lock_data
= be32_to_cpu(payload
[1]);
911 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
915 fw_fill_response(&response
, packet
->header
,
916 RCODE_TYPE_ERROR
, NULL
, 0);
920 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
921 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
922 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
923 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
925 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
926 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
928 fw_notify("swap not done yet\n");
930 fw_fill_response(&response
, packet
->header
,
931 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
933 fw_core_handle_response(&ohci
->card
, &response
);
937 handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
942 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
943 packet
->ack
= ACK_PENDING
;
944 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
948 ((unsigned long long)
949 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
951 csr
= offset
- CSR_REGISTER_BASE
;
953 /* Handle config rom reads. */
954 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
955 handle_local_rom(ctx
->ohci
, packet
, csr
);
957 case CSR_BUS_MANAGER_ID
:
958 case CSR_BANDWIDTH_AVAILABLE
:
959 case CSR_CHANNELS_AVAILABLE_HI
:
960 case CSR_CHANNELS_AVAILABLE_LO
:
961 handle_local_lock(ctx
->ohci
, packet
, csr
);
964 if (ctx
== &ctx
->ohci
->at_request_ctx
)
965 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
967 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
971 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
972 packet
->ack
= ACK_COMPLETE
;
973 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
978 at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
983 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
985 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
986 ctx
->ohci
->generation
== packet
->generation
) {
987 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
988 handle_local_request(ctx
, packet
);
992 retval
= at_context_queue_packet(ctx
, packet
);
993 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
996 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1000 static void bus_reset_tasklet(unsigned long data
)
1002 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1003 int self_id_count
, i
, j
, reg
;
1004 int generation
, new_generation
;
1005 unsigned long flags
;
1006 void *free_rom
= NULL
;
1007 dma_addr_t free_rom_bus
= 0;
1009 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1010 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1011 fw_notify("node ID not valid, new bus reset in progress\n");
1014 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1015 fw_notify("malconfigured bus\n");
1018 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1019 OHCI1394_NodeID_nodeNumber
);
1022 * The count in the SelfIDCount register is the number of
1023 * bytes in the self ID receive buffer. Since we also receive
1024 * the inverted quadlets and a header quadlet, we shift one
1025 * bit extra to get the actual number of self IDs.
1028 self_id_count
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 3) & 0x3ff;
1029 generation
= (le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1032 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1033 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1])
1034 fw_error("inconsistent self IDs\n");
1035 ohci
->self_id_buffer
[j
] = le32_to_cpu(ohci
->self_id_cpu
[i
]);
1040 * Check the consistency of the self IDs we just read. The
1041 * problem we face is that a new bus reset can start while we
1042 * read out the self IDs from the DMA buffer. If this happens,
1043 * the DMA buffer will be overwritten with new self IDs and we
1044 * will read out inconsistent data. The OHCI specification
1045 * (section 11.2) recommends a technique similar to
1046 * linux/seqlock.h, where we remember the generation of the
1047 * self IDs in the buffer before reading them out and compare
1048 * it to the current generation after reading them out. If
1049 * the two generations match we know we have a consistent set
1053 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1054 if (new_generation
!= generation
) {
1055 fw_notify("recursive bus reset detected, "
1056 "discarding self ids\n");
1060 /* FIXME: Document how the locking works. */
1061 spin_lock_irqsave(&ohci
->lock
, flags
);
1063 ohci
->generation
= generation
;
1064 context_stop(&ohci
->at_request_ctx
);
1065 context_stop(&ohci
->at_response_ctx
);
1066 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1069 * This next bit is unrelated to the AT context stuff but we
1070 * have to do it under the spinlock also. If a new config rom
1071 * was set up before this reset, the old one is now no longer
1072 * in use and we can free it. Update the config rom pointers
1073 * to point to the current config rom and clear the
1074 * next_config_rom pointer so a new udpate can take place.
1077 if (ohci
->next_config_rom
!= NULL
) {
1078 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1079 free_rom
= ohci
->config_rom
;
1080 free_rom_bus
= ohci
->config_rom_bus
;
1082 ohci
->config_rom
= ohci
->next_config_rom
;
1083 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1084 ohci
->next_config_rom
= NULL
;
1087 * Restore config_rom image and manually update
1088 * config_rom registers. Writing the header quadlet
1089 * will indicate that the config rom is ready, so we
1092 reg_write(ohci
, OHCI1394_BusOptions
,
1093 be32_to_cpu(ohci
->config_rom
[2]));
1094 ohci
->config_rom
[0] = cpu_to_be32(ohci
->next_header
);
1095 reg_write(ohci
, OHCI1394_ConfigROMhdr
, ohci
->next_header
);
1098 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1101 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1102 free_rom
, free_rom_bus
);
1104 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1105 self_id_count
, ohci
->self_id_buffer
);
1108 static irqreturn_t
irq_handler(int irq
, void *data
)
1110 struct fw_ohci
*ohci
= data
;
1111 u32 event
, iso_event
, cycle_time
;
1114 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1116 if (!event
|| !~event
)
1119 reg_write(ohci
, OHCI1394_IntEventClear
, event
);
1121 if (event
& OHCI1394_selfIDComplete
)
1122 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1124 if (event
& OHCI1394_RQPkt
)
1125 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1127 if (event
& OHCI1394_RSPkt
)
1128 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1130 if (event
& OHCI1394_reqTxComplete
)
1131 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1133 if (event
& OHCI1394_respTxComplete
)
1134 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1136 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1137 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1140 i
= ffs(iso_event
) - 1;
1141 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1142 iso_event
&= ~(1 << i
);
1145 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1146 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1149 i
= ffs(iso_event
) - 1;
1150 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1151 iso_event
&= ~(1 << i
);
1154 if (unlikely(event
& OHCI1394_postedWriteErr
))
1155 fw_error("PCI posted write error\n");
1157 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1158 if (printk_ratelimit())
1159 fw_notify("isochronous cycle too long\n");
1160 reg_write(ohci
, OHCI1394_LinkControlSet
,
1161 OHCI1394_LinkControl_cycleMaster
);
1164 if (event
& OHCI1394_cycle64Seconds
) {
1165 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1166 if ((cycle_time
& 0x80000000) == 0)
1167 ohci
->bus_seconds
++;
1173 static int software_reset(struct fw_ohci
*ohci
)
1177 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1179 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1180 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1181 OHCI1394_HCControl_softReset
) == 0)
1189 static int ohci_enable(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1191 struct fw_ohci
*ohci
= fw_ohci(card
);
1192 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1194 if (software_reset(ohci
)) {
1195 fw_error("Failed to reset ohci card.\n");
1200 * Now enable LPS, which we need in order to start accessing
1201 * most of the registers. In fact, on some cards (ALI M5251),
1202 * accessing registers in the SClk domain without LPS enabled
1203 * will lock up the machine. Wait 50msec to make sure we have
1204 * full link enabled.
1206 reg_write(ohci
, OHCI1394_HCControlSet
,
1207 OHCI1394_HCControl_LPS
|
1208 OHCI1394_HCControl_postedWriteEnable
);
1212 reg_write(ohci
, OHCI1394_HCControlClear
,
1213 OHCI1394_HCControl_noByteSwapData
);
1215 reg_write(ohci
, OHCI1394_LinkControlSet
,
1216 OHCI1394_LinkControl_rcvSelfID
|
1217 OHCI1394_LinkControl_cycleTimerEnable
|
1218 OHCI1394_LinkControl_cycleMaster
);
1220 reg_write(ohci
, OHCI1394_ATRetries
,
1221 OHCI1394_MAX_AT_REQ_RETRIES
|
1222 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1223 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1225 ar_context_run(&ohci
->ar_request_ctx
);
1226 ar_context_run(&ohci
->ar_response_ctx
);
1228 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1229 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1230 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1231 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1232 reg_write(ohci
, OHCI1394_IntMaskSet
,
1233 OHCI1394_selfIDComplete
|
1234 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1235 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1236 OHCI1394_isochRx
| OHCI1394_isochTx
|
1237 OHCI1394_postedWriteErr
| OHCI1394_cycleTooLong
|
1238 OHCI1394_cycle64Seconds
| OHCI1394_masterIntEnable
);
1240 /* Activate link_on bit and contender bit in our self ID packets.*/
1241 if (ohci_update_phy_reg(card
, 4, 0,
1242 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1246 * When the link is not yet enabled, the atomic config rom
1247 * update mechanism described below in ohci_set_config_rom()
1248 * is not active. We have to update ConfigRomHeader and
1249 * BusOptions manually, and the write to ConfigROMmap takes
1250 * effect immediately. We tie this to the enabling of the
1251 * link, so we have a valid config rom before enabling - the
1252 * OHCI requires that ConfigROMhdr and BusOptions have valid
1253 * values before enabling.
1255 * However, when the ConfigROMmap is written, some controllers
1256 * always read back quadlets 0 and 2 from the config rom to
1257 * the ConfigRomHeader and BusOptions registers on bus reset.
1258 * They shouldn't do that in this initial case where the link
1259 * isn't enabled. This means we have to use the same
1260 * workaround here, setting the bus header to 0 and then write
1261 * the right values in the bus reset tasklet.
1265 ohci
->next_config_rom
=
1266 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1267 &ohci
->next_config_rom_bus
,
1269 if (ohci
->next_config_rom
== NULL
)
1272 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1273 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
, length
* 4);
1276 * In the suspend case, config_rom is NULL, which
1277 * means that we just reuse the old config rom.
1279 ohci
->next_config_rom
= ohci
->config_rom
;
1280 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1283 ohci
->next_header
= be32_to_cpu(ohci
->next_config_rom
[0]);
1284 ohci
->next_config_rom
[0] = 0;
1285 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1286 reg_write(ohci
, OHCI1394_BusOptions
,
1287 be32_to_cpu(ohci
->next_config_rom
[2]));
1288 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1290 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1292 if (request_irq(dev
->irq
, irq_handler
,
1293 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1294 fw_error("Failed to allocate shared interrupt %d.\n",
1296 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1297 ohci
->config_rom
, ohci
->config_rom_bus
);
1301 reg_write(ohci
, OHCI1394_HCControlSet
,
1302 OHCI1394_HCControl_linkEnable
|
1303 OHCI1394_HCControl_BIBimageValid
);
1307 * We are ready to go, initiate bus reset to finish the
1311 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1317 ohci_set_config_rom(struct fw_card
*card
, u32
*config_rom
, size_t length
)
1319 struct fw_ohci
*ohci
;
1320 unsigned long flags
;
1321 int retval
= -EBUSY
;
1322 __be32
*next_config_rom
;
1323 dma_addr_t next_config_rom_bus
;
1325 ohci
= fw_ohci(card
);
1328 * When the OHCI controller is enabled, the config rom update
1329 * mechanism is a bit tricky, but easy enough to use. See
1330 * section 5.5.6 in the OHCI specification.
1332 * The OHCI controller caches the new config rom address in a
1333 * shadow register (ConfigROMmapNext) and needs a bus reset
1334 * for the changes to take place. When the bus reset is
1335 * detected, the controller loads the new values for the
1336 * ConfigRomHeader and BusOptions registers from the specified
1337 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1338 * shadow register. All automatically and atomically.
1340 * Now, there's a twist to this story. The automatic load of
1341 * ConfigRomHeader and BusOptions doesn't honor the
1342 * noByteSwapData bit, so with a be32 config rom, the
1343 * controller will load be32 values in to these registers
1344 * during the atomic update, even on litte endian
1345 * architectures. The workaround we use is to put a 0 in the
1346 * header quadlet; 0 is endian agnostic and means that the
1347 * config rom isn't ready yet. In the bus reset tasklet we
1348 * then set up the real values for the two registers.
1350 * We use ohci->lock to avoid racing with the code that sets
1351 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1355 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1356 &next_config_rom_bus
, GFP_KERNEL
);
1357 if (next_config_rom
== NULL
)
1360 spin_lock_irqsave(&ohci
->lock
, flags
);
1362 if (ohci
->next_config_rom
== NULL
) {
1363 ohci
->next_config_rom
= next_config_rom
;
1364 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1366 memset(ohci
->next_config_rom
, 0, CONFIG_ROM_SIZE
);
1367 fw_memcpy_to_be32(ohci
->next_config_rom
, config_rom
,
1370 ohci
->next_header
= config_rom
[0];
1371 ohci
->next_config_rom
[0] = 0;
1373 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1374 ohci
->next_config_rom_bus
);
1378 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1381 * Now initiate a bus reset to have the changes take
1382 * effect. We clean up the old config rom memory and DMA
1383 * mappings in the bus reset tasklet, since the OHCI
1384 * controller could need to access it before the bus reset
1388 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1390 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1391 next_config_rom
, next_config_rom_bus
);
1396 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1398 struct fw_ohci
*ohci
= fw_ohci(card
);
1400 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1403 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1405 struct fw_ohci
*ohci
= fw_ohci(card
);
1407 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1410 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1412 struct fw_ohci
*ohci
= fw_ohci(card
);
1413 struct context
*ctx
= &ohci
->at_request_ctx
;
1414 struct driver_data
*driver_data
= packet
->driver_data
;
1415 int retval
= -ENOENT
;
1417 tasklet_disable(&ctx
->tasklet
);
1419 if (packet
->ack
!= 0)
1422 driver_data
->packet
= NULL
;
1423 packet
->ack
= RCODE_CANCELLED
;
1424 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1428 tasklet_enable(&ctx
->tasklet
);
1434 ohci_enable_phys_dma(struct fw_card
*card
, int node_id
, int generation
)
1436 struct fw_ohci
*ohci
= fw_ohci(card
);
1437 unsigned long flags
;
1441 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1442 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1445 spin_lock_irqsave(&ohci
->lock
, flags
);
1447 if (ohci
->generation
!= generation
) {
1453 * Note, if the node ID contains a non-local bus ID, physical DMA is
1454 * enabled for _all_ nodes on remote buses.
1457 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1459 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1461 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1465 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1470 ohci_get_bus_time(struct fw_card
*card
)
1472 struct fw_ohci
*ohci
= fw_ohci(card
);
1476 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1477 bus_time
= ((u64
) ohci
->bus_seconds
<< 32) | cycle_time
;
1482 static int handle_ir_dualbuffer_packet(struct context
*context
,
1483 struct descriptor
*d
,
1484 struct descriptor
*last
)
1486 struct iso_context
*ctx
=
1487 container_of(context
, struct iso_context
, context
);
1488 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1490 size_t header_length
;
1494 if (db
->first_res_count
!= 0 && db
->second_res_count
!= 0) {
1495 if (ctx
->excess_bytes
<= le16_to_cpu(db
->second_req_count
)) {
1496 /* This descriptor isn't done yet, stop iteration. */
1499 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
);
1502 header_length
= le16_to_cpu(db
->first_req_count
) -
1503 le16_to_cpu(db
->first_res_count
);
1505 i
= ctx
->header_length
;
1507 end
= p
+ header_length
;
1508 while (p
< end
&& i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1510 * The iso header is byteswapped to little endian by
1511 * the controller, but the remaining header quadlets
1512 * are big endian. We want to present all the headers
1513 * as big endian, so we have to swap the first
1516 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1517 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1518 i
+= ctx
->base
.header_size
;
1519 ctx
->excess_bytes
+=
1520 (le32_to_cpu(*(__le32
*)(p
+ 4)) >> 16) & 0xffff;
1521 p
+= ctx
->base
.header_size
+ 4;
1523 ctx
->header_length
= i
;
1525 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
) -
1526 le16_to_cpu(db
->second_res_count
);
1528 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1529 ir_header
= (__le32
*) (db
+ 1);
1530 ctx
->base
.callback(&ctx
->base
,
1531 le32_to_cpu(ir_header
[0]) & 0xffff,
1532 ctx
->header_length
, ctx
->header
,
1533 ctx
->base
.callback_data
);
1534 ctx
->header_length
= 0;
1540 static int handle_ir_packet_per_buffer(struct context
*context
,
1541 struct descriptor
*d
,
1542 struct descriptor
*last
)
1544 struct iso_context
*ctx
=
1545 container_of(context
, struct iso_context
, context
);
1546 struct descriptor
*pd
;
1551 for (pd
= d
; pd
<= last
; pd
++) {
1552 if (pd
->transfer_status
)
1556 /* Descriptor(s) not done yet, stop iteration */
1559 i
= ctx
->header_length
;
1562 if (ctx
->base
.header_size
> 0 &&
1563 i
+ ctx
->base
.header_size
<= PAGE_SIZE
) {
1565 * The iso header is byteswapped to little endian by
1566 * the controller, but the remaining header quadlets
1567 * are big endian. We want to present all the headers
1568 * as big endian, so we have to swap the first quadlet.
1570 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1571 memcpy(ctx
->header
+ i
+ 4, p
+ 8, ctx
->base
.header_size
- 4);
1572 ctx
->header_length
+= ctx
->base
.header_size
;
1575 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1576 ir_header
= (__le32
*) p
;
1577 ctx
->base
.callback(&ctx
->base
,
1578 le32_to_cpu(ir_header
[0]) & 0xffff,
1579 ctx
->header_length
, ctx
->header
,
1580 ctx
->base
.callback_data
);
1581 ctx
->header_length
= 0;
1587 static int handle_it_packet(struct context
*context
,
1588 struct descriptor
*d
,
1589 struct descriptor
*last
)
1591 struct iso_context
*ctx
=
1592 container_of(context
, struct iso_context
, context
);
1594 if (last
->transfer_status
== 0)
1595 /* This descriptor isn't done yet, stop iteration. */
1598 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
)
1599 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1600 0, NULL
, ctx
->base
.callback_data
);
1605 static struct fw_iso_context
*
1606 ohci_allocate_iso_context(struct fw_card
*card
, int type
, size_t header_size
)
1608 struct fw_ohci
*ohci
= fw_ohci(card
);
1609 struct iso_context
*ctx
, *list
;
1610 descriptor_callback_t callback
;
1612 unsigned long flags
;
1613 int index
, retval
= -ENOMEM
;
1615 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1616 mask
= &ohci
->it_context_mask
;
1617 list
= ohci
->it_context_list
;
1618 callback
= handle_it_packet
;
1620 mask
= &ohci
->ir_context_mask
;
1621 list
= ohci
->ir_context_list
;
1622 if (ohci
->version
>= OHCI_VERSION_1_1
)
1623 callback
= handle_ir_dualbuffer_packet
;
1625 callback
= handle_ir_packet_per_buffer
;
1628 spin_lock_irqsave(&ohci
->lock
, flags
);
1629 index
= ffs(*mask
) - 1;
1631 *mask
&= ~(1 << index
);
1632 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1635 return ERR_PTR(-EBUSY
);
1637 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1638 regs
= OHCI1394_IsoXmitContextBase(index
);
1640 regs
= OHCI1394_IsoRcvContextBase(index
);
1643 memset(ctx
, 0, sizeof(*ctx
));
1644 ctx
->header_length
= 0;
1645 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1646 if (ctx
->header
== NULL
)
1649 retval
= context_init(&ctx
->context
, ohci
, regs
, callback
);
1651 goto out_with_header
;
1656 free_page((unsigned long)ctx
->header
);
1658 spin_lock_irqsave(&ohci
->lock
, flags
);
1659 *mask
|= 1 << index
;
1660 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1662 return ERR_PTR(retval
);
1665 static int ohci_start_iso(struct fw_iso_context
*base
,
1666 s32 cycle
, u32 sync
, u32 tags
)
1668 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1669 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
1673 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1674 index
= ctx
- ohci
->it_context_list
;
1677 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
1678 (cycle
& 0x7fff) << 16;
1680 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
1681 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
1682 context_run(&ctx
->context
, match
);
1684 index
= ctx
- ohci
->ir_context_list
;
1685 control
= IR_CONTEXT_ISOCH_HEADER
;
1686 if (ohci
->version
>= OHCI_VERSION_1_1
)
1687 control
|= IR_CONTEXT_DUAL_BUFFER_MODE
;
1688 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
1690 match
|= (cycle
& 0x07fff) << 12;
1691 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
1694 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
1695 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
1696 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
1697 context_run(&ctx
->context
, control
);
1703 static int ohci_stop_iso(struct fw_iso_context
*base
)
1705 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1706 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1709 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1710 index
= ctx
- ohci
->it_context_list
;
1711 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
1713 index
= ctx
- ohci
->ir_context_list
;
1714 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
1717 context_stop(&ctx
->context
);
1722 static void ohci_free_iso_context(struct fw_iso_context
*base
)
1724 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
1725 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1726 unsigned long flags
;
1729 ohci_stop_iso(base
);
1730 context_release(&ctx
->context
);
1731 free_page((unsigned long)ctx
->header
);
1733 spin_lock_irqsave(&ohci
->lock
, flags
);
1735 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
1736 index
= ctx
- ohci
->it_context_list
;
1737 ohci
->it_context_mask
|= 1 << index
;
1739 index
= ctx
- ohci
->ir_context_list
;
1740 ohci
->ir_context_mask
|= 1 << index
;
1743 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1747 ohci_queue_iso_transmit(struct fw_iso_context
*base
,
1748 struct fw_iso_packet
*packet
,
1749 struct fw_iso_buffer
*buffer
,
1750 unsigned long payload
)
1752 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1753 struct descriptor
*d
, *last
, *pd
;
1754 struct fw_iso_packet
*p
;
1756 dma_addr_t d_bus
, page_bus
;
1757 u32 z
, header_z
, payload_z
, irq
;
1758 u32 payload_index
, payload_end_index
, next_page_index
;
1759 int page
, end_page
, i
, length
, offset
;
1762 * FIXME: Cycle lost behavior should be configurable: lose
1763 * packet, retransmit or terminate..
1767 payload_index
= payload
;
1773 if (p
->header_length
> 0)
1776 /* Determine the first page the payload isn't contained in. */
1777 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
1778 if (p
->payload_length
> 0)
1779 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
1785 /* Get header size in number of descriptors. */
1786 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
1788 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
1793 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
1794 d
[0].req_count
= cpu_to_le16(8);
1796 header
= (__le32
*) &d
[1];
1797 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
1798 IT_HEADER_TAG(p
->tag
) |
1799 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
1800 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
1801 IT_HEADER_SPEED(ctx
->base
.speed
));
1803 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
1804 p
->payload_length
));
1807 if (p
->header_length
> 0) {
1808 d
[2].req_count
= cpu_to_le16(p
->header_length
);
1809 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
1810 memcpy(&d
[z
], p
->header
, p
->header_length
);
1813 pd
= d
+ z
- payload_z
;
1814 payload_end_index
= payload_index
+ p
->payload_length
;
1815 for (i
= 0; i
< payload_z
; i
++) {
1816 page
= payload_index
>> PAGE_SHIFT
;
1817 offset
= payload_index
& ~PAGE_MASK
;
1818 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
1820 min(next_page_index
, payload_end_index
) - payload_index
;
1821 pd
[i
].req_count
= cpu_to_le16(length
);
1823 page_bus
= page_private(buffer
->pages
[page
]);
1824 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
1826 payload_index
+= length
;
1830 irq
= DESCRIPTOR_IRQ_ALWAYS
;
1832 irq
= DESCRIPTOR_NO_IRQ
;
1834 last
= z
== 2 ? d
: d
+ z
- 1;
1835 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1837 DESCRIPTOR_BRANCH_ALWAYS
|
1840 context_append(&ctx
->context
, d
, z
, header_z
);
1846 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
1847 struct fw_iso_packet
*packet
,
1848 struct fw_iso_buffer
*buffer
,
1849 unsigned long payload
)
1851 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1852 struct db_descriptor
*db
= NULL
;
1853 struct descriptor
*d
;
1854 struct fw_iso_packet
*p
;
1855 dma_addr_t d_bus
, page_bus
;
1856 u32 z
, header_z
, length
, rest
;
1857 int page
, offset
, packet_count
, header_size
;
1860 * FIXME: Cycle lost behavior should be configurable: lose
1861 * packet, retransmit or terminate..
1868 * The OHCI controller puts the status word in the header
1869 * buffer too, so we need 4 extra bytes per packet.
1871 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
1872 header_size
= packet_count
* (ctx
->base
.header_size
+ 4);
1874 /* Get header size in number of descriptors. */
1875 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
1876 page
= payload
>> PAGE_SHIFT
;
1877 offset
= payload
& ~PAGE_MASK
;
1878 rest
= p
->payload_length
;
1880 /* FIXME: make packet-per-buffer/dual-buffer a context option */
1882 d
= context_get_descriptors(&ctx
->context
,
1883 z
+ header_z
, &d_bus
);
1887 db
= (struct db_descriptor
*) d
;
1888 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1889 DESCRIPTOR_BRANCH_ALWAYS
);
1890 db
->first_size
= cpu_to_le16(ctx
->base
.header_size
+ 4);
1891 if (p
->skip
&& rest
== p
->payload_length
) {
1892 db
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
1893 db
->first_req_count
= db
->first_size
;
1895 db
->first_req_count
= cpu_to_le16(header_size
);
1897 db
->first_res_count
= db
->first_req_count
;
1898 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
1900 if (p
->skip
&& rest
== p
->payload_length
)
1902 else if (offset
+ rest
< PAGE_SIZE
)
1905 length
= PAGE_SIZE
- offset
;
1907 db
->second_req_count
= cpu_to_le16(length
);
1908 db
->second_res_count
= db
->second_req_count
;
1909 page_bus
= page_private(buffer
->pages
[page
]);
1910 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
1912 if (p
->interrupt
&& length
== rest
)
1913 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
1915 context_append(&ctx
->context
, d
, z
, header_z
);
1916 offset
= (offset
+ length
) & ~PAGE_MASK
;
1926 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
1927 struct fw_iso_packet
*packet
,
1928 struct fw_iso_buffer
*buffer
,
1929 unsigned long payload
)
1931 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
1932 struct descriptor
*d
= NULL
, *pd
= NULL
;
1933 struct fw_iso_packet
*p
= packet
;
1934 dma_addr_t d_bus
, page_bus
;
1935 u32 z
, header_z
, rest
;
1937 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
1940 * The OHCI controller puts the status word in the
1941 * buffer too, so we need 4 extra bytes per packet.
1943 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
1944 header_size
= ctx
->base
.header_size
+ 4;
1946 /* Get header size in number of descriptors. */
1947 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
1948 page
= payload
>> PAGE_SHIFT
;
1949 offset
= payload
& ~PAGE_MASK
;
1950 payload_per_buffer
= p
->payload_length
/ packet_count
;
1952 for (i
= 0; i
< packet_count
; i
++) {
1953 /* d points to the header descriptor */
1954 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
1955 d
= context_get_descriptors(&ctx
->context
,
1956 z
+ header_z
, &d_bus
);
1960 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1961 DESCRIPTOR_INPUT_MORE
);
1962 if (p
->skip
&& i
== 0)
1963 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
1964 d
->req_count
= cpu_to_le16(header_size
);
1965 d
->res_count
= d
->req_count
;
1966 d
->transfer_status
= 0;
1967 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
1969 rest
= payload_per_buffer
;
1970 for (j
= 1; j
< z
; j
++) {
1972 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1973 DESCRIPTOR_INPUT_MORE
);
1975 if (offset
+ rest
< PAGE_SIZE
)
1978 length
= PAGE_SIZE
- offset
;
1979 pd
->req_count
= cpu_to_le16(length
);
1980 pd
->res_count
= pd
->req_count
;
1981 pd
->transfer_status
= 0;
1983 page_bus
= page_private(buffer
->pages
[page
]);
1984 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
1986 offset
= (offset
+ length
) & ~PAGE_MASK
;
1991 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
1992 DESCRIPTOR_INPUT_LAST
|
1993 DESCRIPTOR_BRANCH_ALWAYS
);
1994 if (p
->interrupt
&& i
== packet_count
- 1)
1995 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
1997 context_append(&ctx
->context
, d
, z
, header_z
);
2004 ohci_queue_iso(struct fw_iso_context
*base
,
2005 struct fw_iso_packet
*packet
,
2006 struct fw_iso_buffer
*buffer
,
2007 unsigned long payload
)
2009 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2010 unsigned long flags
;
2013 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2014 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2015 retval
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2016 else if (ctx
->context
.ohci
->version
>= OHCI_VERSION_1_1
)
2017 retval
= ohci_queue_iso_receive_dualbuffer(base
, packet
,
2020 retval
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2023 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2028 static const struct fw_card_driver ohci_driver
= {
2029 .name
= ohci_driver_name
,
2030 .enable
= ohci_enable
,
2031 .update_phy_reg
= ohci_update_phy_reg
,
2032 .set_config_rom
= ohci_set_config_rom
,
2033 .send_request
= ohci_send_request
,
2034 .send_response
= ohci_send_response
,
2035 .cancel_packet
= ohci_cancel_packet
,
2036 .enable_phys_dma
= ohci_enable_phys_dma
,
2037 .get_bus_time
= ohci_get_bus_time
,
2039 .allocate_iso_context
= ohci_allocate_iso_context
,
2040 .free_iso_context
= ohci_free_iso_context
,
2041 .queue_iso
= ohci_queue_iso
,
2042 .start_iso
= ohci_start_iso
,
2043 .stop_iso
= ohci_stop_iso
,
2046 static int __devinit
2047 pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
2049 struct fw_ohci
*ohci
;
2050 u32 bus_options
, max_receive
, link_speed
;
2055 #ifdef CONFIG_PPC_PMAC
2056 /* Necessary on some machines if fw-ohci was loaded/ unloaded before */
2057 if (machine_is(powermac
)) {
2058 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2061 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2062 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2065 #endif /* CONFIG_PPC_PMAC */
2067 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2069 fw_error("Could not malloc fw_ohci data.\n");
2073 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2075 err
= pci_enable_device(dev
);
2077 fw_error("Failed to enable OHCI hardware.\n");
2081 pci_set_master(dev
);
2082 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2083 pci_set_drvdata(dev
, ohci
);
2085 spin_lock_init(&ohci
->lock
);
2087 tasklet_init(&ohci
->bus_reset_tasklet
,
2088 bus_reset_tasklet
, (unsigned long)ohci
);
2090 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2092 fw_error("MMIO resource unavailable\n");
2096 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2097 if (ohci
->registers
== NULL
) {
2098 fw_error("Failed to remap registers\n");
2103 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2104 OHCI1394_AsReqRcvContextControlSet
);
2106 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2107 OHCI1394_AsRspRcvContextControlSet
);
2109 context_init(&ohci
->at_request_ctx
, ohci
,
2110 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2112 context_init(&ohci
->at_response_ctx
, ohci
,
2113 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2115 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2116 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2117 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2118 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
2119 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2121 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2122 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2123 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2124 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
2125 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2127 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2128 fw_error("Out of memory for it/ir contexts.\n");
2130 goto fail_registers
;
2133 /* self-id dma buffer allocation */
2134 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2138 if (ohci
->self_id_cpu
== NULL
) {
2139 fw_error("Out of memory for self ID buffer.\n");
2141 goto fail_registers
;
2144 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2145 max_receive
= (bus_options
>> 12) & 0xf;
2146 link_speed
= bus_options
& 0x7;
2147 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2148 reg_read(ohci
, OHCI1394_GUIDLo
);
2150 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2154 ohci
->version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2155 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2156 dev
->dev
.bus_id
, ohci
->version
>> 16, ohci
->version
& 0xff);
2160 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2161 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2163 kfree(ohci
->it_context_list
);
2164 kfree(ohci
->ir_context_list
);
2165 pci_iounmap(dev
, ohci
->registers
);
2167 pci_release_region(dev
, 0);
2169 pci_disable_device(dev
);
2171 fw_card_put(&ohci
->card
);
2176 static void pci_remove(struct pci_dev
*dev
)
2178 struct fw_ohci
*ohci
;
2180 ohci
= pci_get_drvdata(dev
);
2181 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2183 fw_core_remove_card(&ohci
->card
);
2186 * FIXME: Fail all pending packets here, now that the upper
2187 * layers can't queue any more.
2190 software_reset(ohci
);
2191 free_irq(dev
->irq
, ohci
);
2192 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2193 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2194 kfree(ohci
->it_context_list
);
2195 kfree(ohci
->ir_context_list
);
2196 pci_iounmap(dev
, ohci
->registers
);
2197 pci_release_region(dev
, 0);
2198 pci_disable_device(dev
);
2199 fw_card_put(&ohci
->card
);
2201 #ifdef CONFIG_PPC_PMAC
2202 /* On UniNorth, power down the cable and turn off the chip clock
2203 * to save power on laptops */
2204 if (machine_is(powermac
)) {
2205 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2208 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2209 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2212 #endif /* CONFIG_PPC_PMAC */
2214 fw_notify("Removed fw-ohci device.\n");
2218 static int pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2220 struct fw_ohci
*ohci
= pci_get_drvdata(pdev
);
2223 software_reset(ohci
);
2224 free_irq(pdev
->irq
, ohci
);
2225 err
= pci_save_state(pdev
);
2227 fw_error("pci_save_state failed\n");
2230 err
= pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
2232 fw_error("pci_set_power_state failed with %d\n", err
);
2234 /* PowerMac suspend code comes last */
2235 #ifdef CONFIG_PPC_PMAC
2236 if (machine_is(powermac
)) {
2237 struct device_node
*ofn
= pci_device_to_OF_node(pdev
);
2240 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2242 #endif /* CONFIG_PPC_PMAC */
2247 static int pci_resume(struct pci_dev
*pdev
)
2249 struct fw_ohci
*ohci
= pci_get_drvdata(pdev
);
2252 /* PowerMac resume code comes first */
2253 #ifdef CONFIG_PPC_PMAC
2254 if (machine_is(powermac
)) {
2255 struct device_node
*ofn
= pci_device_to_OF_node(pdev
);
2258 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2260 #endif /* CONFIG_PPC_PMAC */
2262 pci_set_power_state(pdev
, PCI_D0
);
2263 pci_restore_state(pdev
);
2264 err
= pci_enable_device(pdev
);
2266 fw_error("pci_enable_device failed\n");
2270 return ohci_enable(&ohci
->card
, NULL
, 0);
2274 static struct pci_device_id pci_table
[] = {
2275 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2279 MODULE_DEVICE_TABLE(pci
, pci_table
);
2281 static struct pci_driver fw_ohci_pci_driver
= {
2282 .name
= ohci_driver_name
,
2283 .id_table
= pci_table
,
2285 .remove
= pci_remove
,
2287 .resume
= pci_resume
,
2288 .suspend
= pci_suspend
,
2292 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2293 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2294 MODULE_LICENSE("GPL");
2296 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2297 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2298 MODULE_ALIAS("ohci1394");
2301 static int __init
fw_ohci_init(void)
2303 return pci_register_driver(&fw_ohci_pci_driver
);
2306 static void __exit
fw_ohci_cleanup(void)
2308 pci_unregister_driver(&fw_ohci_pci_driver
);
2311 module_init(fw_ohci_init
);
2312 module_exit(fw_ohci_cleanup
);