drivers/net/e1000e/hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #ifndef _E1000_HW_H_
  30 #define _E1000_HW_H_
  31
  32 #include <linux/types.h>
  33
  34 struct e1000_hw;
  35 struct e1000_adapter;
  36
  37 #include "defines.h"
  38
  39 #define er32(reg)       __er32(hw, E1000_##reg)
  40 #define ew32(reg,val)   __ew32(hw, E1000_##reg, (val))
  41 #define e1e_flush()     er32(STATUS)
  42
  43 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
  44         (writel((value), ((a)->hw_addr + reg + ((offset) << 2))))
  45
  46 #define E1000_READ_REG_ARRAY(a, reg, offset) \
  47         (readl((a)->hw_addr + reg + ((offset) << 2)))
  48
  49 enum e1e_registers {
  50         E1000_CTRL     = 0x00000, /* Device Control - RW */
  51         E1000_STATUS   = 0x00008, /* Device Status - RO */
  52         E1000_EECD     = 0x00010, /* EEPROM/Flash Control - RW */
  53         E1000_EERD     = 0x00014, /* EEPROM Read - RW */
  54         E1000_CTRL_EXT = 0x00018, /* Extended Device Control - RW */
  55         E1000_FLA      = 0x0001C, /* Flash Access - RW */
  56         E1000_MDIC     = 0x00020, /* MDI Control - RW */
  57         E1000_SCTL     = 0x00024, /* SerDes Control - RW */
  58         E1000_FCAL     = 0x00028, /* Flow Control Address Low - RW */
  59         E1000_FCAH     = 0x0002C, /* Flow Control Address High -RW */
  60         E1000_FEXTNVM  = 0x00028, /* Future Extended NVM - RW */
  61         E1000_FCT      = 0x00030, /* Flow Control Type - RW */
  62         E1000_VET      = 0x00038, /* VLAN Ether Type - RW */
  63         E1000_ICR      = 0x000C0, /* Interrupt Cause Read - R/clr */
  64         E1000_ITR      = 0x000C4, /* Interrupt Throttling Rate - RW */
  65         E1000_ICS      = 0x000C8, /* Interrupt Cause Set - WO */
  66         E1000_IMS      = 0x000D0, /* Interrupt Mask Set - RW */
  67         E1000_IMC      = 0x000D8, /* Interrupt Mask Clear - WO */
  68         E1000_IAM      = 0x000E0, /* Interrupt Acknowledge Auto Mask */
  69         E1000_RCTL     = 0x00100, /* Rx Control - RW */
  70         E1000_FCTTV    = 0x00170, /* Flow Control Transmit Timer Value - RW */
  71         E1000_TXCW     = 0x00178, /* Tx Configuration Word - RW */
  72         E1000_RXCW     = 0x00180, /* Rx Configuration Word - RO */
  73         E1000_TCTL     = 0x00400, /* Tx Control - RW */
  74         E1000_TCTL_EXT = 0x00404, /* Extended Tx Control - RW */
  75         E1000_TIPG     = 0x00410, /* Tx Inter-packet gap -RW */
  76         E1000_AIT      = 0x00458, /* Adaptive Interframe Spacing Throttle -RW */
  77         E1000_LEDCTL   = 0x00E00, /* LED Control - RW */
  78         E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
  79         E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
  80         E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
  81         E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
  82         E1000_PBS      = 0x01008, /* Packet Buffer Size */
  83         E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
  84         E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
  85         E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
  86         E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
  87         E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
  88         E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */
  89         E1000_PSRCTL   = 0x02170, /* Packet Split Receive Control - RW */
  90         E1000_RDBAL    = 0x02800, /* Rx Descriptor Base Address Low - RW */
  91         E1000_RDBAH    = 0x02804, /* Rx Descriptor Base Address High - RW */
  92         E1000_RDLEN    = 0x02808, /* Rx Descriptor Length - RW */
  93         E1000_RDH      = 0x02810, /* Rx Descriptor Head - RW */
  94         E1000_RDT      = 0x02818, /* Rx Descriptor Tail - RW */
  95         E1000_RDTR     = 0x02820, /* Rx Delay Timer - RW */
  96         E1000_RXDCTL_BASE = 0x02828, /* Rx Descriptor Control - RW */
  97 #define E1000_RXDCTL(_n)   (E1000_RXDCTL_BASE + (_n << 8))
  98         E1000_RADV     = 0x0282C, /* RX Interrupt Absolute Delay Timer - RW */
  99
 100 /* Convenience macros
 101  *
 102  * Note: "_n" is the queue number of the register to be written to.
 103  *
 104  * Example usage:
 105  * E1000_RDBAL_REG(current_rx_queue)
 106  *
 107  */
 108 #define E1000_RDBAL_REG(_n)   (E1000_RDBAL + (_n << 8))
 109         E1000_KABGTXD  = 0x03004, /* AFE Band Gap Transmit Ref Data */
 110         E1000_TDBAL    = 0x03800, /* Tx Descriptor Base Address Low - RW */
 111         E1000_TDBAH    = 0x03804, /* Tx Descriptor Base Address High - RW */
 112         E1000_TDLEN    = 0x03808, /* Tx Descriptor Length - RW */
 113         E1000_TDH      = 0x03810, /* Tx Descriptor Head - RW */
 114         E1000_TDT      = 0x03818, /* Tx Descriptor Tail - RW */
 115         E1000_TIDV     = 0x03820, /* Tx Interrupt Delay Value - RW */
 116         E1000_TXDCTL_BASE = 0x03828, /* Tx Descriptor Control - RW */
 117 #define E1000_TXDCTL(_n)   (E1000_TXDCTL_BASE + (_n << 8))
 118         E1000_TADV     = 0x0382C, /* Tx Interrupt Absolute Delay Val - RW */
 119         E1000_TARC_BASE = 0x03840, /* Tx Arbitration Count (0) */
 120 #define E1000_TARC(_n)   (E1000_TARC_BASE + (_n << 8))
 121         E1000_CRCERRS  = 0x04000, /* CRC Error Count - R/clr */
 122         E1000_ALGNERRC = 0x04004, /* Alignment Error Count - R/clr */
 123         E1000_SYMERRS  = 0x04008, /* Symbol Error Count - R/clr */
 124         E1000_RXERRC   = 0x0400C, /* Receive Error Count - R/clr */
 125         E1000_MPC      = 0x04010, /* Missed Packet Count - R/clr */
 126         E1000_SCC      = 0x04014, /* Single Collision Count - R/clr */
 127         E1000_ECOL     = 0x04018, /* Excessive Collision Count - R/clr */
 128         E1000_MCC      = 0x0401C, /* Multiple Collision Count - R/clr */
 129         E1000_LATECOL  = 0x04020, /* Late Collision Count - R/clr */
 130         E1000_COLC     = 0x04028, /* Collision Count - R/clr */
 131         E1000_DC       = 0x04030, /* Defer Count - R/clr */
 132         E1000_TNCRS    = 0x04034, /* Tx-No CRS - R/clr */
 133         E1000_SEC      = 0x04038, /* Sequence Error Count - R/clr */
 134         E1000_CEXTERR  = 0x0403C, /* Carrier Extension Error Count - R/clr */
 135         E1000_RLEC     = 0x04040, /* Receive Length Error Count - R/clr */
 136         E1000_XONRXC   = 0x04048, /* XON Rx Count - R/clr */
 137         E1000_XONTXC   = 0x0404C, /* XON Tx Count - R/clr */
 138         E1000_XOFFRXC  = 0x04050, /* XOFF Rx Count - R/clr */
 139         E1000_XOFFTXC  = 0x04054, /* XOFF Tx Count - R/clr */
 140         E1000_FCRUC    = 0x04058, /* Flow Control Rx Unsupported Count- R/clr */
 141         E1000_PRC64    = 0x0405C, /* Packets Rx (64 bytes) - R/clr */
 142         E1000_PRC127   = 0x04060, /* Packets Rx (65-127 bytes) - R/clr */
 143         E1000_PRC255   = 0x04064, /* Packets Rx (128-255 bytes) - R/clr */
 144         E1000_PRC511   = 0x04068, /* Packets Rx (255-511 bytes) - R/clr */
 145         E1000_PRC1023  = 0x0406C, /* Packets Rx (512-1023 bytes) - R/clr */
 146         E1000_PRC1522  = 0x04070, /* Packets Rx (1024-1522 bytes) - R/clr */
 147         E1000_GPRC     = 0x04074, /* Good Packets Rx Count - R/clr */
 148         E1000_BPRC     = 0x04078, /* Broadcast Packets Rx Count - R/clr */
 149         E1000_MPRC     = 0x0407C, /* Multicast Packets Rx Count - R/clr */
 150         E1000_GPTC     = 0x04080, /* Good Packets Tx Count - R/clr */
 151         E1000_GORCL    = 0x04088, /* Good Octets Rx Count Low - R/clr */
 152         E1000_GORCH    = 0x0408C, /* Good Octets Rx Count High - R/clr */
 153         E1000_GOTCL    = 0x04090, /* Good Octets Tx Count Low - R/clr */
 154         E1000_GOTCH    = 0x04094, /* Good Octets Tx Count High - R/clr */
 155         E1000_RNBC     = 0x040A0, /* Rx No Buffers Count - R/clr */
 156         E1000_RUC      = 0x040A4, /* Rx Undersize Count - R/clr */
 157         E1000_RFC      = 0x040A8, /* Rx Fragment Count - R/clr */
 158         E1000_ROC      = 0x040AC, /* Rx Oversize Count - R/clr */
 159         E1000_RJC      = 0x040B0, /* Rx Jabber Count - R/clr */
 160         E1000_MGTPRC   = 0x040B4, /* Management Packets Rx Count - R/clr */
 161         E1000_MGTPDC   = 0x040B8, /* Management Packets Dropped Count - R/clr */
 162         E1000_MGTPTC   = 0x040BC, /* Management Packets Tx Count - R/clr */
 163         E1000_TORL     = 0x040C0, /* Total Octets Rx Low - R/clr */
 164         E1000_TORH     = 0x040C4, /* Total Octets Rx High - R/clr */
 165         E1000_TOTL     = 0x040C8, /* Total Octets Tx Low - R/clr */
 166         E1000_TOTH     = 0x040CC, /* Total Octets Tx High - R/clr */
 167         E1000_TPR      = 0x040D0, /* Total Packets Rx - R/clr */
 168         E1000_TPT      = 0x040D4, /* Total Packets Tx - R/clr */
 169         E1000_PTC64    = 0x040D8, /* Packets Tx (64 bytes) - R/clr */
 170         E1000_PTC127   = 0x040DC, /* Packets Tx (65-127 bytes) - R/clr */
 171         E1000_PTC255   = 0x040E0, /* Packets Tx (128-255 bytes) - R/clr */
 172         E1000_PTC511   = 0x040E4, /* Packets Tx (256-511 bytes) - R/clr */
 173         E1000_PTC1023  = 0x040E8, /* Packets Tx (512-1023 bytes) - R/clr */
 174         E1000_PTC1522  = 0x040EC, /* Packets Tx (1024-1522 Bytes) - R/clr */
 175         E1000_MPTC     = 0x040F0, /* Multicast Packets Tx Count - R/clr */
 176         E1000_BPTC     = 0x040F4, /* Broadcast Packets Tx Count - R/clr */
 177         E1000_TSCTC    = 0x040F8, /* TCP Segmentation Context Tx - R/clr */
 178         E1000_TSCTFC   = 0x040FC, /* TCP Segmentation Context Tx Fail - R/clr */
 179         E1000_IAC      = 0x04100, /* Interrupt Assertion Count */
 180         E1000_ICRXPTC  = 0x04104, /* Irq Cause Rx Packet Timer Expire Count */
 181         E1000_ICRXATC  = 0x04108, /* Irq Cause Rx Abs Timer Expire Count */
 182         E1000_ICTXPTC  = 0x0410C, /* Irq Cause Tx Packet Timer Expire Count */
 183         E1000_ICTXATC  = 0x04110, /* Irq Cause Tx Abs Timer Expire Count */
 184         E1000_ICTXQEC  = 0x04118, /* Irq Cause Tx Queue Empty Count */
 185         E1000_ICTXQMTC = 0x0411C, /* Irq Cause Tx Queue MinThreshold Count */
 186         E1000_ICRXDMTC = 0x04120, /* Irq Cause Rx Desc MinThreshold Count */
 187         E1000_ICRXOC   = 0x04124, /* Irq Cause Receiver Overrun Count */
 188         E1000_RXCSUM   = 0x05000, /* Rx Checksum Control - RW */
 189         E1000_RFCTL    = 0x05008, /* Receive Filter Control */
 190         E1000_MTA      = 0x05200, /* Multicast Table Array - RW Array */
 191         E1000_RA       = 0x05400, /* Receive Address - RW Array */
 192         E1000_VFTA     = 0x05600, /* VLAN Filter Table Array - RW Array */
 193         E1000_WUC      = 0x05800, /* Wakeup Control - RW */
 194         E1000_WUFC     = 0x05808, /* Wakeup Filter Control - RW */
 195         E1000_WUS      = 0x05810, /* Wakeup Status - RO */
 196         E1000_MANC     = 0x05820, /* Management Control - RW */
 197         E1000_FFLT     = 0x05F00, /* Flexible Filter Length Table - RW Array */
 198         E1000_HOST_IF  = 0x08800, /* Host Interface */
 199
 200         E1000_KMRNCTRLSTA = 0x00034, /* MAC-PHY interface - RW */
 201         E1000_MANC2H    = 0x05860, /* Management Control To Host - RW */
 202         E1000_SW_FW_SYNC = 0x05B5C, /* Software-Firmware Synchronization - RW */
 203         E1000_GCR       = 0x05B00, /* PCI-Ex Control */
 204         E1000_FACTPS    = 0x05B30, /* Function Active and Power State to MNG */
 205         E1000_SWSM      = 0x05B50, /* SW Semaphore */
 206         E1000_FWSM      = 0x05B54, /* FW Semaphore */
 207         E1000_HICR      = 0x08F00, /* Host Interface Control */
 208 };
 209
 210 /* RSS registers */
 211
 212 /* IGP01E1000 Specific Registers */
 213 #define IGP01E1000_PHY_PORT_CONFIG      0x10 /* Port Config */
 214 #define IGP01E1000_PHY_PORT_STATUS      0x11 /* Status */
 215 #define IGP01E1000_PHY_PORT_CTRL        0x12 /* Control */
 216 #define IGP01E1000_PHY_LINK_HEALTH      0x13 /* PHY Link Health */
 217 #define IGP02E1000_PHY_POWER_MGMT       0x19 /* Power Management */
 218 #define IGP01E1000_PHY_PAGE_SELECT      0x1F /* Page Select */
 219
 220 #define IGP01E1000_PHY_PCS_INIT_REG     0x00B4
 221 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 222
 223 #define IGP01E1000_PSCR_AUTO_MDIX       0x1000
 224 #define IGP01E1000_PSCR_FORCE_MDI_MDIX  0x2000 /* 0=MDI, 1=MDIX */
 225
 226 #define IGP01E1000_PSCFR_SMART_SPEED    0x0080
 227
 228 #define IGP02E1000_PM_SPD               0x0001 /* Smart Power Down */
 229 #define IGP02E1000_PM_D0_LPLU           0x0002 /* For D0a states */
 230 #define IGP02E1000_PM_D3_LPLU           0x0004 /* For all other states */
 231
 232 #define IGP01E1000_PLHR_SS_DOWNGRADE    0x8000
 233
 234 #define IGP01E1000_PSSR_POLARITY_REVERSED       0x0002
 235 #define IGP01E1000_PSSR_MDIX                    0x0008
 236 #define IGP01E1000_PSSR_SPEED_MASK              0xC000
 237 #define IGP01E1000_PSSR_SPEED_1000MBPS          0xC000
 238
 239 #define IGP02E1000_PHY_CHANNEL_NUM              4
 240 #define IGP02E1000_PHY_AGC_A                    0x11B1
 241 #define IGP02E1000_PHY_AGC_B                    0x12B1
 242 #define IGP02E1000_PHY_AGC_C                    0x14B1
 243 #define IGP02E1000_PHY_AGC_D                    0x18B1
 244
 245 #define IGP02E1000_AGC_LENGTH_SHIFT     9 /* Course - 15:13, Fine - 12:9 */
 246 #define IGP02E1000_AGC_LENGTH_MASK      0x7F
 247 #define IGP02E1000_AGC_RANGE            15
 248
 249 /* manage.c */
 250 #define E1000_VFTA_ENTRY_SHIFT          5
 251 #define E1000_VFTA_ENTRY_MASK           0x7F
 252 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F
 253
 254 #define E1000_HICR_EN                   0x01  /* Enable bit - RO */
 255 /* Driver sets this bit when done to put command in RAM */
 256 #define E1000_HICR_C                    0x02
 257 #define E1000_HICR_FW_RESET_ENABLE      0x40
 258 #define E1000_HICR_FW_RESET             0x80
 259
 260 #define E1000_FWSM_MODE_MASK            0xE
 261 #define E1000_FWSM_MODE_SHIFT           1
 262
 263 #define E1000_MNG_IAMT_MODE             0x3
 264 #define E1000_MNG_DHCP_COOKIE_LENGTH    0x10
 265 #define E1000_MNG_DHCP_COOKIE_OFFSET    0x6F0
 266 #define E1000_MNG_DHCP_COMMAND_TIMEOUT  10
 267 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD   64
 268 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING    0x1
 269 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN       0x2
 270
 271 /* nvm.c */
 272 #define E1000_STM_OPCODE  0xDB00
 273
 274 #define E1000_KMRNCTRLSTA_OFFSET        0x001F0000
 275 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT  16
 276 #define E1000_KMRNCTRLSTA_REN           0x00200000
 277 #define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3    /* Kumeran Diagnostic */
 278 #define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000 /* Nearend Loopback mode */
 279
 280 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 281 #define IFE_PHY_SPECIAL_CONTROL         0x11 /* 100BaseTx PHY Special Control */
 282 #define IFE_PHY_SPECIAL_CONTROL_LED     0x1B /* PHY Special and LED Control */
 283 #define IFE_PHY_MDIX_CONTROL            0x1C /* MDI/MDI-X Control */
 284
 285 /* IFE PHY Extended Status Control */
 286 #define IFE_PESC_POLARITY_REVERSED      0x0100
 287
 288 /* IFE PHY Special Control */
 289 #define IFE_PSC_AUTO_POLARITY_DISABLE           0x0010
 290 #define IFE_PSC_FORCE_POLARITY                  0x0020
 291
 292 /* IFE PHY Special Control and LED Control */
 293 #define IFE_PSCL_PROBE_MODE             0x0020
 294 #define IFE_PSCL_PROBE_LEDS_OFF         0x0006 /* Force LEDs 0 and 2 off */
 295 #define IFE_PSCL_PROBE_LEDS_ON          0x0007 /* Force LEDs 0 and 2 on */
 296
 297 /* IFE PHY MDIX Control */
 298 #define IFE_PMC_MDIX_STATUS     0x0020 /* 1=MDI-X, 0=MDI */
 299 #define IFE_PMC_FORCE_MDIX      0x0040 /* 1=force MDI-X, 0=force MDI */
 300 #define IFE_PMC_AUTO_MDIX       0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
 301
 302 #define E1000_CABLE_LENGTH_UNDEFINED    0xFF
 303
 304 #define E1000_DEV_ID_82571EB_COPPER             0x105E
 305 #define E1000_DEV_ID_82571EB_FIBER              0x105F
 306 #define E1000_DEV_ID_82571EB_SERDES             0x1060
 307 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
 308 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
 309 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
 310 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
 311 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
 312 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
 313 #define E1000_DEV_ID_82572EI_COPPER             0x107D
 314 #define E1000_DEV_ID_82572EI_FIBER              0x107E
 315 #define E1000_DEV_ID_82572EI_SERDES             0x107F
 316 #define E1000_DEV_ID_82572EI                    0x10B9
 317 #define E1000_DEV_ID_82573E                     0x108B
 318 #define E1000_DEV_ID_82573E_IAMT                0x108C
 319 #define E1000_DEV_ID_82573L                     0x109A
 320
 321 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 322 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 323 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 324 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 325
 326 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 327 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 328 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 329 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 330 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 331 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 332 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 333 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 334 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 335 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 336 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 337 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 338
 339 #define E1000_FUNC_1 1
 340
 341 enum e1000_mac_type {
 342         e1000_82571,
 343         e1000_82572,
 344         e1000_82573,
 345         e1000_80003es2lan,
 346         e1000_ich8lan,
 347         e1000_ich9lan,
 348 };
 349
 350 enum e1000_media_type {
 351         e1000_media_type_unknown = 0,
 352         e1000_media_type_copper = 1,
 353         e1000_media_type_fiber = 2,
 354         e1000_media_type_internal_serdes = 3,
 355         e1000_num_media_types
 356 };
 357
 358 enum e1000_nvm_type {
 359         e1000_nvm_unknown = 0,
 360         e1000_nvm_none,
 361         e1000_nvm_eeprom_spi,
 362         e1000_nvm_flash_hw,
 363         e1000_nvm_flash_sw
 364 };
 365
 366 enum e1000_nvm_override {
 367         e1000_nvm_override_none = 0,
 368         e1000_nvm_override_spi_small,
 369         e1000_nvm_override_spi_large
 370 };
 371
 372 enum e1000_phy_type {
 373         e1000_phy_unknown = 0,
 374         e1000_phy_none,
 375         e1000_phy_m88,
 376         e1000_phy_igp,
 377         e1000_phy_igp_2,
 378         e1000_phy_gg82563,
 379         e1000_phy_igp_3,
 380         e1000_phy_ife,
 381 };
 382
 383 enum e1000_bus_width {
 384         e1000_bus_width_unknown = 0,
 385         e1000_bus_width_pcie_x1,
 386         e1000_bus_width_pcie_x2,
 387         e1000_bus_width_pcie_x4 = 4,
 388         e1000_bus_width_32,
 389         e1000_bus_width_64,
 390         e1000_bus_width_reserved
 391 };
 392
 393 enum e1000_1000t_rx_status {
 394         e1000_1000t_rx_status_not_ok = 0,
 395         e1000_1000t_rx_status_ok,
 396         e1000_1000t_rx_status_undefined = 0xFF
 397 };
 398
 399 enum e1000_rev_polarity{
 400         e1000_rev_polarity_normal = 0,
 401         e1000_rev_polarity_reversed,
 402         e1000_rev_polarity_undefined = 0xFF
 403 };
 404
 405 enum e1000_fc_type {
 406         e1000_fc_none = 0,
 407         e1000_fc_rx_pause,
 408         e1000_fc_tx_pause,
 409         e1000_fc_full,
 410         e1000_fc_default = 0xFF
 411 };
 412
 413 enum e1000_ms_type {
 414         e1000_ms_hw_default = 0,
 415         e1000_ms_force_master,
 416         e1000_ms_force_slave,
 417         e1000_ms_auto
 418 };
 419
 420 enum e1000_smart_speed {
 421         e1000_smart_speed_default = 0,
 422         e1000_smart_speed_on,
 423         e1000_smart_speed_off
 424 };
 425
 426 /* Receive Descriptor */
 427 struct e1000_rx_desc {
 428         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 429         __le16 length;      /* Length of data DMAed into data buffer */
 430         __le16 csum;    /* Packet checksum */
 431         u8  status;      /* Descriptor status */
 432         u8  errors;      /* Descriptor Errors */
 433         __le16 special;
 434 };
 435
 436 /* Receive Descriptor - Extended */
 437 union e1000_rx_desc_extended {
 438         struct {
 439                 __le64 buffer_addr;
 440                 __le64 reserved;
 441         } read;
 442         struct {
 443                 struct {
 444                         __le32 mrq;           /* Multiple Rx Queues */
 445                         union {
 446                                 __le32 rss;         /* RSS Hash */
 447                                 struct {
 448                                         __le16 ip_id;  /* IP id */
 449                                         __le16 csum;   /* Packet Checksum */
 450                                 } csum_ip;
 451                         } hi_dword;
 452                 } lower;
 453                 struct {
 454                         __le32 status_error;     /* ext status/error */
 455                         __le16 length;
 456                         __le16 vlan;         /* VLAN tag */
 457                 } upper;
 458         } wb;  /* writeback */
 459 };
 460
 461 #define MAX_PS_BUFFERS 4
 462 /* Receive Descriptor - Packet Split */
 463 union e1000_rx_desc_packet_split {
 464         struct {
 465                 /* one buffer for protocol header(s), three data buffers */
 466                 __le64 buffer_addr[MAX_PS_BUFFERS];
 467         } read;
 468         struct {
 469                 struct {
 470                         __le32 mrq;           /* Multiple Rx Queues */
 471                         union {
 472                                 __le32 rss;           /* RSS Hash */
 473                                 struct {
 474                                         __le16 ip_id;    /* IP id */
 475                                         __le16 csum;     /* Packet Checksum */
 476                                 } csum_ip;
 477                         } hi_dword;
 478                 } lower;
 479                 struct {
 480                         __le32 status_error;     /* ext status/error */
 481                         __le16 length0;   /* length of buffer 0 */
 482                         __le16 vlan;         /* VLAN tag */
 483                 } middle;
 484                 struct {
 485                         __le16 header_status;
 486                         __le16 length[3];       /* length of buffers 1-3 */
 487                 } upper;
 488                 __le64 reserved;
 489         } wb; /* writeback */
 490 };
 491
 492 /* Transmit Descriptor */
 493 struct e1000_tx_desc {
 494         __le64 buffer_addr;      /* Address of the descriptor's data buffer */
 495         union {
 496                 __le32 data;
 497                 struct {
 498                         __le16 length;    /* Data buffer length */
 499                         u8 cso; /* Checksum offset */
 500                         u8 cmd; /* Descriptor control */
 501                 } flags;
 502         } lower;
 503         union {
 504                 __le32 data;
 505                 struct {
 506                         u8 status;     /* Descriptor status */
 507                         u8 css; /* Checksum start */
 508                         __le16 special;
 509                 } fields;
 510         } upper;
 511 };
 512
 513 /* Offload Context Descriptor */
 514 struct e1000_context_desc {
 515         union {
 516                 __le32 ip_config;
 517                 struct {
 518                         u8 ipcss;      /* IP checksum start */
 519                         u8 ipcso;      /* IP checksum offset */
 520                         __le16 ipcse;     /* IP checksum end */
 521                 } ip_fields;
 522         } lower_setup;
 523         union {
 524                 __le32 tcp_config;
 525                 struct {
 526                         u8 tucss;      /* TCP checksum start */
 527                         u8 tucso;      /* TCP checksum offset */
 528                         __le16 tucse;     /* TCP checksum end */
 529                 } tcp_fields;
 530         } upper_setup;
 531         __le32 cmd_and_length;
 532         union {
 533                 __le32 data;
 534                 struct {
 535                         u8 status;     /* Descriptor status */
 536                         u8 hdr_len;    /* Header length */
 537                         __le16 mss;       /* Maximum segment size */
 538                 } fields;
 539         } tcp_seg_setup;
 540 };
 541
 542 /* Offload data descriptor */
 543 struct e1000_data_desc {
 544         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 545         union {
 546                 __le32 data;
 547                 struct {
 548                         __le16 length;    /* Data buffer length */
 549                         u8 typ_len_ext;
 550                         u8 cmd;
 551                 } flags;
 552         } lower;
 553         union {
 554                 __le32 data;
 555                 struct {
 556                         u8 status;     /* Descriptor status */
 557                         u8 popts;      /* Packet Options */
 558                         __le16 special;   /* */
 559                 } fields;
 560         } upper;
 561 };
 562
 563 /* Statistics counters collected by the MAC */
 564 struct e1000_hw_stats {
 565         u64 crcerrs;
 566         u64 algnerrc;
 567         u64 symerrs;
 568         u64 rxerrc;
 569         u64 mpc;
 570         u64 scc;
 571         u64 ecol;
 572         u64 mcc;
 573         u64 latecol;
 574         u64 colc;
 575         u64 dc;
 576         u64 tncrs;
 577         u64 sec;
 578         u64 cexterr;
 579         u64 rlec;
 580         u64 xonrxc;
 581         u64 xontxc;
 582         u64 xoffrxc;
 583         u64 xofftxc;
 584         u64 fcruc;
 585         u64 prc64;
 586         u64 prc127;
 587         u64 prc255;
 588         u64 prc511;
 589         u64 prc1023;
 590         u64 prc1522;
 591         u64 gprc;
 592         u64 bprc;
 593         u64 mprc;
 594         u64 gptc;
 595         u64 gorcl;
 596         u64 gorch;
 597         u64 gotcl;
 598         u64 gotch;
 599         u64 rnbc;
 600         u64 ruc;
 601         u64 rfc;
 602         u64 roc;
 603         u64 rjc;
 604         u64 mgprc;
 605         u64 mgpdc;
 606         u64 mgptc;
 607         u64 torl;
 608         u64 torh;
 609         u64 totl;
 610         u64 toth;
 611         u64 tpr;
 612         u64 tpt;
 613         u64 ptc64;
 614         u64 ptc127;
 615         u64 ptc255;
 616         u64 ptc511;
 617         u64 ptc1023;
 618         u64 ptc1522;
 619         u64 mptc;
 620         u64 bptc;
 621         u64 tsctc;
 622         u64 tsctfc;
 623         u64 iac;
 624         u64 icrxptc;
 625         u64 icrxatc;
 626         u64 ictxptc;
 627         u64 ictxatc;
 628         u64 ictxqec;
 629         u64 ictxqmtc;
 630         u64 icrxdmtc;
 631         u64 icrxoc;
 632 };
 633
 634 struct e1000_phy_stats {
 635         u32 idle_errors;
 636         u32 receive_errors;
 637 };
 638
 639 struct e1000_host_mng_dhcp_cookie {
 640         u32 signature;
 641         u8  status;
 642         u8  reserved0;
 643         u16 vlan_id;
 644         u32 reserved1;
 645         u16 reserved2;
 646         u8  reserved3;
 647         u8  checksum;
 648 };
 649
 650 /* Host Interface "Rev 1" */
 651 struct e1000_host_command_header {
 652         u8 command_id;
 653         u8 command_length;
 654         u8 command_options;
 655         u8 checksum;
 656 };
 657
 658 #define E1000_HI_MAX_DATA_LENGTH     252
 659 struct e1000_host_command_info {
 660         struct e1000_host_command_header command_header;
 661         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 662 };
 663
 664 /* Host Interface "Rev 2" */
 665 struct e1000_host_mng_command_header {
 666         u8  command_id;
 667         u8  checksum;
 668         u16 reserved1;
 669         u16 reserved2;
 670         u16 command_length;
 671 };
 672
 673 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 674 struct e1000_host_mng_command_info {
 675         struct e1000_host_mng_command_header command_header;
 676         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 677 };
 678
 679 /* Function pointers and static data for the MAC. */
 680 struct e1000_mac_operations {
 681         u32                     mng_mode_enab;
 682
 683         s32  (*check_for_link)(struct e1000_hw *);
 684         s32  (*cleanup_led)(struct e1000_hw *);
 685         void (*clear_hw_cntrs)(struct e1000_hw *);
 686         s32  (*get_bus_info)(struct e1000_hw *);
 687         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 688         s32  (*led_on)(struct e1000_hw *);
 689         s32  (*led_off)(struct e1000_hw *);
 690         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
 691         s32  (*reset_hw)(struct e1000_hw *);
 692         s32  (*init_hw)(struct e1000_hw *);
 693         s32  (*setup_link)(struct e1000_hw *);
 694         s32  (*setup_physical_interface)(struct e1000_hw *);
 695 };
 696
 697 /* Function pointers for the PHY. */
 698 struct e1000_phy_operations {
 699         s32  (*acquire_phy)(struct e1000_hw *);
 700         s32  (*check_reset_block)(struct e1000_hw *);
 701         s32  (*commit_phy)(struct e1000_hw *);
 702         s32  (*force_speed_duplex)(struct e1000_hw *);
 703         s32  (*get_cfg_done)(struct e1000_hw *hw);
 704         s32  (*get_cable_length)(struct e1000_hw *);
 705         s32  (*get_phy_info)(struct e1000_hw *);
 706         s32  (*read_phy_reg)(struct e1000_hw *, u32, u16 *);
 707         void (*release_phy)(struct e1000_hw *);
 708         s32  (*reset_phy)(struct e1000_hw *);
 709         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 710         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 711         s32  (*write_phy_reg)(struct e1000_hw *, u32, u16);
 712 };
 713
 714 /* Function pointers for the NVM. */
 715 struct e1000_nvm_operations {
 716         s32  (*acquire_nvm)(struct e1000_hw *);
 717         s32  (*read_nvm)(struct e1000_hw *, u16, u16, u16 *);
 718         void (*release_nvm)(struct e1000_hw *);
 719         s32  (*update_nvm)(struct e1000_hw *);
 720         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 721         s32  (*validate_nvm)(struct e1000_hw *);
 722         s32  (*write_nvm)(struct e1000_hw *, u16, u16, u16 *);
 723 };
 724
 725 struct e1000_mac_info {
 726         struct e1000_mac_operations ops;
 727
 728         u8 addr[6];
 729         u8 perm_addr[6];
 730
 731         enum e1000_mac_type type;
 732
 733         u32 collision_delta;
 734         u32 ledctl_default;
 735         u32 ledctl_mode1;
 736         u32 ledctl_mode2;
 737         u32 mc_filter_type;
 738         u32 tx_packet_delta;
 739         u32 txcw;
 740
 741         u16 current_ifs_val;
 742         u16 ifs_max_val;
 743         u16 ifs_min_val;
 744         u16 ifs_ratio;
 745         u16 ifs_step_size;
 746         u16 mta_reg_count;
 747         u16 rar_entry_count;
 748
 749         u8  forced_speed_duplex;
 750
 751         bool arc_subsystem_valid;
 752         bool autoneg;
 753         bool autoneg_failed;
 754         bool get_link_status;
 755         bool in_ifs_mode;
 756         bool serdes_has_link;
 757         bool tx_pkt_filtering;
 758 };
 759
 760 struct e1000_phy_info {
 761         struct e1000_phy_operations ops;
 762
 763         enum e1000_phy_type type;
 764
 765         enum e1000_1000t_rx_status local_rx;
 766         enum e1000_1000t_rx_status remote_rx;
 767         enum e1000_ms_type ms_type;
 768         enum e1000_ms_type original_ms_type;
 769         enum e1000_rev_polarity cable_polarity;
 770         enum e1000_smart_speed smart_speed;
 771
 772         u32 addr;
 773         u32 id;
 774         u32 reset_delay_us; /* in usec */
 775         u32 revision;
 776
 777         enum e1000_media_type media_type;
 778
 779         u16 autoneg_advertised;
 780         u16 autoneg_mask;
 781         u16 cable_length;
 782         u16 max_cable_length;
 783         u16 min_cable_length;
 784
 785         u8 mdix;
 786
 787         bool disable_polarity_correction;
 788         bool is_mdix;
 789         bool polarity_correction;
 790         bool speed_downgraded;
 791         bool autoneg_wait_to_complete;
 792 };
 793
 794 struct e1000_nvm_info {
 795         struct e1000_nvm_operations ops;
 796
 797         enum e1000_nvm_type type;
 798         enum e1000_nvm_override override;
 799
 800         u32 flash_bank_size;
 801         u32 flash_base_addr;
 802
 803         u16 word_size;
 804         u16 delay_usec;
 805         u16 address_bits;
 806         u16 opcode_bits;
 807         u16 page_size;
 808 };
 809
 810 struct e1000_bus_info {
 811         enum e1000_bus_width width;
 812
 813         u16 func;
 814 };
 815
 816 struct e1000_fc_info {
 817         u32 high_water;          /* Flow control high-water mark */
 818         u32 low_water;           /* Flow control low-water mark */
 819         u16 pause_time;          /* Flow control pause timer */
 820         bool send_xon;           /* Flow control send XON */
 821         bool strict_ieee;        /* Strict IEEE mode */
 822         enum e1000_fc_type type; /* Type of flow control */
 823         enum e1000_fc_type original_type;
 824 };
 825
 826 struct e1000_dev_spec_82571 {
 827         bool laa_is_present;
 828         bool alt_mac_addr_is_present;
 829 };
 830
 831 struct e1000_shadow_ram {
 832         u16  value;
 833         bool modified;
 834 };
 835
 836 #define E1000_ICH8_SHADOW_RAM_WORDS             2048
 837
 838 struct e1000_dev_spec_ich8lan {
 839         bool kmrn_lock_loss_workaround_enabled;
 840         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
 841 };
 842
 843 struct e1000_hw {
 844         struct e1000_adapter *adapter;
 845
 846         u8 __iomem *hw_addr;
 847         u8 __iomem *flash_address;
 848
 849         struct e1000_mac_info  mac;
 850         struct e1000_fc_info   fc;
 851         struct e1000_phy_info  phy;
 852         struct e1000_nvm_info  nvm;
 853         struct e1000_bus_info  bus;
 854         struct e1000_host_mng_dhcp_cookie mng_cookie;
 855
 856         union {
 857                 struct e1000_dev_spec_82571     e82571;
 858                 struct e1000_dev_spec_ich8lan   ich8lan;
 859         } dev_spec;
 860 };
 861
 862 #ifdef DEBUG
 863 #define hw_dbg(hw, format, arg...) \
 864         printk(KERN_DEBUG "%s: " format, e1000e_get_hw_dev_name(hw), ##arg)
 865 #else
 866 static inline int __attribute__ ((format (printf, 2, 3)))
 867 hw_dbg(struct e1000_hw *hw, const char *format, ...)
 868 {
 869         return 0;
 870 }
 871 #endif
 872
 873 #endif