3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <net/iw_handler.h>
44 #include "bcm43xx_main.h"
45 #include "bcm43xx_debugfs.h"
46 #include "bcm43xx_radio.h"
47 #include "bcm43xx_phy.h"
48 #include "bcm43xx_dma.h"
49 #include "bcm43xx_pio.h"
50 #include "bcm43xx_power.h"
51 #include "bcm43xx_wx.h"
52 #include "bcm43xx_ethtool.h"
53 #include "bcm43xx_xmit.h"
56 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
57 MODULE_AUTHOR("Martin Langer");
58 MODULE_AUTHOR("Stefano Brivio");
59 MODULE_AUTHOR("Michael Buesch");
60 MODULE_LICENSE("GPL");
62 #ifdef CONFIG_BCM947XX
63 extern char *nvram_get(char *name
);
66 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
67 static int modparam_pio
;
68 module_param_named(pio
, modparam_pio
, int, 0444);
69 MODULE_PARM_DESC(pio
, "enable(1) / disable(0) PIO mode");
70 #elif defined(CONFIG_BCM43XX_DMA)
71 # define modparam_pio 0
72 #elif defined(CONFIG_BCM43XX_PIO)
73 # define modparam_pio 1
76 static int modparam_bad_frames_preempt
;
77 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
78 MODULE_PARM_DESC(bad_frames_preempt
, "enable(1) / disable(0) Bad Frames Preemption");
80 static int modparam_short_retry
= BCM43xx_DEFAULT_SHORT_RETRY_LIMIT
;
81 module_param_named(short_retry
, modparam_short_retry
, int, 0444);
82 MODULE_PARM_DESC(short_retry
, "Short-Retry-Limit (0 - 15)");
84 static int modparam_long_retry
= BCM43xx_DEFAULT_LONG_RETRY_LIMIT
;
85 module_param_named(long_retry
, modparam_long_retry
, int, 0444);
86 MODULE_PARM_DESC(long_retry
, "Long-Retry-Limit (0 - 15)");
88 static int modparam_locale
= -1;
89 module_param_named(locale
, modparam_locale
, int, 0444);
90 MODULE_PARM_DESC(country
, "Select LocaleCode 0-11 (For travelers)");
92 static int modparam_noleds
;
93 module_param_named(noleds
, modparam_noleds
, int, 0444);
94 MODULE_PARM_DESC(noleds
, "Turn off all LED activity");
96 #ifdef CONFIG_BCM43XX_DEBUG
97 static char modparam_fwpostfix
[64];
98 module_param_string(fwpostfix
, modparam_fwpostfix
, 64, 0444);
99 MODULE_PARM_DESC(fwpostfix
, "Postfix for .fw files. Useful for debugging.");
101 # define modparam_fwpostfix ""
102 #endif /* CONFIG_BCM43XX_DEBUG*/
105 /* If you want to debug with just a single device, enable this,
106 * where the string is the pci device ID (as given by the kernel's
107 * pci_name function) of the device to be used.
109 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
111 /* If you want to enable printing of each MMIO access, enable this. */
112 //#define DEBUG_ENABLE_MMIO_PRINT
114 /* If you want to enable printing of MMIO access within
115 * ucode/pcm upload, initvals write, enable this.
117 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
119 /* If you want to enable printing of PCI Config Space access, enable this */
120 //#define DEBUG_ENABLE_PCILOG
123 /* Detailed list maintained at:
124 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
126 static struct pci_device_id bcm43xx_pci_tbl
[] = {
127 /* Broadcom 4303 802.11b */
128 { PCI_VENDOR_ID_BROADCOM
, 0x4301, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
129 /* Broadcom 4307 802.11b */
130 { PCI_VENDOR_ID_BROADCOM
, 0x4307, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
131 /* Broadcom 4318 802.11b/g */
132 { PCI_VENDOR_ID_BROADCOM
, 0x4318, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
133 /* Broadcom 4306 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM
, 0x4320, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
135 /* Broadcom 4306 802.11a */
136 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4309 802.11a/b/g */
138 { PCI_VENDOR_ID_BROADCOM
, 0x4324, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
139 /* Broadcom 43XG 802.11b/g */
140 { PCI_VENDOR_ID_BROADCOM
, 0x4325, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
141 #ifdef CONFIG_BCM947XX
142 /* SB bus on BCM947xx */
143 { PCI_VENDOR_ID_BROADCOM
, 0x0800, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0 },
147 MODULE_DEVICE_TABLE(pci
, bcm43xx_pci_tbl
);
149 static void bcm43xx_ram_write(struct bcm43xx_private
*bcm
, u16 offset
, u32 val
)
153 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
154 if (!(status
& BCM43xx_SBF_XFER_REG_BYTESWAP
))
157 bcm43xx_write32(bcm
, BCM43xx_MMIO_RAM_CONTROL
, offset
);
159 bcm43xx_write32(bcm
, BCM43xx_MMIO_RAM_DATA
, val
);
163 void bcm43xx_shm_control_word(struct bcm43xx_private
*bcm
,
164 u16 routing
, u16 offset
)
168 /* "offset" is the WORD offset. */
173 bcm43xx_write32(bcm
, BCM43xx_MMIO_SHM_CONTROL
, control
);
176 u32
bcm43xx_shm_read32(struct bcm43xx_private
*bcm
,
177 u16 routing
, u16 offset
)
181 if (routing
== BCM43xx_SHM_SHARED
) {
182 if (offset
& 0x0003) {
183 /* Unaligned access */
184 bcm43xx_shm_control_word(bcm
, routing
, offset
>> 2);
185 ret
= bcm43xx_read16(bcm
, BCM43xx_MMIO_SHM_DATA_UNALIGNED
);
187 bcm43xx_shm_control_word(bcm
, routing
, (offset
>> 2) + 1);
188 ret
|= bcm43xx_read16(bcm
, BCM43xx_MMIO_SHM_DATA
);
194 bcm43xx_shm_control_word(bcm
, routing
, offset
);
195 ret
= bcm43xx_read32(bcm
, BCM43xx_MMIO_SHM_DATA
);
200 u16
bcm43xx_shm_read16(struct bcm43xx_private
*bcm
,
201 u16 routing
, u16 offset
)
205 if (routing
== BCM43xx_SHM_SHARED
) {
206 if (offset
& 0x0003) {
207 /* Unaligned access */
208 bcm43xx_shm_control_word(bcm
, routing
, offset
>> 2);
209 ret
= bcm43xx_read16(bcm
, BCM43xx_MMIO_SHM_DATA_UNALIGNED
);
215 bcm43xx_shm_control_word(bcm
, routing
, offset
);
216 ret
= bcm43xx_read16(bcm
, BCM43xx_MMIO_SHM_DATA
);
221 void bcm43xx_shm_write32(struct bcm43xx_private
*bcm
,
222 u16 routing
, u16 offset
,
225 if (routing
== BCM43xx_SHM_SHARED
) {
226 if (offset
& 0x0003) {
227 /* Unaligned access */
228 bcm43xx_shm_control_word(bcm
, routing
, offset
>> 2);
230 bcm43xx_write16(bcm
, BCM43xx_MMIO_SHM_DATA_UNALIGNED
,
231 (value
>> 16) & 0xffff);
233 bcm43xx_shm_control_word(bcm
, routing
, (offset
>> 2) + 1);
235 bcm43xx_write16(bcm
, BCM43xx_MMIO_SHM_DATA
,
241 bcm43xx_shm_control_word(bcm
, routing
, offset
);
243 bcm43xx_write32(bcm
, BCM43xx_MMIO_SHM_DATA
, value
);
246 void bcm43xx_shm_write16(struct bcm43xx_private
*bcm
,
247 u16 routing
, u16 offset
,
250 if (routing
== BCM43xx_SHM_SHARED
) {
251 if (offset
& 0x0003) {
252 /* Unaligned access */
253 bcm43xx_shm_control_word(bcm
, routing
, offset
>> 2);
255 bcm43xx_write16(bcm
, BCM43xx_MMIO_SHM_DATA_UNALIGNED
,
261 bcm43xx_shm_control_word(bcm
, routing
, offset
);
263 bcm43xx_write16(bcm
, BCM43xx_MMIO_SHM_DATA
, value
);
266 void bcm43xx_tsf_read(struct bcm43xx_private
*bcm
, u64
*tsf
)
268 /* We need to be careful. As we read the TSF from multiple
269 * registers, we should take care of register overflows.
270 * In theory, the whole tsf read process should be atomic.
271 * We try to be atomic here, by restaring the read process,
272 * if any of the high registers changed (overflew).
274 if (bcm
->current_core
->rev
>= 3) {
275 u32 low
, high
, high2
;
278 high
= bcm43xx_read32(bcm
, BCM43xx_MMIO_REV3PLUS_TSF_HIGH
);
279 low
= bcm43xx_read32(bcm
, BCM43xx_MMIO_REV3PLUS_TSF_LOW
);
280 high2
= bcm43xx_read32(bcm
, BCM43xx_MMIO_REV3PLUS_TSF_HIGH
);
281 } while (unlikely(high
!= high2
));
289 u16 test1
, test2
, test3
;
292 v3
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_3
);
293 v2
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_2
);
294 v1
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_1
);
295 v0
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_0
);
297 test3
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_3
);
298 test2
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_2
);
299 test1
= bcm43xx_read16(bcm
, BCM43xx_MMIO_TSF_1
);
300 } while (v3
!= test3
|| v2
!= test2
|| v1
!= test1
);
314 void bcm43xx_tsf_write(struct bcm43xx_private
*bcm
, u64 tsf
)
318 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
319 status
|= BCM43xx_SBF_TIME_UPDATE
;
320 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
323 /* Be careful with the in-progress timer.
324 * First zero out the low register, so we have a full
325 * register-overflow duration to complete the operation.
327 if (bcm
->current_core
->rev
>= 3) {
328 u32 lo
= (tsf
& 0x00000000FFFFFFFFULL
);
329 u32 hi
= (tsf
& 0xFFFFFFFF00000000ULL
) >> 32;
331 bcm43xx_write32(bcm
, BCM43xx_MMIO_REV3PLUS_TSF_LOW
, 0);
333 bcm43xx_write32(bcm
, BCM43xx_MMIO_REV3PLUS_TSF_HIGH
, hi
);
335 bcm43xx_write32(bcm
, BCM43xx_MMIO_REV3PLUS_TSF_LOW
, lo
);
337 u16 v0
= (tsf
& 0x000000000000FFFFULL
);
338 u16 v1
= (tsf
& 0x00000000FFFF0000ULL
) >> 16;
339 u16 v2
= (tsf
& 0x0000FFFF00000000ULL
) >> 32;
340 u16 v3
= (tsf
& 0xFFFF000000000000ULL
) >> 48;
342 bcm43xx_write16(bcm
, BCM43xx_MMIO_TSF_0
, 0);
344 bcm43xx_write16(bcm
, BCM43xx_MMIO_TSF_3
, v3
);
346 bcm43xx_write16(bcm
, BCM43xx_MMIO_TSF_2
, v2
);
348 bcm43xx_write16(bcm
, BCM43xx_MMIO_TSF_1
, v1
);
350 bcm43xx_write16(bcm
, BCM43xx_MMIO_TSF_0
, v0
);
353 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
354 status
&= ~BCM43xx_SBF_TIME_UPDATE
;
355 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
359 void bcm43xx_macfilter_set(struct bcm43xx_private
*bcm
,
366 bcm43xx_write16(bcm
, BCM43xx_MMIO_MACFILTER_CONTROL
, offset
);
370 bcm43xx_write16(bcm
, BCM43xx_MMIO_MACFILTER_DATA
, data
);
373 bcm43xx_write16(bcm
, BCM43xx_MMIO_MACFILTER_DATA
, data
);
376 bcm43xx_write16(bcm
, BCM43xx_MMIO_MACFILTER_DATA
, data
);
379 static void bcm43xx_macfilter_clear(struct bcm43xx_private
*bcm
,
382 const u8 zero_addr
[ETH_ALEN
] = { 0 };
384 bcm43xx_macfilter_set(bcm
, offset
, zero_addr
);
387 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private
*bcm
)
389 const u8
*mac
= (const u8
*)(bcm
->net_dev
->dev_addr
);
390 const u8
*bssid
= (const u8
*)(bcm
->ieee
->bssid
);
391 u8 mac_bssid
[ETH_ALEN
* 2];
394 memcpy(mac_bssid
, mac
, ETH_ALEN
);
395 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
397 /* Write our MAC address and BSSID to template ram */
398 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
))
399 bcm43xx_ram_write(bcm
, 0x20 + i
, *((u32
*)(mac_bssid
+ i
)));
400 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
))
401 bcm43xx_ram_write(bcm
, 0x78 + i
, *((u32
*)(mac_bssid
+ i
)));
402 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
))
403 bcm43xx_ram_write(bcm
, 0x478 + i
, *((u32
*)(mac_bssid
+ i
)));
406 static void bcm43xx_set_slot_time(struct bcm43xx_private
*bcm
, u16 slot_time
)
408 /* slot_time is in usec. */
409 if (bcm43xx_current_phy(bcm
)->type
!= BCM43xx_PHYTYPE_G
)
411 bcm43xx_write16(bcm
, 0x684, 510 + slot_time
);
412 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0010, slot_time
);
415 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private
*bcm
)
417 bcm43xx_set_slot_time(bcm
, 9);
420 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private
*bcm
)
422 bcm43xx_set_slot_time(bcm
, 20);
425 //FIXME: rename this func?
426 static void bcm43xx_disassociate(struct bcm43xx_private
*bcm
)
428 bcm43xx_mac_suspend(bcm
);
429 bcm43xx_macfilter_clear(bcm
, BCM43xx_MACFILTER_ASSOC
);
431 bcm43xx_ram_write(bcm
, 0x0026, 0x0000);
432 bcm43xx_ram_write(bcm
, 0x0028, 0x0000);
433 bcm43xx_ram_write(bcm
, 0x007E, 0x0000);
434 bcm43xx_ram_write(bcm
, 0x0080, 0x0000);
435 bcm43xx_ram_write(bcm
, 0x047E, 0x0000);
436 bcm43xx_ram_write(bcm
, 0x0480, 0x0000);
438 if (bcm
->current_core
->rev
< 3) {
439 bcm43xx_write16(bcm
, 0x0610, 0x8000);
440 bcm43xx_write16(bcm
, 0x060E, 0x0000);
442 bcm43xx_write32(bcm
, 0x0188, 0x80000000);
444 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_WIRELESS
, 0x0004, 0x000003ff);
446 if (bcm43xx_current_phy(bcm
)->type
== BCM43xx_PHYTYPE_G
&&
447 ieee80211_is_ofdm_rate(bcm
->softmac
->txrates
.default_rate
))
448 bcm43xx_short_slot_timing_enable(bcm
);
450 bcm43xx_mac_enable(bcm
);
453 //FIXME: rename this func?
454 static void bcm43xx_associate(struct bcm43xx_private
*bcm
,
457 memcpy(bcm
->ieee
->bssid
, mac
, ETH_ALEN
);
459 bcm43xx_mac_suspend(bcm
);
460 bcm43xx_macfilter_set(bcm
, BCM43xx_MACFILTER_ASSOC
, mac
);
461 bcm43xx_write_mac_bssid_templates(bcm
);
462 bcm43xx_mac_enable(bcm
);
465 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
466 * Returns the _previously_ enabled IRQ mask.
468 static inline u32
bcm43xx_interrupt_enable(struct bcm43xx_private
*bcm
, u32 mask
)
472 old_mask
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_MASK
);
473 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_MASK
, old_mask
| mask
);
478 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
479 * Returns the _previously_ enabled IRQ mask.
481 static inline u32
bcm43xx_interrupt_disable(struct bcm43xx_private
*bcm
, u32 mask
)
485 old_mask
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_MASK
);
486 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_MASK
, old_mask
& ~mask
);
491 /* Make sure we don't receive more data from the device. */
492 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private
*bcm
, u32
*oldstate
)
497 bcm43xx_lock_mmio(bcm
, flags
);
498 if (bcm43xx_is_initializing(bcm
) || bcm
->shutting_down
) {
499 bcm43xx_unlock_mmio(bcm
, flags
);
502 old
= bcm43xx_interrupt_disable(bcm
, BCM43xx_IRQ_ALL
);
503 tasklet_disable(&bcm
->isr_tasklet
);
504 bcm43xx_unlock_mmio(bcm
, flags
);
511 static int bcm43xx_read_radioinfo(struct bcm43xx_private
*bcm
)
513 struct bcm43xx_radioinfo
*radio
= bcm43xx_current_radio(bcm
);
514 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
521 if (bcm
->chip_id
== 0x4317) {
522 if (bcm
->chip_rev
== 0x00)
523 radio_id
= 0x3205017F;
524 else if (bcm
->chip_rev
== 0x01)
525 radio_id
= 0x4205017F;
527 radio_id
= 0x5205017F;
529 bcm43xx_write16(bcm
, BCM43xx_MMIO_RADIO_CONTROL
, BCM43xx_RADIOCTL_ID
);
530 radio_id
= bcm43xx_read16(bcm
, BCM43xx_MMIO_RADIO_DATA_HIGH
);
532 bcm43xx_write16(bcm
, BCM43xx_MMIO_RADIO_CONTROL
, BCM43xx_RADIOCTL_ID
);
533 radio_id
|= bcm43xx_read16(bcm
, BCM43xx_MMIO_RADIO_DATA_LOW
);
536 manufact
= (radio_id
& 0x00000FFF);
537 version
= (radio_id
& 0x0FFFF000) >> 12;
538 revision
= (radio_id
& 0xF0000000) >> 28;
540 dprintk(KERN_INFO PFX
"Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
541 radio_id
, manufact
, version
, revision
);
544 case BCM43xx_PHYTYPE_A
:
545 if ((version
!= 0x2060) || (revision
!= 1) || (manufact
!= 0x17f))
546 goto err_unsupported_radio
;
548 case BCM43xx_PHYTYPE_B
:
549 if ((version
& 0xFFF0) != 0x2050)
550 goto err_unsupported_radio
;
552 case BCM43xx_PHYTYPE_G
:
553 if (version
!= 0x2050)
554 goto err_unsupported_radio
;
558 radio
->manufact
= manufact
;
559 radio
->version
= version
;
560 radio
->revision
= revision
;
562 /* Set default attenuation values. */
563 radio
->txpower
[0] = 2;
564 radio
->txpower
[1] = 2;
566 radio
->txpower
[2] = 3;
568 radio
->txpower
[2] = 0;
569 if (phy
->type
== BCM43xx_PHYTYPE_A
)
570 radio
->txpower_desired
= bcm
->sprom
.maxpower_aphy
;
572 radio
->txpower_desired
= bcm
->sprom
.maxpower_bgphy
;
574 /* Initialize the in-memory nrssi Lookup Table. */
575 for (i
= 0; i
< 64; i
++)
576 radio
->nrssi_lt
[i
] = i
;
580 err_unsupported_radio
:
581 printk(KERN_ERR PFX
"Unsupported Radio connected to the PHY!\n");
585 static const char * bcm43xx_locale_iso(u8 locale
)
587 /* ISO 3166-1 country codes.
588 * Note that there aren't ISO 3166-1 codes for
589 * all or locales. (Not all locales are countries)
592 case BCM43xx_LOCALE_WORLD
:
593 case BCM43xx_LOCALE_ALL
:
595 case BCM43xx_LOCALE_THAILAND
:
597 case BCM43xx_LOCALE_ISRAEL
:
599 case BCM43xx_LOCALE_JORDAN
:
601 case BCM43xx_LOCALE_CHINA
:
603 case BCM43xx_LOCALE_JAPAN
:
604 case BCM43xx_LOCALE_JAPAN_HIGH
:
606 case BCM43xx_LOCALE_USA_CANADA_ANZ
:
607 case BCM43xx_LOCALE_USA_LOW
:
609 case BCM43xx_LOCALE_EUROPE
:
611 case BCM43xx_LOCALE_NONE
:
618 static const char * bcm43xx_locale_string(u8 locale
)
621 case BCM43xx_LOCALE_WORLD
:
623 case BCM43xx_LOCALE_THAILAND
:
625 case BCM43xx_LOCALE_ISRAEL
:
627 case BCM43xx_LOCALE_JORDAN
:
629 case BCM43xx_LOCALE_CHINA
:
631 case BCM43xx_LOCALE_JAPAN
:
633 case BCM43xx_LOCALE_USA_CANADA_ANZ
:
634 return "USA/Canada/ANZ";
635 case BCM43xx_LOCALE_EUROPE
:
637 case BCM43xx_LOCALE_USA_LOW
:
639 case BCM43xx_LOCALE_JAPAN_HIGH
:
641 case BCM43xx_LOCALE_ALL
:
643 case BCM43xx_LOCALE_NONE
:
650 static inline u8
bcm43xx_crc8(u8 crc
, u8 data
)
652 static const u8 t
[] = {
653 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
654 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
655 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
656 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
657 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
658 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
659 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
660 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
661 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
662 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
663 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
664 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
665 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
666 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
667 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
668 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
669 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
670 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
671 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
672 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
673 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
674 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
675 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
676 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
677 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
678 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
679 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
680 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
681 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
682 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
683 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
684 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
686 return t
[crc
^ data
];
689 static u8
bcm43xx_sprom_crc(const u16
*sprom
)
694 for (word
= 0; word
< BCM43xx_SPROM_SIZE
- 1; word
++) {
695 crc
= bcm43xx_crc8(crc
, sprom
[word
] & 0x00FF);
696 crc
= bcm43xx_crc8(crc
, (sprom
[word
] & 0xFF00) >> 8);
698 crc
= bcm43xx_crc8(crc
, sprom
[BCM43xx_SPROM_VERSION
] & 0x00FF);
704 int bcm43xx_sprom_read(struct bcm43xx_private
*bcm
, u16
*sprom
)
707 u8 crc
, expected_crc
;
709 for (i
= 0; i
< BCM43xx_SPROM_SIZE
; i
++)
710 sprom
[i
] = bcm43xx_read16(bcm
, BCM43xx_SPROM_BASE
+ (i
* 2));
712 crc
= bcm43xx_sprom_crc(sprom
);
713 expected_crc
= (sprom
[BCM43xx_SPROM_VERSION
] & 0xFF00) >> 8;
714 if (crc
!= expected_crc
) {
715 printk(KERN_WARNING PFX
"WARNING: Invalid SPROM checksum "
716 "(0x%02X, expected: 0x%02X)\n",
724 int bcm43xx_sprom_write(struct bcm43xx_private
*bcm
, const u16
*sprom
)
727 u8 crc
, expected_crc
;
730 /* CRC-8 validation of the input data. */
731 crc
= bcm43xx_sprom_crc(sprom
);
732 expected_crc
= (sprom
[BCM43xx_SPROM_VERSION
] & 0xFF00) >> 8;
733 if (crc
!= expected_crc
) {
734 printk(KERN_ERR PFX
"SPROM input data: Invalid CRC\n");
738 printk(KERN_INFO PFX
"Writing SPROM. Do NOT turn off the power! Please stand by...\n");
739 err
= bcm43xx_pci_read_config32(bcm
, BCM43xx_PCICFG_SPROMCTL
, &spromctl
);
742 spromctl
|= 0x10; /* SPROM WRITE enable. */
743 bcm43xx_pci_write_config32(bcm
, BCM43xx_PCICFG_SPROMCTL
, spromctl
);
746 /* We must burn lots of CPU cycles here, but that does not
747 * really matter as one does not write the SPROM every other minute...
749 printk(KERN_INFO PFX
"[ 0%%");
751 for (i
= 0; i
< BCM43xx_SPROM_SIZE
; i
++) {
760 bcm43xx_write16(bcm
, BCM43xx_SPROM_BASE
+ (i
* 2), sprom
[i
]);
764 spromctl
&= ~0x10; /* SPROM WRITE enable. */
765 bcm43xx_pci_write_config32(bcm
, BCM43xx_PCICFG_SPROMCTL
, spromctl
);
770 printk(KERN_INFO PFX
"SPROM written.\n");
771 bcm43xx_controller_restart(bcm
, "SPROM update");
775 printk(KERN_ERR PFX
"Could not access SPROM control register.\n");
779 static int bcm43xx_sprom_extract(struct bcm43xx_private
*bcm
)
783 #ifdef CONFIG_BCM947XX
787 sprom
= kzalloc(BCM43xx_SPROM_SIZE
* sizeof(u16
),
790 printk(KERN_ERR PFX
"sprom_extract OOM\n");
793 #ifdef CONFIG_BCM947XX
794 sprom
[BCM43xx_SPROM_BOARDFLAGS2
] = atoi(nvram_get("boardflags2"));
795 sprom
[BCM43xx_SPROM_BOARDFLAGS
] = atoi(nvram_get("boardflags"));
797 if ((c
= nvram_get("il0macaddr")) != NULL
)
798 e_aton(c
, (char *) &(sprom
[BCM43xx_SPROM_IL0MACADDR
]));
800 if ((c
= nvram_get("et1macaddr")) != NULL
)
801 e_aton(c
, (char *) &(sprom
[BCM43xx_SPROM_ET1MACADDR
]));
803 sprom
[BCM43xx_SPROM_PA0B0
] = atoi(nvram_get("pa0b0"));
804 sprom
[BCM43xx_SPROM_PA0B1
] = atoi(nvram_get("pa0b1"));
805 sprom
[BCM43xx_SPROM_PA0B2
] = atoi(nvram_get("pa0b2"));
807 sprom
[BCM43xx_SPROM_PA1B0
] = atoi(nvram_get("pa1b0"));
808 sprom
[BCM43xx_SPROM_PA1B1
] = atoi(nvram_get("pa1b1"));
809 sprom
[BCM43xx_SPROM_PA1B2
] = atoi(nvram_get("pa1b2"));
811 sprom
[BCM43xx_SPROM_BOARDREV
] = atoi(nvram_get("boardrev"));
813 bcm43xx_sprom_read(bcm
, sprom
);
817 value
= sprom
[BCM43xx_SPROM_BOARDFLAGS2
];
818 bcm
->sprom
.boardflags2
= value
;
821 value
= sprom
[BCM43xx_SPROM_IL0MACADDR
+ 0];
822 *(((u16
*)bcm
->sprom
.il0macaddr
) + 0) = cpu_to_be16(value
);
823 value
= sprom
[BCM43xx_SPROM_IL0MACADDR
+ 1];
824 *(((u16
*)bcm
->sprom
.il0macaddr
) + 1) = cpu_to_be16(value
);
825 value
= sprom
[BCM43xx_SPROM_IL0MACADDR
+ 2];
826 *(((u16
*)bcm
->sprom
.il0macaddr
) + 2) = cpu_to_be16(value
);
829 value
= sprom
[BCM43xx_SPROM_ET0MACADDR
+ 0];
830 *(((u16
*)bcm
->sprom
.et0macaddr
) + 0) = cpu_to_be16(value
);
831 value
= sprom
[BCM43xx_SPROM_ET0MACADDR
+ 1];
832 *(((u16
*)bcm
->sprom
.et0macaddr
) + 1) = cpu_to_be16(value
);
833 value
= sprom
[BCM43xx_SPROM_ET0MACADDR
+ 2];
834 *(((u16
*)bcm
->sprom
.et0macaddr
) + 2) = cpu_to_be16(value
);
837 value
= sprom
[BCM43xx_SPROM_ET1MACADDR
+ 0];
838 *(((u16
*)bcm
->sprom
.et1macaddr
) + 0) = cpu_to_be16(value
);
839 value
= sprom
[BCM43xx_SPROM_ET1MACADDR
+ 1];
840 *(((u16
*)bcm
->sprom
.et1macaddr
) + 1) = cpu_to_be16(value
);
841 value
= sprom
[BCM43xx_SPROM_ET1MACADDR
+ 2];
842 *(((u16
*)bcm
->sprom
.et1macaddr
) + 2) = cpu_to_be16(value
);
844 /* ethernet phy settings */
845 value
= sprom
[BCM43xx_SPROM_ETHPHY
];
846 bcm
->sprom
.et0phyaddr
= (value
& 0x001F);
847 bcm
->sprom
.et1phyaddr
= (value
& 0x03E0) >> 5;
848 bcm
->sprom
.et0mdcport
= (value
& (1 << 14)) >> 14;
849 bcm
->sprom
.et1mdcport
= (value
& (1 << 15)) >> 15;
851 /* boardrev, antennas, locale */
852 value
= sprom
[BCM43xx_SPROM_BOARDREV
];
853 bcm
->sprom
.boardrev
= (value
& 0x00FF);
854 bcm
->sprom
.locale
= (value
& 0x0F00) >> 8;
855 bcm
->sprom
.antennas_aphy
= (value
& 0x3000) >> 12;
856 bcm
->sprom
.antennas_bgphy
= (value
& 0xC000) >> 14;
857 if (modparam_locale
!= -1) {
858 if (modparam_locale
>= 0 && modparam_locale
<= 11) {
859 bcm
->sprom
.locale
= modparam_locale
;
860 printk(KERN_WARNING PFX
"Operating with modified "
861 "LocaleCode %u (%s)\n",
863 bcm43xx_locale_string(bcm
->sprom
.locale
));
865 printk(KERN_WARNING PFX
"Module parameter \"locale\" "
866 "invalid value. (0 - 11)\n");
871 value
= sprom
[BCM43xx_SPROM_PA0B0
];
872 bcm
->sprom
.pa0b0
= value
;
873 value
= sprom
[BCM43xx_SPROM_PA0B1
];
874 bcm
->sprom
.pa0b1
= value
;
875 value
= sprom
[BCM43xx_SPROM_PA0B2
];
876 bcm
->sprom
.pa0b2
= value
;
879 value
= sprom
[BCM43xx_SPROM_WL0GPIO0
];
882 bcm
->sprom
.wl0gpio0
= value
& 0x00FF;
883 bcm
->sprom
.wl0gpio1
= (value
& 0xFF00) >> 8;
884 value
= sprom
[BCM43xx_SPROM_WL0GPIO2
];
887 bcm
->sprom
.wl0gpio2
= value
& 0x00FF;
888 bcm
->sprom
.wl0gpio3
= (value
& 0xFF00) >> 8;
891 value
= sprom
[BCM43xx_SPROM_MAXPWR
];
892 bcm
->sprom
.maxpower_aphy
= (value
& 0xFF00) >> 8;
893 bcm
->sprom
.maxpower_bgphy
= value
& 0x00FF;
896 value
= sprom
[BCM43xx_SPROM_PA1B0
];
897 bcm
->sprom
.pa1b0
= value
;
898 value
= sprom
[BCM43xx_SPROM_PA1B1
];
899 bcm
->sprom
.pa1b1
= value
;
900 value
= sprom
[BCM43xx_SPROM_PA1B2
];
901 bcm
->sprom
.pa1b2
= value
;
903 /* idle tssi target */
904 value
= sprom
[BCM43xx_SPROM_IDL_TSSI_TGT
];
905 bcm
->sprom
.idle_tssi_tgt_aphy
= value
& 0x00FF;
906 bcm
->sprom
.idle_tssi_tgt_bgphy
= (value
& 0xFF00) >> 8;
909 value
= sprom
[BCM43xx_SPROM_BOARDFLAGS
];
912 bcm
->sprom
.boardflags
= value
;
915 value
= sprom
[BCM43xx_SPROM_ANTENNA_GAIN
];
916 if (value
== 0x0000 || value
== 0xFFFF)
918 /* convert values to Q5.2 */
919 bcm
->sprom
.antennagain_aphy
= ((value
& 0xFF00) >> 8) * 4;
920 bcm
->sprom
.antennagain_bgphy
= (value
& 0x00FF) * 4;
927 static void bcm43xx_geo_init(struct bcm43xx_private
*bcm
)
929 struct ieee80211_geo geo
;
930 struct ieee80211_channel
*chan
;
931 int have_a
= 0, have_bg
= 0;
934 struct bcm43xx_phyinfo
*phy
;
935 const char *iso_country
;
937 memset(&geo
, 0, sizeof(geo
));
938 for (i
= 0; i
< bcm
->nr_80211_available
; i
++) {
939 phy
= &(bcm
->core_80211_ext
[i
].phy
);
941 case BCM43xx_PHYTYPE_B
:
942 case BCM43xx_PHYTYPE_G
:
945 case BCM43xx_PHYTYPE_A
:
952 iso_country
= bcm43xx_locale_iso(bcm
->sprom
.locale
);
955 for (i
= 0, channel
= 0; channel
< 201; channel
++) {
957 chan
->freq
= bcm43xx_channel_to_freq_a(channel
);
958 chan
->channel
= channel
;
963 for (i
= 0, channel
= 1; channel
< 15; channel
++) {
965 chan
->freq
= bcm43xx_channel_to_freq_bg(channel
);
966 chan
->channel
= channel
;
970 memcpy(geo
.name
, iso_country
, 2);
971 if (0 /*TODO: Outdoor use only */)
973 else if (0 /*TODO: Indoor use only */)
979 ieee80211_set_geo(bcm
->ieee
, &geo
);
982 /* DummyTransmission function, as documented on
983 * http://bcm-specs.sipsolutions.net/DummyTransmission
985 void bcm43xx_dummy_transmission(struct bcm43xx_private
*bcm
)
987 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
988 struct bcm43xx_radioinfo
*radio
= bcm43xx_current_radio(bcm
);
989 unsigned int i
, max_loop
;
999 /* FIXME: It seems like a dummy_transmission corrupts the DMA engines,
1000 * once they are initialized. So avoid doing a dummy_transmission,
1001 * if the DMA engines are running.
1003 if (bcm
->initialized
)
1006 switch (phy
->type
) {
1007 case BCM43xx_PHYTYPE_A
:
1009 buffer
[0] = 0xCC010200;
1011 case BCM43xx_PHYTYPE_B
:
1012 case BCM43xx_PHYTYPE_G
:
1014 buffer
[0] = 0x6E840B00;
1021 for (i
= 0; i
< 5; i
++)
1022 bcm43xx_ram_write(bcm
, i
* 4, buffer
[i
]);
1024 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
); /* dummy read */
1026 bcm43xx_write16(bcm
, 0x0568, 0x0000);
1027 bcm43xx_write16(bcm
, 0x07C0, 0x0000);
1028 bcm43xx_write16(bcm
, 0x050C, ((phy
->type
== BCM43xx_PHYTYPE_A
) ? 1 : 0));
1029 bcm43xx_write16(bcm
, 0x0508, 0x0000);
1030 bcm43xx_write16(bcm
, 0x050A, 0x0000);
1031 bcm43xx_write16(bcm
, 0x054C, 0x0000);
1032 bcm43xx_write16(bcm
, 0x056A, 0x0014);
1033 bcm43xx_write16(bcm
, 0x0568, 0x0826);
1034 bcm43xx_write16(bcm
, 0x0500, 0x0000);
1035 bcm43xx_write16(bcm
, 0x0502, 0x0030);
1037 if (radio
->version
== 0x2050 && radio
->revision
<= 0x5)
1038 bcm43xx_radio_write16(bcm
, 0x0051, 0x0017);
1039 for (i
= 0x00; i
< max_loop
; i
++) {
1040 value
= bcm43xx_read16(bcm
, 0x050E);
1045 for (i
= 0x00; i
< 0x0A; i
++) {
1046 value
= bcm43xx_read16(bcm
, 0x050E);
1051 for (i
= 0x00; i
< 0x0A; i
++) {
1052 value
= bcm43xx_read16(bcm
, 0x0690);
1053 if (!(value
& 0x0100))
1057 if (radio
->version
== 0x2050 && radio
->revision
<= 0x5)
1058 bcm43xx_radio_write16(bcm
, 0x0051, 0x0037);
1061 static void key_write(struct bcm43xx_private
*bcm
,
1062 u8 index
, u8 algorithm
, const u16
*key
)
1064 unsigned int i
, basic_wep
= 0;
1068 /* Write associated key information */
1069 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x100 + (index
* 2),
1070 ((index
<< 4) | (algorithm
& 0x0F)));
1072 /* The first 4 WEP keys need extra love */
1073 if (((algorithm
== BCM43xx_SEC_ALGO_WEP
) ||
1074 (algorithm
== BCM43xx_SEC_ALGO_WEP104
)) && (index
< 4))
1077 /* Write key payload, 8 little endian words */
1078 offset
= bcm
->security_offset
+ (index
* BCM43xx_SEC_KEYSIZE
);
1079 for (i
= 0; i
< (BCM43xx_SEC_KEYSIZE
/ sizeof(u16
)); i
++) {
1080 value
= cpu_to_le16(key
[i
]);
1081 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
,
1082 offset
+ (i
* 2), value
);
1087 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
,
1088 offset
+ (i
* 2) + 4 * BCM43xx_SEC_KEYSIZE
,
1093 static void keymac_write(struct bcm43xx_private
*bcm
,
1094 u8 index
, const u32
*addr
)
1096 /* for keys 0-3 there is no associated mac address */
1101 if (bcm
->current_core
->rev
>= 5) {
1102 bcm43xx_shm_write32(bcm
,
1105 cpu_to_be32(*addr
));
1106 bcm43xx_shm_write16(bcm
,
1109 cpu_to_be16(*((u16
*)(addr
+ 1))));
1112 TODO(); /* Put them in the macaddress filter */
1115 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1116 Keep in mind to update the count of keymacs in 0x003E as well! */
1121 static int bcm43xx_key_write(struct bcm43xx_private
*bcm
,
1122 u8 index
, u8 algorithm
,
1123 const u8
*_key
, int key_len
,
1126 u8 key
[BCM43xx_SEC_KEYSIZE
] = { 0 };
1128 if (index
>= ARRAY_SIZE(bcm
->key
))
1130 if (key_len
> ARRAY_SIZE(key
))
1132 if (algorithm
< 1 || algorithm
> 5)
1135 memcpy(key
, _key
, key_len
);
1136 key_write(bcm
, index
, algorithm
, (const u16
*)key
);
1137 keymac_write(bcm
, index
, (const u32
*)mac_addr
);
1139 bcm
->key
[index
].algorithm
= algorithm
;
1144 static void bcm43xx_clear_keys(struct bcm43xx_private
*bcm
)
1146 static const u32 zero_mac
[2] = { 0 };
1147 unsigned int i
,j
, nr_keys
= 54;
1150 if (bcm
->current_core
->rev
< 5)
1152 assert(nr_keys
<= ARRAY_SIZE(bcm
->key
));
1154 for (i
= 0; i
< nr_keys
; i
++) {
1155 bcm
->key
[i
].enabled
= 0;
1156 /* returns for i < 4 immediately */
1157 keymac_write(bcm
, i
, zero_mac
);
1158 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
,
1159 0x100 + (i
* 2), 0x0000);
1160 for (j
= 0; j
< 8; j
++) {
1161 offset
= bcm
->security_offset
+ (j
* 4) + (i
* BCM43xx_SEC_KEYSIZE
);
1162 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
,
1166 dprintk(KERN_INFO PFX
"Keys cleared\n");
1169 /* Lowlevel core-switch function. This is only to be used in
1170 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1172 static int _switch_core(struct bcm43xx_private
*bcm
, int core
)
1180 err
= bcm43xx_pci_write_config32(bcm
, BCM43xx_PCICFG_ACTIVE_CORE
,
1181 (core
* 0x1000) + 0x18000000);
1184 err
= bcm43xx_pci_read_config32(bcm
, BCM43xx_PCICFG_ACTIVE_CORE
,
1188 current_core
= (current_core
- 0x18000000) / 0x1000;
1189 if (current_core
== core
)
1192 if (unlikely(attempts
++ > BCM43xx_SWITCH_CORE_MAX_RETRIES
))
1196 #ifdef CONFIG_BCM947XX
1197 if (bcm
->pci_dev
->bus
->number
== 0)
1198 bcm
->current_core_offset
= 0x1000 * core
;
1200 bcm
->current_core_offset
= 0;
1205 printk(KERN_ERR PFX
"Failed to switch to core %d\n", core
);
1209 int bcm43xx_switch_core(struct bcm43xx_private
*bcm
, struct bcm43xx_coreinfo
*new_core
)
1213 if (unlikely(!new_core
))
1215 if (!new_core
->available
)
1217 if (bcm
->current_core
== new_core
)
1219 err
= _switch_core(bcm
, new_core
->index
);
1223 bcm
->current_core
= new_core
;
1224 bcm
->current_80211_core_idx
= -1;
1225 if (new_core
->id
== BCM43xx_COREID_80211
)
1226 bcm
->current_80211_core_idx
= (int)(new_core
- &(bcm
->core_80211
[0]));
1232 static int bcm43xx_core_enabled(struct bcm43xx_private
*bcm
)
1236 value
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
1237 value
&= BCM43xx_SBTMSTATELOW_CLOCK
| BCM43xx_SBTMSTATELOW_RESET
1238 | BCM43xx_SBTMSTATELOW_REJECT
;
1240 return (value
== BCM43xx_SBTMSTATELOW_CLOCK
);
1243 /* disable current core */
1244 static int bcm43xx_core_disable(struct bcm43xx_private
*bcm
, u32 core_flags
)
1250 /* fetch sbtmstatelow from core information registers */
1251 sbtmstatelow
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
1253 /* core is already in reset */
1254 if (sbtmstatelow
& BCM43xx_SBTMSTATELOW_RESET
)
1257 if (sbtmstatelow
& BCM43xx_SBTMSTATELOW_CLOCK
) {
1258 sbtmstatelow
= BCM43xx_SBTMSTATELOW_CLOCK
|
1259 BCM43xx_SBTMSTATELOW_REJECT
;
1260 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1262 for (i
= 0; i
< 1000; i
++) {
1263 sbtmstatelow
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
1264 if (sbtmstatelow
& BCM43xx_SBTMSTATELOW_REJECT
) {
1271 printk(KERN_ERR PFX
"Error: core_disable() REJECT timeout!\n");
1275 for (i
= 0; i
< 1000; i
++) {
1276 sbtmstatehigh
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATEHIGH
);
1277 if (!(sbtmstatehigh
& BCM43xx_SBTMSTATEHIGH_BUSY
)) {
1284 printk(KERN_ERR PFX
"Error: core_disable() BUSY timeout!\n");
1288 sbtmstatelow
= BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK
|
1289 BCM43xx_SBTMSTATELOW_REJECT
|
1290 BCM43xx_SBTMSTATELOW_RESET
|
1291 BCM43xx_SBTMSTATELOW_CLOCK
|
1293 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1297 sbtmstatelow
= BCM43xx_SBTMSTATELOW_RESET
|
1298 BCM43xx_SBTMSTATELOW_REJECT
|
1300 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1303 bcm
->current_core
->enabled
= 0;
1308 /* enable (reset) current core */
1309 static int bcm43xx_core_enable(struct bcm43xx_private
*bcm
, u32 core_flags
)
1316 err
= bcm43xx_core_disable(bcm
, core_flags
);
1320 sbtmstatelow
= BCM43xx_SBTMSTATELOW_CLOCK
|
1321 BCM43xx_SBTMSTATELOW_RESET
|
1322 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK
|
1324 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1327 sbtmstatehigh
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATEHIGH
);
1328 if (sbtmstatehigh
& BCM43xx_SBTMSTATEHIGH_SERROR
) {
1329 sbtmstatehigh
= 0x00000000;
1330 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATEHIGH
, sbtmstatehigh
);
1333 sbimstate
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBIMSTATE
);
1334 if (sbimstate
& (BCM43xx_SBIMSTATE_IB_ERROR
| BCM43xx_SBIMSTATE_TIMEOUT
)) {
1335 sbimstate
&= ~(BCM43xx_SBIMSTATE_IB_ERROR
| BCM43xx_SBIMSTATE_TIMEOUT
);
1336 bcm43xx_write32(bcm
, BCM43xx_CIR_SBIMSTATE
, sbimstate
);
1339 sbtmstatelow
= BCM43xx_SBTMSTATELOW_CLOCK
|
1340 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK
|
1342 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1345 sbtmstatelow
= BCM43xx_SBTMSTATELOW_CLOCK
| core_flags
;
1346 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1349 bcm
->current_core
->enabled
= 1;
1355 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1356 void bcm43xx_wireless_core_reset(struct bcm43xx_private
*bcm
, int connect_phy
)
1358 u32 flags
= 0x00040000;
1360 if ((bcm43xx_core_enabled(bcm
)) &&
1361 !bcm43xx_using_pio(bcm
)) {
1362 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1363 #ifndef CONFIG_BCM947XX
1364 /* reset all used DMA controllers. */
1365 bcm43xx_dmacontroller_tx_reset(bcm
, BCM43xx_MMIO_DMA1_BASE
);
1366 bcm43xx_dmacontroller_tx_reset(bcm
, BCM43xx_MMIO_DMA2_BASE
);
1367 bcm43xx_dmacontroller_tx_reset(bcm
, BCM43xx_MMIO_DMA3_BASE
);
1368 bcm43xx_dmacontroller_tx_reset(bcm
, BCM43xx_MMIO_DMA4_BASE
);
1369 bcm43xx_dmacontroller_rx_reset(bcm
, BCM43xx_MMIO_DMA1_BASE
);
1370 if (bcm
->current_core
->rev
< 5)
1371 bcm43xx_dmacontroller_rx_reset(bcm
, BCM43xx_MMIO_DMA4_BASE
);
1374 if (bcm
->shutting_down
) {
1375 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
,
1376 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
)
1377 & ~(BCM43xx_SBF_MAC_ENABLED
| 0x00000002));
1380 flags
|= 0x20000000;
1381 bcm43xx_phy_connect(bcm
, connect_phy
);
1382 bcm43xx_core_enable(bcm
, flags
);
1383 bcm43xx_write16(bcm
, 0x03E6, 0x0000);
1384 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
,
1385 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
)
1390 static void bcm43xx_wireless_core_disable(struct bcm43xx_private
*bcm
)
1392 bcm43xx_radio_turn_off(bcm
);
1393 bcm43xx_write16(bcm
, 0x03E6, 0x00F4);
1394 bcm43xx_core_disable(bcm
, 0);
1397 /* Mark the current 80211 core inactive.
1398 * "active_80211_core" is the other 80211 core, which is used.
1400 static int bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private
*bcm
,
1401 struct bcm43xx_coreinfo
*active_80211_core
)
1404 struct bcm43xx_coreinfo
*old_core
;
1407 bcm43xx_interrupt_disable(bcm
, BCM43xx_IRQ_ALL
);
1408 bcm43xx_radio_turn_off(bcm
);
1409 sbtmstatelow
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
1410 sbtmstatelow
&= ~0x200a0000;
1411 sbtmstatelow
|= 0xa0000;
1412 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1414 sbtmstatelow
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
1415 sbtmstatelow
&= ~0xa0000;
1416 sbtmstatelow
|= 0x80000;
1417 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1420 if (bcm43xx_current_phy(bcm
)->type
== BCM43xx_PHYTYPE_G
) {
1421 old_core
= bcm
->current_core
;
1422 err
= bcm43xx_switch_core(bcm
, active_80211_core
);
1425 sbtmstatelow
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
1426 sbtmstatelow
&= ~0x20000000;
1427 sbtmstatelow
|= 0x20000000;
1428 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, sbtmstatelow
);
1429 err
= bcm43xx_switch_core(bcm
, old_core
);
1436 static void handle_irq_transmit_status(struct bcm43xx_private
*bcm
)
1440 struct bcm43xx_xmitstatus stat
;
1443 v0
= bcm43xx_read32(bcm
, BCM43xx_MMIO_XMITSTAT_0
);
1446 v1
= bcm43xx_read32(bcm
, BCM43xx_MMIO_XMITSTAT_1
);
1448 stat
.cookie
= (v0
>> 16) & 0x0000FFFF;
1449 tmp
= (u16
)((v0
& 0xFFF0) | ((v0
& 0xF) >> 1));
1450 stat
.flags
= tmp
& 0xFF;
1451 stat
.cnt1
= (tmp
& 0x0F00) >> 8;
1452 stat
.cnt2
= (tmp
& 0xF000) >> 12;
1453 stat
.seq
= (u16
)(v1
& 0xFFFF);
1454 stat
.unknown
= (u16
)((v1
>> 16) & 0xFF);
1456 bcm43xx_debugfs_log_txstat(bcm
, &stat
);
1458 if (stat
.flags
& BCM43xx_TXSTAT_FLAG_IGNORE
)
1460 if (!(stat
.flags
& BCM43xx_TXSTAT_FLAG_ACK
)) {
1461 //TODO: packet was not acked (was lost)
1463 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1465 if (bcm43xx_using_pio(bcm
))
1466 bcm43xx_pio_handle_xmitstatus(bcm
, &stat
);
1468 bcm43xx_dma_handle_xmitstatus(bcm
, &stat
);
1472 static void bcm43xx_generate_noise_sample(struct bcm43xx_private
*bcm
)
1474 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x408, 0x7F7F);
1475 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x40A, 0x7F7F);
1476 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
,
1477 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
) | (1 << 4));
1478 assert(bcm
->noisecalc
.core_at_start
== bcm
->current_core
);
1479 assert(bcm
->noisecalc
.channel_at_start
== bcm43xx_current_radio(bcm
)->channel
);
1482 static void bcm43xx_calculate_link_quality(struct bcm43xx_private
*bcm
)
1484 /* Top half of Link Quality calculation. */
1486 if (bcm
->noisecalc
.calculation_running
)
1488 bcm
->noisecalc
.core_at_start
= bcm
->current_core
;
1489 bcm
->noisecalc
.channel_at_start
= bcm43xx_current_radio(bcm
)->channel
;
1490 bcm
->noisecalc
.calculation_running
= 1;
1491 bcm
->noisecalc
.nr_samples
= 0;
1493 bcm43xx_generate_noise_sample(bcm
);
1496 static void handle_irq_noise(struct bcm43xx_private
*bcm
)
1498 struct bcm43xx_radioinfo
*radio
= bcm43xx_current_radio(bcm
);
1504 /* Bottom half of Link Quality calculation. */
1506 assert(bcm
->noisecalc
.calculation_running
);
1507 if (bcm
->noisecalc
.core_at_start
!= bcm
->current_core
||
1508 bcm
->noisecalc
.channel_at_start
!= radio
->channel
)
1509 goto drop_calculation
;
1510 tmp
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, 0x408);
1511 noise
[0] = (tmp
& 0x00FF);
1512 noise
[1] = (tmp
& 0xFF00) >> 8;
1513 tmp
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, 0x40A);
1514 noise
[2] = (tmp
& 0x00FF);
1515 noise
[3] = (tmp
& 0xFF00) >> 8;
1516 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1517 noise
[2] == 0x7F || noise
[3] == 0x7F)
1520 /* Get the noise samples. */
1521 assert(bcm
->noisecalc
.nr_samples
<= 8);
1522 i
= bcm
->noisecalc
.nr_samples
;
1523 noise
[0] = limit_value(noise
[0], 0, ARRAY_SIZE(radio
->nrssi_lt
) - 1);
1524 noise
[1] = limit_value(noise
[1], 0, ARRAY_SIZE(radio
->nrssi_lt
) - 1);
1525 noise
[2] = limit_value(noise
[2], 0, ARRAY_SIZE(radio
->nrssi_lt
) - 1);
1526 noise
[3] = limit_value(noise
[3], 0, ARRAY_SIZE(radio
->nrssi_lt
) - 1);
1527 bcm
->noisecalc
.samples
[i
][0] = radio
->nrssi_lt
[noise
[0]];
1528 bcm
->noisecalc
.samples
[i
][1] = radio
->nrssi_lt
[noise
[1]];
1529 bcm
->noisecalc
.samples
[i
][2] = radio
->nrssi_lt
[noise
[2]];
1530 bcm
->noisecalc
.samples
[i
][3] = radio
->nrssi_lt
[noise
[3]];
1531 bcm
->noisecalc
.nr_samples
++;
1532 if (bcm
->noisecalc
.nr_samples
== 8) {
1533 /* Calculate the Link Quality by the noise samples. */
1535 for (i
= 0; i
< 8; i
++) {
1536 for (j
= 0; j
< 4; j
++)
1537 average
+= bcm
->noisecalc
.samples
[i
][j
];
1543 tmp
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, 0x40C);
1544 tmp
= (tmp
/ 128) & 0x1F;
1555 bcm
->stats
.link_quality
= 0;
1556 else if (average
> -75)
1557 bcm
->stats
.link_quality
= 1;
1558 else if (average
> -85)
1559 bcm
->stats
.link_quality
= 2;
1561 bcm
->stats
.link_quality
= 3;
1562 // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1564 bcm
->noisecalc
.calculation_running
= 0;
1568 bcm43xx_generate_noise_sample(bcm
);
1571 static void handle_irq_ps(struct bcm43xx_private
*bcm
)
1573 if (bcm
->ieee
->iw_mode
== IW_MODE_MASTER
) {
1576 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1577 bcm43xx_power_saving_ctl_bits(bcm
, -1, -1);
1579 if (bcm
->ieee
->iw_mode
== IW_MODE_ADHOC
)
1580 bcm
->reg124_set_0x4
= 1;
1581 //FIXME else set to false?
1584 static void handle_irq_reg124(struct bcm43xx_private
*bcm
)
1586 if (!bcm
->reg124_set_0x4
)
1588 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
,
1589 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
)
1591 //FIXME: reset reg124_set_0x4 to false?
1594 static void handle_irq_pmq(struct bcm43xx_private
*bcm
)
1601 tmp
= bcm43xx_read32(bcm
, BCM43xx_MMIO_PS_STATUS
);
1602 if (!(tmp
& 0x00000008))
1605 /* 16bit write is odd, but correct. */
1606 bcm43xx_write16(bcm
, BCM43xx_MMIO_PS_STATUS
, 0x0002);
1609 static void bcm43xx_generate_beacon_template(struct bcm43xx_private
*bcm
,
1610 u16 ram_offset
, u16 shm_size_offset
)
1616 //FIXME: assumption: The chip sets the timestamp
1618 bcm43xx_ram_write(bcm
, ram_offset
++, value
);
1619 bcm43xx_ram_write(bcm
, ram_offset
++, value
);
1622 /* Beacon Interval / Capability Information */
1623 value
= 0x0000;//FIXME: Which interval?
1624 value
|= (1 << 0) << 16; /* ESS */
1625 value
|= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1626 value
|= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1627 if (!bcm
->ieee
->open_wep
)
1628 value
|= (1 << 4) << 16; /* Privacy */
1629 bcm43xx_ram_write(bcm
, ram_offset
++, value
);
1635 /* FH Parameter Set */
1638 /* DS Parameter Set */
1641 /* CF Parameter Set */
1647 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, shm_size_offset
, size
);
1650 static void handle_irq_beacon(struct bcm43xx_private
*bcm
)
1654 bcm
->irq_savedstate
&= ~BCM43xx_IRQ_BEACON
;
1655 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
);
1657 if ((status
& 0x1) && (status
& 0x2)) {
1658 /* ACK beacon IRQ. */
1659 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
,
1660 BCM43xx_IRQ_BEACON
);
1661 bcm
->irq_savedstate
|= BCM43xx_IRQ_BEACON
;
1664 if (!(status
& 0x1)) {
1665 bcm43xx_generate_beacon_template(bcm
, 0x68, 0x18);
1667 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
, status
);
1669 if (!(status
& 0x2)) {
1670 bcm43xx_generate_beacon_template(bcm
, 0x468, 0x1A);
1672 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS2_BITFIELD
, status
);
1676 /* Interrupt handler bottom-half */
1677 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private
*bcm
)
1682 unsigned long flags
;
1684 #ifdef CONFIG_BCM43XX_DEBUG
1685 u32 _handled
= 0x00000000;
1686 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1688 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1689 #endif /* CONFIG_BCM43XX_DEBUG*/
1691 bcm43xx_lock_mmio(bcm
, flags
);
1692 reason
= bcm
->irq_reason
;
1693 dma_reason
[0] = bcm
->dma_reason
[0];
1694 dma_reason
[1] = bcm
->dma_reason
[1];
1695 dma_reason
[2] = bcm
->dma_reason
[2];
1696 dma_reason
[3] = bcm
->dma_reason
[3];
1698 if (unlikely(reason
& BCM43xx_IRQ_XMIT_ERROR
)) {
1699 /* TX error. We get this when Template Ram is written in wrong endianess
1700 * in dummy_tx(). We also get this if something is wrong with the TX header
1701 * on DMA or PIO queues.
1702 * Maybe we get this in other error conditions, too.
1704 printkl(KERN_ERR PFX
"FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1705 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR
);
1707 if (unlikely((dma_reason
[0] & BCM43xx_DMAIRQ_FATALMASK
) |
1708 (dma_reason
[1] & BCM43xx_DMAIRQ_FATALMASK
) |
1709 (dma_reason
[2] & BCM43xx_DMAIRQ_FATALMASK
) |
1710 (dma_reason
[3] & BCM43xx_DMAIRQ_FATALMASK
))) {
1711 printkl(KERN_ERR PFX
"FATAL ERROR: Fatal DMA error: "
1712 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1713 dma_reason
[0], dma_reason
[1],
1714 dma_reason
[2], dma_reason
[3]);
1715 bcm43xx_controller_restart(bcm
, "DMA error");
1716 bcm43xx_unlock_mmio(bcm
, flags
);
1719 if (unlikely((dma_reason
[0] & BCM43xx_DMAIRQ_NONFATALMASK
) |
1720 (dma_reason
[1] & BCM43xx_DMAIRQ_NONFATALMASK
) |
1721 (dma_reason
[2] & BCM43xx_DMAIRQ_NONFATALMASK
) |
1722 (dma_reason
[3] & BCM43xx_DMAIRQ_NONFATALMASK
))) {
1723 printkl(KERN_ERR PFX
"DMA error: "
1724 "0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
1725 dma_reason
[0], dma_reason
[1],
1726 dma_reason
[2], dma_reason
[3]);
1729 if (reason
& BCM43xx_IRQ_PS
) {
1731 bcmirq_handled(BCM43xx_IRQ_PS
);
1734 if (reason
& BCM43xx_IRQ_REG124
) {
1735 handle_irq_reg124(bcm
);
1736 bcmirq_handled(BCM43xx_IRQ_REG124
);
1739 if (reason
& BCM43xx_IRQ_BEACON
) {
1740 if (bcm
->ieee
->iw_mode
== IW_MODE_MASTER
)
1741 handle_irq_beacon(bcm
);
1742 bcmirq_handled(BCM43xx_IRQ_BEACON
);
1745 if (reason
& BCM43xx_IRQ_PMQ
) {
1746 handle_irq_pmq(bcm
);
1747 bcmirq_handled(BCM43xx_IRQ_PMQ
);
1750 if (reason
& BCM43xx_IRQ_SCAN
) {
1752 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1755 if (reason
& BCM43xx_IRQ_NOISE
) {
1756 handle_irq_noise(bcm
);
1757 bcmirq_handled(BCM43xx_IRQ_NOISE
);
1760 /* Check the DMA reason registers for received data. */
1761 assert(!(dma_reason
[1] & BCM43xx_DMAIRQ_RX_DONE
));
1762 assert(!(dma_reason
[2] & BCM43xx_DMAIRQ_RX_DONE
));
1763 if (dma_reason
[0] & BCM43xx_DMAIRQ_RX_DONE
) {
1764 if (bcm43xx_using_pio(bcm
))
1765 bcm43xx_pio_rx(bcm43xx_current_pio(bcm
)->queue0
);
1767 bcm43xx_dma_rx(bcm43xx_current_dma(bcm
)->rx_ring0
);
1768 /* We intentionally don't set "activity" to 1, here. */
1770 if (dma_reason
[3] & BCM43xx_DMAIRQ_RX_DONE
) {
1771 if (bcm43xx_using_pio(bcm
))
1772 bcm43xx_pio_rx(bcm43xx_current_pio(bcm
)->queue3
);
1774 bcm43xx_dma_rx(bcm43xx_current_dma(bcm
)->rx_ring1
);
1777 bcmirq_handled(BCM43xx_IRQ_RX
);
1779 if (reason
& BCM43xx_IRQ_XMIT_STATUS
) {
1780 handle_irq_transmit_status(bcm
);
1782 //TODO: In AP mode, this also causes sending of powersave responses.
1783 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS
);
1786 /* We get spurious IRQs, althought they are masked.
1787 * Assume they are void and ignore them.
1789 bcmirq_handled(~(bcm
->irq_savedstate
));
1790 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1791 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND
);
1792 #ifdef CONFIG_BCM43XX_DEBUG
1793 if (unlikely(reason
& ~_handled
)) {
1794 printkl(KERN_WARNING PFX
1795 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1796 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1797 reason
, (reason
& ~_handled
),
1798 dma_reason
[0], dma_reason
[1],
1799 dma_reason
[2], dma_reason
[3]);
1802 #undef bcmirq_handled
1804 if (!modparam_noleds
)
1805 bcm43xx_leds_update(bcm
, activity
);
1806 bcm43xx_interrupt_enable(bcm
, bcm
->irq_savedstate
);
1807 bcm43xx_unlock_mmio(bcm
, flags
);
1810 static void bcm43xx_interrupt_ack(struct bcm43xx_private
*bcm
,
1811 u32 reason
, u32 mask
)
1813 bcm
->dma_reason
[0] = bcm43xx_read32(bcm
, BCM43xx_MMIO_DMA1_REASON
)
1815 bcm
->dma_reason
[1] = bcm43xx_read32(bcm
, BCM43xx_MMIO_DMA2_REASON
)
1817 bcm
->dma_reason
[2] = bcm43xx_read32(bcm
, BCM43xx_MMIO_DMA3_REASON
)
1819 bcm
->dma_reason
[3] = bcm43xx_read32(bcm
, BCM43xx_MMIO_DMA4_REASON
)
1822 if (bcm43xx_using_pio(bcm
) &&
1823 (bcm
->current_core
->rev
< 3) &&
1824 (!(reason
& BCM43xx_IRQ_PIO_WORKAROUND
))) {
1825 /* Apply a PIO specific workaround to the dma_reasons */
1827 #define apply_pio_workaround(BASE, QNUM) \
1829 if (bcm43xx_read16(bcm, BASE + BCM43xx_PIO_RXCTL) & BCM43xx_PIO_RXCTL_DATAAVAILABLE) \
1830 bcm->dma_reason[QNUM] |= 0x00010000; \
1832 bcm->dma_reason[QNUM] &= ~0x00010000; \
1835 apply_pio_workaround(BCM43xx_MMIO_PIO1_BASE
, 0);
1836 apply_pio_workaround(BCM43xx_MMIO_PIO2_BASE
, 1);
1837 apply_pio_workaround(BCM43xx_MMIO_PIO3_BASE
, 2);
1838 apply_pio_workaround(BCM43xx_MMIO_PIO4_BASE
, 3);
1840 #undef apply_pio_workaround
1843 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
,
1846 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA1_REASON
,
1847 bcm
->dma_reason
[0]);
1848 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA2_REASON
,
1849 bcm
->dma_reason
[1]);
1850 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA3_REASON
,
1851 bcm
->dma_reason
[2]);
1852 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA4_REASON
,
1853 bcm
->dma_reason
[3]);
1856 /* Interrupt handler top-half */
1857 static irqreturn_t
bcm43xx_interrupt_handler(int irq
, void *dev_id
, struct pt_regs
*regs
)
1859 irqreturn_t ret
= IRQ_HANDLED
;
1860 struct bcm43xx_private
*bcm
= dev_id
;
1866 spin_lock(&bcm
->_lock
);
1868 reason
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
);
1869 if (reason
== 0xffffffff) {
1870 /* irq not for us (shared irq) */
1874 mask
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_MASK
);
1875 if (!(reason
& mask
))
1878 bcm43xx_interrupt_ack(bcm
, reason
, mask
);
1880 /* Only accept IRQs, if we are initialized properly.
1881 * This avoids an RX race while initializing.
1882 * We should probably not enable IRQs before we are initialized
1883 * completely, but some careful work is needed to fix this. I think it
1884 * is best to stay with this cheap workaround for now... .
1886 if (likely(bcm
->initialized
)) {
1887 /* disable all IRQs. They are enabled again in the bottom half. */
1888 bcm
->irq_savedstate
= bcm43xx_interrupt_disable(bcm
, BCM43xx_IRQ_ALL
);
1889 /* save the reason code and call our bottom half. */
1890 bcm
->irq_reason
= reason
;
1891 tasklet_schedule(&bcm
->isr_tasklet
);
1896 spin_unlock(&bcm
->_lock
);
1901 static void bcm43xx_release_firmware(struct bcm43xx_private
*bcm
, int force
)
1903 if (bcm
->firmware_norelease
&& !force
)
1904 return; /* Suspending or controller reset. */
1905 release_firmware(bcm
->ucode
);
1907 release_firmware(bcm
->pcm
);
1909 release_firmware(bcm
->initvals0
);
1910 bcm
->initvals0
= NULL
;
1911 release_firmware(bcm
->initvals1
);
1912 bcm
->initvals1
= NULL
;
1915 static int bcm43xx_request_firmware(struct bcm43xx_private
*bcm
)
1917 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
1918 u8 rev
= bcm
->current_core
->rev
;
1921 char buf
[22 + sizeof(modparam_fwpostfix
) - 1] = { 0 };
1924 snprintf(buf
, ARRAY_SIZE(buf
), "bcm43xx_microcode%d%s.fw",
1925 (rev
>= 5 ? 5 : rev
),
1926 modparam_fwpostfix
);
1927 err
= request_firmware(&bcm
->ucode
, buf
, &bcm
->pci_dev
->dev
);
1930 "Error: Microcode \"%s\" not available or load failed.\n",
1937 snprintf(buf
, ARRAY_SIZE(buf
),
1938 "bcm43xx_pcm%d%s.fw",
1940 modparam_fwpostfix
);
1941 err
= request_firmware(&bcm
->pcm
, buf
, &bcm
->pci_dev
->dev
);
1944 "Error: PCM \"%s\" not available or load failed.\n",
1950 if (!bcm
->initvals0
) {
1951 if (rev
== 2 || rev
== 4) {
1952 switch (phy
->type
) {
1953 case BCM43xx_PHYTYPE_A
:
1956 case BCM43xx_PHYTYPE_B
:
1957 case BCM43xx_PHYTYPE_G
:
1964 } else if (rev
>= 5) {
1965 switch (phy
->type
) {
1966 case BCM43xx_PHYTYPE_A
:
1969 case BCM43xx_PHYTYPE_B
:
1970 case BCM43xx_PHYTYPE_G
:
1978 snprintf(buf
, ARRAY_SIZE(buf
), "bcm43xx_initval%02d%s.fw",
1979 nr
, modparam_fwpostfix
);
1981 err
= request_firmware(&bcm
->initvals0
, buf
, &bcm
->pci_dev
->dev
);
1984 "Error: InitVals \"%s\" not available or load failed.\n",
1988 if (bcm
->initvals0
->size
% sizeof(struct bcm43xx_initval
)) {
1989 printk(KERN_ERR PFX
"InitVals fileformat error.\n");
1994 if (!bcm
->initvals1
) {
1998 switch (phy
->type
) {
1999 case BCM43xx_PHYTYPE_A
:
2000 sbtmstatehigh
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATEHIGH
);
2001 if (sbtmstatehigh
& 0x00010000)
2006 case BCM43xx_PHYTYPE_B
:
2007 case BCM43xx_PHYTYPE_G
:
2013 snprintf(buf
, ARRAY_SIZE(buf
), "bcm43xx_initval%02d%s.fw",
2014 nr
, modparam_fwpostfix
);
2016 err
= request_firmware(&bcm
->initvals1
, buf
, &bcm
->pci_dev
->dev
);
2019 "Error: InitVals \"%s\" not available or load failed.\n",
2023 if (bcm
->initvals1
->size
% sizeof(struct bcm43xx_initval
)) {
2024 printk(KERN_ERR PFX
"InitVals fileformat error.\n");
2033 bcm43xx_release_firmware(bcm
, 1);
2036 printk(KERN_ERR PFX
"Error: No InitVals available!\n");
2041 static void bcm43xx_upload_microcode(struct bcm43xx_private
*bcm
)
2044 unsigned int i
, len
;
2046 /* Upload Microcode. */
2047 data
= (u32
*)(bcm
->ucode
->data
);
2048 len
= bcm
->ucode
->size
/ sizeof(u32
);
2049 bcm43xx_shm_control_word(bcm
, BCM43xx_SHM_UCODE
, 0x0000);
2050 for (i
= 0; i
< len
; i
++) {
2051 bcm43xx_write32(bcm
, BCM43xx_MMIO_SHM_DATA
,
2052 be32_to_cpu(data
[i
]));
2056 /* Upload PCM data. */
2057 data
= (u32
*)(bcm
->pcm
->data
);
2058 len
= bcm
->pcm
->size
/ sizeof(u32
);
2059 bcm43xx_shm_control_word(bcm
, BCM43xx_SHM_PCM
, 0x01ea);
2060 bcm43xx_write32(bcm
, BCM43xx_MMIO_SHM_DATA
, 0x00004000);
2061 bcm43xx_shm_control_word(bcm
, BCM43xx_SHM_PCM
, 0x01eb);
2062 for (i
= 0; i
< len
; i
++) {
2063 bcm43xx_write32(bcm
, BCM43xx_MMIO_SHM_DATA
,
2064 be32_to_cpu(data
[i
]));
2069 static int bcm43xx_write_initvals(struct bcm43xx_private
*bcm
,
2070 const struct bcm43xx_initval
*data
,
2071 const unsigned int len
)
2077 for (i
= 0; i
< len
; i
++) {
2078 offset
= be16_to_cpu(data
[i
].offset
);
2079 size
= be16_to_cpu(data
[i
].size
);
2080 value
= be32_to_cpu(data
[i
].value
);
2082 if (unlikely(offset
>= 0x1000))
2085 if (unlikely(value
& 0xFFFF0000))
2087 bcm43xx_write16(bcm
, offset
, (u16
)value
);
2088 } else if (size
== 4) {
2089 bcm43xx_write32(bcm
, offset
, value
);
2097 printk(KERN_ERR PFX
"InitVals (bcm43xx_initvalXX.fw) file-format error. "
2098 "Please fix your bcm43xx firmware files.\n");
2102 static int bcm43xx_upload_initvals(struct bcm43xx_private
*bcm
)
2106 err
= bcm43xx_write_initvals(bcm
, (struct bcm43xx_initval
*)bcm
->initvals0
->data
,
2107 bcm
->initvals0
->size
/ sizeof(struct bcm43xx_initval
));
2110 if (bcm
->initvals1
) {
2111 err
= bcm43xx_write_initvals(bcm
, (struct bcm43xx_initval
*)bcm
->initvals1
->data
,
2112 bcm
->initvals1
->size
/ sizeof(struct bcm43xx_initval
));
2120 static int bcm43xx_initialize_irq(struct bcm43xx_private
*bcm
)
2126 bcm
->irq
= bcm
->pci_dev
->irq
;
2127 #ifdef CONFIG_BCM947XX
2128 if (bcm
->pci_dev
->bus
->number
== 0) {
2129 struct pci_dev
*d
= NULL
;
2130 /* FIXME: we will probably need more device IDs here... */
2131 d
= pci_find_device(PCI_VENDOR_ID_BROADCOM
, 0x4324, NULL
);
2137 res
= request_irq(bcm
->irq
, bcm43xx_interrupt_handler
,
2138 SA_SHIRQ
, KBUILD_MODNAME
, bcm
);
2140 printk(KERN_ERR PFX
"Cannot register IRQ%d\n", bcm
->irq
);
2143 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
, 0xffffffff);
2144 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, 0x00020402);
2147 data
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
);
2148 if (data
== BCM43xx_IRQ_READY
)
2151 if (i
>= BCM43xx_IRQWAIT_MAX_RETRIES
) {
2152 printk(KERN_ERR PFX
"Card IRQ register not responding. "
2154 free_irq(bcm
->irq
, bcm
);
2160 bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
);
2165 /* Switch to the core used to write the GPIO register.
2166 * This is either the ChipCommon, or the PCI core.
2168 static int switch_to_gpio_core(struct bcm43xx_private
*bcm
)
2172 /* Where to find the GPIO register depends on the chipset.
2173 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2174 * control register. Otherwise the register at offset 0x6c in the
2175 * PCI core is the GPIO control register.
2177 err
= bcm43xx_switch_core(bcm
, &bcm
->core_chipcommon
);
2178 if (err
== -ENODEV
) {
2179 err
= bcm43xx_switch_core(bcm
, &bcm
->core_pci
);
2180 if (unlikely(err
== -ENODEV
)) {
2181 printk(KERN_ERR PFX
"gpio error: "
2182 "Neither ChipCommon nor PCI core available!\n");
2184 } else if (unlikely(err
!= 0))
2186 } else if (unlikely(err
!= 0))
2192 /* Initialize the GPIOs
2193 * http://bcm-specs.sipsolutions.net/GPIO
2195 static int bcm43xx_gpio_init(struct bcm43xx_private
*bcm
)
2197 struct bcm43xx_coreinfo
*old_core
;
2201 value
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2203 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, value
);
2207 bcm43xx_write16(bcm
, BCM43xx_MMIO_GPIO_CONTROL
,
2208 bcm43xx_read16(bcm
, BCM43xx_MMIO_GPIO_CONTROL
) & 0xFFF0);
2209 bcm43xx_write16(bcm
, BCM43xx_MMIO_GPIO_MASK
,
2210 bcm43xx_read16(bcm
, BCM43xx_MMIO_GPIO_MASK
) | 0x000F);
2212 old_core
= bcm
->current_core
;
2214 err
= switch_to_gpio_core(bcm
);
2218 if (bcm
->current_core
->rev
>= 2){
2222 if (bcm
->chip_id
== 0x4301) {
2226 if (bcm
->sprom
.boardflags
& BCM43xx_BFL_PACTRL
) {
2231 bcm43xx_write32(bcm
, BCM43xx_GPIO_CONTROL
,
2232 (bcm43xx_read32(bcm
, BCM43xx_GPIO_CONTROL
) & mask
) | value
);
2234 err
= bcm43xx_switch_core(bcm
, old_core
);
2240 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2241 static int bcm43xx_gpio_cleanup(struct bcm43xx_private
*bcm
)
2243 struct bcm43xx_coreinfo
*old_core
;
2246 old_core
= bcm
->current_core
;
2247 err
= switch_to_gpio_core(bcm
);
2250 bcm43xx_write32(bcm
, BCM43xx_GPIO_CONTROL
, 0x00000000);
2251 err
= bcm43xx_switch_core(bcm
, old_core
);
2257 /* http://bcm-specs.sipsolutions.net/EnableMac */
2258 void bcm43xx_mac_enable(struct bcm43xx_private
*bcm
)
2260 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
,
2261 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
)
2262 | BCM43xx_SBF_MAC_ENABLED
);
2263 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
, BCM43xx_IRQ_READY
);
2264 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
); /* dummy read */
2265 bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
); /* dummy read */
2266 bcm43xx_power_saving_ctl_bits(bcm
, -1, -1);
2269 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2270 void bcm43xx_mac_suspend(struct bcm43xx_private
*bcm
)
2275 bcm43xx_power_saving_ctl_bits(bcm
, -1, 1);
2276 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
,
2277 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
)
2278 & ~BCM43xx_SBF_MAC_ENABLED
);
2279 bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
); /* dummy read */
2280 for (i
= 100000; i
; i
--) {
2281 tmp
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
);
2282 if (tmp
& BCM43xx_IRQ_READY
)
2286 printkl(KERN_ERR PFX
"MAC suspend failed\n");
2289 void bcm43xx_set_iwmode(struct bcm43xx_private
*bcm
,
2292 unsigned long flags
;
2295 spin_lock_irqsave(&bcm
->ieee
->lock
, flags
);
2296 bcm
->ieee
->iw_mode
= iw_mode
;
2297 spin_unlock_irqrestore(&bcm
->ieee
->lock
, flags
);
2298 if (iw_mode
== IW_MODE_MONITOR
)
2299 bcm
->net_dev
->type
= ARPHRD_IEEE80211
;
2301 bcm
->net_dev
->type
= ARPHRD_ETHER
;
2303 if (!bcm
->initialized
)
2306 bcm43xx_mac_suspend(bcm
);
2307 status
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2308 /* Reset status to infrastructured mode */
2309 status
&= ~(BCM43xx_SBF_MODE_AP
| BCM43xx_SBF_MODE_MONITOR
);
2310 /*FIXME: We actually set promiscuous mode as well, until we don't
2311 * get the HW mac filter working */
2312 status
|= BCM43xx_SBF_MODE_NOTADHOC
| BCM43xx_SBF_MODE_PROMISC
;
2315 case IW_MODE_MONITOR
:
2316 status
|= (BCM43xx_SBF_MODE_PROMISC
|
2317 BCM43xx_SBF_MODE_MONITOR
);
2320 status
&= ~BCM43xx_SBF_MODE_NOTADHOC
;
2322 case IW_MODE_MASTER
:
2323 case IW_MODE_SECOND
:
2324 case IW_MODE_REPEAT
:
2325 /* TODO: No AP/Repeater mode for now :-/ */
2329 /* nothing to be done here... */
2332 printk(KERN_ERR PFX
"Unknown iwmode %d\n", iw_mode
);
2335 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
2336 bcm43xx_mac_enable(bcm
);
2339 /* This is the opposite of bcm43xx_chip_init() */
2340 static void bcm43xx_chip_cleanup(struct bcm43xx_private
*bcm
)
2342 bcm43xx_radio_turn_off(bcm
);
2343 if (!modparam_noleds
)
2344 bcm43xx_leds_exit(bcm
);
2345 bcm43xx_gpio_cleanup(bcm
);
2346 free_irq(bcm
->irq
, bcm
);
2347 bcm43xx_release_firmware(bcm
, 0);
2350 /* Initialize the chip
2351 * http://bcm-specs.sipsolutions.net/ChipInit
2353 static int bcm43xx_chip_init(struct bcm43xx_private
*bcm
)
2355 struct bcm43xx_radioinfo
*radio
= bcm43xx_current_radio(bcm
);
2356 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
2358 int iw_mode
= bcm
->ieee
->iw_mode
;
2363 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
,
2364 BCM43xx_SBF_CORE_READY
2367 err
= bcm43xx_request_firmware(bcm
);
2370 bcm43xx_upload_microcode(bcm
);
2372 err
= bcm43xx_initialize_irq(bcm
);
2374 goto err_release_fw
;
2376 err
= bcm43xx_gpio_init(bcm
);
2380 err
= bcm43xx_upload_initvals(bcm
);
2382 goto err_gpio_cleanup
;
2383 bcm43xx_radio_turn_on(bcm
);
2385 if (modparam_noleds
)
2386 bcm43xx_leds_turn_off(bcm
);
2388 bcm43xx_leds_update(bcm
, 0);
2390 bcm43xx_write16(bcm
, 0x03E6, 0x0000);
2391 err
= bcm43xx_phy_init(bcm
);
2395 /* Select initial Interference Mitigation. */
2396 tmp
= radio
->interfmode
;
2397 radio
->interfmode
= BCM43xx_RADIO_INTERFMODE_NONE
;
2398 bcm43xx_radio_set_interference_mitigation(bcm
, tmp
);
2400 bcm43xx_phy_set_antenna_diversity(bcm
);
2401 bcm43xx_radio_set_txantenna(bcm
, BCM43xx_RADIO_TXANTENNA_DEFAULT
);
2402 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
2403 value16
= bcm43xx_read16(bcm
, 0x005E);
2405 bcm43xx_write16(bcm
, 0x005E, value16
);
2407 bcm43xx_write32(bcm
, 0x0100, 0x01000000);
2408 if (bcm
->current_core
->rev
< 5)
2409 bcm43xx_write32(bcm
, 0x010C, 0x01000000);
2411 value32
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2412 value32
&= ~ BCM43xx_SBF_MODE_NOTADHOC
;
2413 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2414 value32
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2415 value32
|= BCM43xx_SBF_MODE_NOTADHOC
;
2416 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2417 /*FIXME: For now, use promiscuous mode at all times; otherwise we don't
2418 get broadcast or multicast packets */
2419 value32
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2420 value32
|= BCM43xx_SBF_MODE_PROMISC
;
2421 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2423 if (iw_mode
== IW_MODE_MONITOR
) {
2424 value32
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2425 value32
|= BCM43xx_SBF_MODE_PROMISC
;
2426 value32
|= BCM43xx_SBF_MODE_MONITOR
;
2427 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2429 value32
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2430 value32
|= 0x100000; //FIXME: What's this? Is this correct?
2431 bcm43xx_write32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2433 if (bcm43xx_using_pio(bcm
)) {
2434 bcm43xx_write32(bcm
, 0x0210, 0x00000100);
2435 bcm43xx_write32(bcm
, 0x0230, 0x00000100);
2436 bcm43xx_write32(bcm
, 0x0250, 0x00000100);
2437 bcm43xx_write32(bcm
, 0x0270, 0x00000100);
2438 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0034, 0x0000);
2441 /* Probe Response Timeout value */
2442 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2443 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0074, 0x0000);
2445 if (iw_mode
!= IW_MODE_ADHOC
&& iw_mode
!= IW_MODE_MASTER
) {
2446 if ((bcm
->chip_id
== 0x4306) && (bcm
->chip_rev
== 3))
2447 bcm43xx_write16(bcm
, 0x0612, 0x0064);
2449 bcm43xx_write16(bcm
, 0x0612, 0x0032);
2451 bcm43xx_write16(bcm
, 0x0612, 0x0002);
2453 if (bcm
->current_core
->rev
< 3) {
2454 bcm43xx_write16(bcm
, 0x060E, 0x0000);
2455 bcm43xx_write16(bcm
, 0x0610, 0x8000);
2456 bcm43xx_write16(bcm
, 0x0604, 0x0000);
2457 bcm43xx_write16(bcm
, 0x0606, 0x0200);
2459 bcm43xx_write32(bcm
, 0x0188, 0x80000000);
2460 bcm43xx_write32(bcm
, 0x018C, 0x02000000);
2462 bcm43xx_write32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
, 0x00004000);
2463 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA1_IRQ_MASK
, 0x0001DC00);
2464 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2465 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA3_IRQ_MASK
, 0x0000DC00);
2466 bcm43xx_write32(bcm
, BCM43xx_MMIO_DMA4_IRQ_MASK
, 0x0001DC00);
2468 value32
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTMSTATELOW
);
2469 value32
|= 0x00100000;
2470 bcm43xx_write32(bcm
, BCM43xx_CIR_SBTMSTATELOW
, value32
);
2472 bcm43xx_write16(bcm
, BCM43xx_MMIO_POWERUP_DELAY
, bcm43xx_pctl_powerup_delay(bcm
));
2475 dprintk(KERN_INFO PFX
"Chip initialized\n");
2480 bcm43xx_radio_turn_off(bcm
);
2482 bcm43xx_gpio_cleanup(bcm
);
2484 free_irq(bcm
->irq
, bcm
);
2486 bcm43xx_release_firmware(bcm
, 1);
2490 /* Validate chip access
2491 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2492 static int bcm43xx_validate_chip(struct bcm43xx_private
*bcm
)
2497 shm_backup
= bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
, 0x0000);
2498 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_SHARED
, 0x0000, 0xAA5555AA);
2499 if (bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
, 0x0000) != 0xAA5555AA)
2501 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_SHARED
, 0x0000, 0x55AAAA55);
2502 if (bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
, 0x0000) != 0x55AAAA55)
2504 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_SHARED
, 0x0000, shm_backup
);
2506 value
= bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
);
2507 if ((value
| 0x80000000) != 0x80000400)
2510 value
= bcm43xx_read32(bcm
, BCM43xx_MMIO_GEN_IRQ_REASON
);
2511 if (value
!= 0x00000000)
2516 printk(KERN_ERR PFX
"Failed to validate the chipaccess\n");
2520 void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo
*phy
)
2522 /* Initialize a "phyinfo" structure. The structure is already
2525 phy
->antenna_diversity
= 0xFFFF;
2526 phy
->savedpctlreg
= 0xFFFF;
2527 phy
->minlowsig
[0] = 0xFFFF;
2528 phy
->minlowsig
[1] = 0xFFFF;
2529 spin_lock_init(&phy
->lock
);
2532 void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo
*radio
)
2534 /* Initialize a "radioinfo" structure. The structure is already
2537 radio
->interfmode
= BCM43xx_RADIO_INTERFMODE_NONE
;
2538 radio
->channel
= 0xFF;
2539 radio
->initial_channel
= 0xFF;
2540 radio
->lofcal
= 0xFFFF;
2541 radio
->initval
= 0xFFFF;
2542 radio
->nrssi
[0] = -1000;
2543 radio
->nrssi
[1] = -1000;
2546 static int bcm43xx_probe_cores(struct bcm43xx_private
*bcm
)
2550 u32 core_vendor
, core_id
, core_rev
;
2551 u32 sb_id_hi
, chip_id_32
= 0;
2552 u16 pci_device
, chip_id_16
;
2555 memset(&bcm
->core_chipcommon
, 0, sizeof(struct bcm43xx_coreinfo
));
2556 memset(&bcm
->core_pci
, 0, sizeof(struct bcm43xx_coreinfo
));
2557 memset(&bcm
->core_80211
, 0, sizeof(struct bcm43xx_coreinfo
)
2558 * BCM43xx_MAX_80211_CORES
);
2559 memset(&bcm
->core_80211_ext
, 0, sizeof(struct bcm43xx_coreinfo_80211
)
2560 * BCM43xx_MAX_80211_CORES
);
2561 bcm
->current_80211_core_idx
= -1;
2562 bcm
->nr_80211_available
= 0;
2563 bcm
->current_core
= NULL
;
2564 bcm
->active_80211_core
= NULL
;
2567 err
= _switch_core(bcm
, 0);
2571 /* fetch sb_id_hi from core information registers */
2572 sb_id_hi
= bcm43xx_read32(bcm
, BCM43xx_CIR_SB_ID_HI
);
2574 core_id
= (sb_id_hi
& 0xFFF0) >> 4;
2575 core_rev
= (sb_id_hi
& 0xF);
2576 core_vendor
= (sb_id_hi
& 0xFFFF0000) >> 16;
2578 /* if present, chipcommon is always core 0; read the chipid from it */
2579 if (core_id
== BCM43xx_COREID_CHIPCOMMON
) {
2580 chip_id_32
= bcm43xx_read32(bcm
, 0);
2581 chip_id_16
= chip_id_32
& 0xFFFF;
2582 bcm
->core_chipcommon
.available
= 1;
2583 bcm
->core_chipcommon
.id
= core_id
;
2584 bcm
->core_chipcommon
.rev
= core_rev
;
2585 bcm
->core_chipcommon
.index
= 0;
2586 /* While we are at it, also read the capabilities. */
2587 bcm
->chipcommon_capabilities
= bcm43xx_read32(bcm
, BCM43xx_CHIPCOMMON_CAPABILITIES
);
2589 /* without a chipCommon, use a hard coded table. */
2590 pci_device
= bcm
->pci_dev
->device
;
2591 if (pci_device
== 0x4301)
2592 chip_id_16
= 0x4301;
2593 else if ((pci_device
>= 0x4305) && (pci_device
<= 0x4307))
2594 chip_id_16
= 0x4307;
2595 else if ((pci_device
>= 0x4402) && (pci_device
<= 0x4403))
2596 chip_id_16
= 0x4402;
2597 else if ((pci_device
>= 0x4610) && (pci_device
<= 0x4615))
2598 chip_id_16
= 0x4610;
2599 else if ((pci_device
>= 0x4710) && (pci_device
<= 0x4715))
2600 chip_id_16
= 0x4710;
2601 #ifdef CONFIG_BCM947XX
2602 else if ((pci_device
>= 0x4320) && (pci_device
<= 0x4325))
2603 chip_id_16
= 0x4309;
2606 printk(KERN_ERR PFX
"Could not determine Chip ID\n");
2611 /* ChipCommon with Core Rev >=4 encodes number of cores,
2612 * otherwise consult hardcoded table */
2613 if ((core_id
== BCM43xx_COREID_CHIPCOMMON
) && (core_rev
>= 4)) {
2614 core_count
= (chip_id_32
& 0x0F000000) >> 24;
2616 switch (chip_id_16
) {
2639 /* SOL if we get here */
2645 bcm
->chip_id
= chip_id_16
;
2646 bcm
->chip_rev
= (chip_id_32
& 0x000f0000) >> 16;
2648 dprintk(KERN_INFO PFX
"Chip ID 0x%x, rev 0x%x\n",
2649 bcm
->chip_id
, bcm
->chip_rev
);
2650 dprintk(KERN_INFO PFX
"Number of cores: %d\n", core_count
);
2651 if (bcm
->core_chipcommon
.available
) {
2652 dprintk(KERN_INFO PFX
"Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2653 core_id
, core_rev
, core_vendor
,
2654 bcm43xx_core_enabled(bcm
) ? "enabled" : "disabled");
2657 if (bcm
->core_chipcommon
.available
)
2661 for ( ; current_core
< core_count
; current_core
++) {
2662 struct bcm43xx_coreinfo
*core
;
2663 struct bcm43xx_coreinfo_80211
*ext_80211
;
2665 err
= _switch_core(bcm
, current_core
);
2668 /* Gather information */
2669 /* fetch sb_id_hi from core information registers */
2670 sb_id_hi
= bcm43xx_read32(bcm
, BCM43xx_CIR_SB_ID_HI
);
2672 /* extract core_id, core_rev, core_vendor */
2673 core_id
= (sb_id_hi
& 0xFFF0) >> 4;
2674 core_rev
= (sb_id_hi
& 0xF);
2675 core_vendor
= (sb_id_hi
& 0xFFFF0000) >> 16;
2677 dprintk(KERN_INFO PFX
"Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2678 current_core
, core_id
, core_rev
, core_vendor
,
2679 bcm43xx_core_enabled(bcm
) ? "enabled" : "disabled" );
2683 case BCM43xx_COREID_PCI
:
2684 core
= &bcm
->core_pci
;
2685 if (core
->available
) {
2686 printk(KERN_WARNING PFX
"Multiple PCI cores found.\n");
2690 case BCM43xx_COREID_80211
:
2691 for (i
= 0; i
< BCM43xx_MAX_80211_CORES
; i
++) {
2692 core
= &(bcm
->core_80211
[i
]);
2693 ext_80211
= &(bcm
->core_80211_ext
[i
]);
2694 if (!core
->available
)
2699 printk(KERN_WARNING PFX
"More than %d cores of type 802.11 found.\n",
2700 BCM43xx_MAX_80211_CORES
);
2704 /* More than one 80211 core is only supported
2706 * There are chips with two 80211 cores, but with
2707 * dangling pins on the second core. Be careful
2708 * and ignore these cores here.
2710 if (bcm
->pci_dev
->device
!= 0x4324) {
2711 dprintk(KERN_INFO PFX
"Ignoring additional 802.11 core.\n");
2724 printk(KERN_ERR PFX
"Error: Unsupported 80211 core revision %u\n",
2729 bcm
->nr_80211_available
++;
2730 bcm43xx_init_struct_phyinfo(&ext_80211
->phy
);
2731 bcm43xx_init_struct_radioinfo(&ext_80211
->radio
);
2733 case BCM43xx_COREID_CHIPCOMMON
:
2734 printk(KERN_WARNING PFX
"Multiple CHIPCOMMON cores found.\n");
2738 core
->available
= 1;
2740 core
->rev
= core_rev
;
2741 core
->index
= current_core
;
2745 if (!bcm
->core_80211
[0].available
) {
2746 printk(KERN_ERR PFX
"Error: No 80211 core found!\n");
2751 err
= bcm43xx_switch_core(bcm
, &bcm
->core_80211
[0]);
2758 static void bcm43xx_gen_bssid(struct bcm43xx_private
*bcm
)
2760 const u8
*mac
= (const u8
*)(bcm
->net_dev
->dev_addr
);
2761 u8
*bssid
= bcm
->ieee
->bssid
;
2763 switch (bcm
->ieee
->iw_mode
) {
2765 random_ether_addr(bssid
);
2767 case IW_MODE_MASTER
:
2769 case IW_MODE_REPEAT
:
2770 case IW_MODE_SECOND
:
2771 case IW_MODE_MONITOR
:
2772 memcpy(bssid
, mac
, ETH_ALEN
);
2779 static void bcm43xx_rate_memory_write(struct bcm43xx_private
*bcm
,
2787 offset
+= (bcm43xx_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2791 offset
+= (bcm43xx_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2793 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, offset
+ 0x20,
2794 bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
, offset
));
2797 static void bcm43xx_rate_memory_init(struct bcm43xx_private
*bcm
)
2799 switch (bcm43xx_current_phy(bcm
)->type
) {
2800 case BCM43xx_PHYTYPE_A
:
2801 case BCM43xx_PHYTYPE_G
:
2802 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_6MB
, 1);
2803 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_12MB
, 1);
2804 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_18MB
, 1);
2805 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_24MB
, 1);
2806 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_36MB
, 1);
2807 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_48MB
, 1);
2808 bcm43xx_rate_memory_write(bcm
, IEEE80211_OFDM_RATE_54MB
, 1);
2809 case BCM43xx_PHYTYPE_B
:
2810 bcm43xx_rate_memory_write(bcm
, IEEE80211_CCK_RATE_1MB
, 0);
2811 bcm43xx_rate_memory_write(bcm
, IEEE80211_CCK_RATE_2MB
, 0);
2812 bcm43xx_rate_memory_write(bcm
, IEEE80211_CCK_RATE_5MB
, 0);
2813 bcm43xx_rate_memory_write(bcm
, IEEE80211_CCK_RATE_11MB
, 0);
2820 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private
*bcm
)
2822 bcm43xx_chip_cleanup(bcm
);
2823 bcm43xx_pio_free(bcm
);
2824 bcm43xx_dma_free(bcm
);
2826 bcm
->current_core
->initialized
= 0;
2829 /* http://bcm-specs.sipsolutions.net/80211Init */
2830 static int bcm43xx_wireless_core_init(struct bcm43xx_private
*bcm
)
2832 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
2833 struct bcm43xx_radioinfo
*radio
= bcm43xx_current_radio(bcm
);
2839 if (bcm
->chip_rev
< 5) {
2840 sbimconfiglow
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBIMCONFIGLOW
);
2841 sbimconfiglow
&= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK
;
2842 sbimconfiglow
&= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK
;
2843 if (bcm
->bustype
== BCM43xx_BUSTYPE_PCI
)
2844 sbimconfiglow
|= 0x32;
2845 else if (bcm
->bustype
== BCM43xx_BUSTYPE_SB
)
2846 sbimconfiglow
|= 0x53;
2849 bcm43xx_write32(bcm
, BCM43xx_CIR_SBIMCONFIGLOW
, sbimconfiglow
);
2852 bcm43xx_phy_calibrate(bcm
);
2853 err
= bcm43xx_chip_init(bcm
);
2857 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0016, bcm
->current_core
->rev
);
2858 ucodeflags
= bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
, BCM43xx_UCODEFLAGS_OFFSET
);
2860 if (0 /*FIXME: which condition has to be used here? */)
2861 ucodeflags
|= 0x00000010;
2863 /* HW decryption needs to be set now */
2864 ucodeflags
|= 0x40000000;
2866 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
2867 ucodeflags
|= BCM43xx_UCODEFLAG_UNKBGPHY
;
2869 ucodeflags
|= BCM43xx_UCODEFLAG_UNKGPHY
;
2870 if (bcm
->sprom
.boardflags
& BCM43xx_BFL_PACTRL
)
2871 ucodeflags
|= BCM43xx_UCODEFLAG_UNKPACTRL
;
2872 } else if (phy
->type
== BCM43xx_PHYTYPE_B
) {
2873 ucodeflags
|= BCM43xx_UCODEFLAG_UNKBGPHY
;
2874 if (phy
->rev
>= 2 && radio
->version
== 0x2050)
2875 ucodeflags
&= ~BCM43xx_UCODEFLAG_UNKGPHY
;
2878 if (ucodeflags
!= bcm43xx_shm_read32(bcm
, BCM43xx_SHM_SHARED
,
2879 BCM43xx_UCODEFLAGS_OFFSET
)) {
2880 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_SHARED
,
2881 BCM43xx_UCODEFLAGS_OFFSET
, ucodeflags
);
2884 /* Short/Long Retry Limit.
2885 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2886 * the chip-internal counter.
2888 limit
= limit_value(modparam_short_retry
, 0, 0xF);
2889 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_WIRELESS
, 0x0006, limit
);
2890 limit
= limit_value(modparam_long_retry
, 0, 0xF);
2891 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_WIRELESS
, 0x0007, limit
);
2893 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0044, 3);
2894 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0046, 2);
2896 bcm43xx_rate_memory_init(bcm
);
2898 /* Minimum Contention Window */
2899 if (phy
->type
== BCM43xx_PHYTYPE_B
)
2900 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_WIRELESS
, 0x0003, 0x0000001f);
2902 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_WIRELESS
, 0x0003, 0x0000000f);
2903 /* Maximum Contention Window */
2904 bcm43xx_shm_write32(bcm
, BCM43xx_SHM_WIRELESS
, 0x0004, 0x000003ff);
2906 bcm43xx_gen_bssid(bcm
);
2907 bcm43xx_write_mac_bssid_templates(bcm
);
2909 if (bcm
->current_core
->rev
>= 5)
2910 bcm43xx_write16(bcm
, 0x043C, 0x000C);
2912 if (bcm43xx_using_pio(bcm
))
2913 err
= bcm43xx_pio_init(bcm
);
2915 err
= bcm43xx_dma_init(bcm
);
2917 goto err_chip_cleanup
;
2918 bcm43xx_write16(bcm
, 0x0612, 0x0050);
2919 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0416, 0x0050);
2920 bcm43xx_shm_write16(bcm
, BCM43xx_SHM_SHARED
, 0x0414, 0x01F4);
2922 bcm43xx_mac_enable(bcm
);
2923 bcm43xx_interrupt_enable(bcm
, bcm
->irq_savedstate
);
2925 bcm
->current_core
->initialized
= 1;
2930 bcm43xx_chip_cleanup(bcm
);
2934 static int bcm43xx_chipset_attach(struct bcm43xx_private
*bcm
)
2939 err
= bcm43xx_pctl_set_crystal(bcm
, 1);
2942 bcm43xx_pci_read_config16(bcm
, PCI_STATUS
, &pci_status
);
2943 bcm43xx_pci_write_config16(bcm
, PCI_STATUS
, pci_status
& ~PCI_STATUS_SIG_TARGET_ABORT
);
2949 static void bcm43xx_chipset_detach(struct bcm43xx_private
*bcm
)
2951 bcm43xx_pctl_set_clock(bcm
, BCM43xx_PCTL_CLK_SLOW
);
2952 bcm43xx_pctl_set_crystal(bcm
, 0);
2955 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private
*bcm
,
2959 bcm43xx_write32(bcm
, BCM43xx_PCICORE_BCAST_ADDR
, address
);
2960 bcm43xx_write32(bcm
, BCM43xx_PCICORE_BCAST_DATA
, data
);
2963 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private
*bcm
)
2966 struct bcm43xx_coreinfo
*old_core
;
2968 old_core
= bcm
->current_core
;
2969 err
= bcm43xx_switch_core(bcm
, &bcm
->core_pci
);
2973 bcm43xx_pcicore_broadcast_value(bcm
, 0xfd8, 0x00000000);
2975 bcm43xx_switch_core(bcm
, old_core
);
2981 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2982 * To enable core 0, pass a core_mask of 1<<0
2984 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private
*bcm
,
2987 u32 backplane_flag_nr
;
2989 struct bcm43xx_coreinfo
*old_core
;
2992 value
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBTPSFLAG
);
2993 backplane_flag_nr
= value
& BCM43xx_BACKPLANE_FLAG_NR_MASK
;
2995 old_core
= bcm
->current_core
;
2996 err
= bcm43xx_switch_core(bcm
, &bcm
->core_pci
);
3000 if (bcm
->core_pci
.rev
< 6) {
3001 value
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBINTVEC
);
3002 value
|= (1 << backplane_flag_nr
);
3003 bcm43xx_write32(bcm
, BCM43xx_CIR_SBINTVEC
, value
);
3005 err
= bcm43xx_pci_read_config32(bcm
, BCM43xx_PCICFG_ICR
, &value
);
3007 printk(KERN_ERR PFX
"Error: ICR setup failure!\n");
3008 goto out_switch_back
;
3010 value
|= core_mask
<< 8;
3011 err
= bcm43xx_pci_write_config32(bcm
, BCM43xx_PCICFG_ICR
, value
);
3013 printk(KERN_ERR PFX
"Error: ICR setup failure!\n");
3014 goto out_switch_back
;
3018 value
= bcm43xx_read32(bcm
, BCM43xx_PCICORE_SBTOPCI2
);
3019 value
|= BCM43xx_SBTOPCI2_PREFETCH
| BCM43xx_SBTOPCI2_BURST
;
3020 bcm43xx_write32(bcm
, BCM43xx_PCICORE_SBTOPCI2
, value
);
3022 if (bcm
->core_pci
.rev
< 5) {
3023 value
= bcm43xx_read32(bcm
, BCM43xx_CIR_SBIMCONFIGLOW
);
3024 value
|= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT
)
3025 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK
;
3026 value
|= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT
)
3027 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK
;
3028 bcm43xx_write32(bcm
, BCM43xx_CIR_SBIMCONFIGLOW
, value
);
3029 err
= bcm43xx_pcicore_commit_settings(bcm
);
3034 err
= bcm43xx_switch_core(bcm
, old_core
);
3039 static void bcm43xx_softmac_init(struct bcm43xx_private
*bcm
)
3041 ieee80211softmac_start(bcm
->net_dev
);
3044 static void bcm43xx_periodic_every120sec(struct bcm43xx_private
*bcm
)
3046 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
3048 if (phy
->type
!= BCM43xx_PHYTYPE_G
|| phy
->rev
< 2)
3051 bcm43xx_mac_suspend(bcm
);
3052 bcm43xx_phy_lo_g_measure(bcm
);
3053 bcm43xx_mac_enable(bcm
);
3056 static void bcm43xx_periodic_every60sec(struct bcm43xx_private
*bcm
)
3058 bcm43xx_phy_lo_mark_all_unused(bcm
);
3059 if (bcm
->sprom
.boardflags
& BCM43xx_BFL_RSSI
) {
3060 bcm43xx_mac_suspend(bcm
);
3061 bcm43xx_calc_nrssi_slope(bcm
);
3062 bcm43xx_mac_enable(bcm
);
3066 static void bcm43xx_periodic_every30sec(struct bcm43xx_private
*bcm
)
3068 /* Update device statistics. */
3069 bcm43xx_calculate_link_quality(bcm
);
3072 static void bcm43xx_periodic_every15sec(struct bcm43xx_private
*bcm
)
3074 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
3075 struct bcm43xx_radioinfo
*radio
= bcm43xx_current_radio(bcm
);
3077 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
3078 //TODO: update_aci_moving_average
3079 if (radio
->aci_enable
&& radio
->aci_wlan_automatic
) {
3080 bcm43xx_mac_suspend(bcm
);
3081 if (!radio
->aci_enable
&& 1 /*TODO: not scanning? */) {
3082 if (0 /*TODO: bunch of conditions*/) {
3083 bcm43xx_radio_set_interference_mitigation(bcm
,
3084 BCM43xx_RADIO_INTERFMODE_MANUALWLAN
);
3086 } else if (1/*TODO*/) {
3088 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3089 bcm43xx_radio_set_interference_mitigation(bcm,
3090 BCM43xx_RADIO_INTERFMODE_NONE);
3094 bcm43xx_mac_enable(bcm
);
3095 } else if (radio
->interfmode
== BCM43xx_RADIO_INTERFMODE_NONWLAN
&&
3097 //TODO: implement rev1 workaround
3100 bcm43xx_phy_xmitpower(bcm
); //FIXME: unless scanning?
3101 //TODO for APHY (temperature?)
3104 static void bcm43xx_periodic_task_handler(unsigned long d
)
3106 struct bcm43xx_private
*bcm
= (struct bcm43xx_private
*)d
;
3107 unsigned long flags
;
3110 bcm43xx_lock_mmio(bcm
, flags
);
3112 assert(bcm
->initialized
);
3113 state
= bcm
->periodic_state
;
3115 bcm43xx_periodic_every120sec(bcm
);
3117 bcm43xx_periodic_every60sec(bcm
);
3119 bcm43xx_periodic_every30sec(bcm
);
3120 bcm43xx_periodic_every15sec(bcm
);
3121 bcm
->periodic_state
= state
+ 1;
3123 mod_timer(&bcm
->periodic_tasks
, jiffies
+ (HZ
* 15));
3125 bcm43xx_unlock_mmio(bcm
, flags
);
3128 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private
*bcm
)
3130 del_timer_sync(&bcm
->periodic_tasks
);
3133 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private
*bcm
)
3135 struct timer_list
*timer
= &(bcm
->periodic_tasks
);
3137 assert(bcm
->initialized
);
3139 bcm43xx_periodic_task_handler
,
3140 (unsigned long)bcm
);
3141 timer
->expires
= jiffies
;
3145 static void bcm43xx_security_init(struct bcm43xx_private
*bcm
)
3147 bcm
->security_offset
= bcm43xx_shm_read16(bcm
, BCM43xx_SHM_SHARED
,
3149 bcm43xx_clear_keys(bcm
);
3152 /* This is the opposite of bcm43xx_init_board() */
3153 static void bcm43xx_free_board(struct bcm43xx_private
*bcm
)
3156 unsigned long flags
;
3158 bcm43xx_sysfs_unregister(bcm
);
3160 bcm43xx_periodic_tasks_delete(bcm
);
3162 bcm43xx_lock(bcm
, flags
);
3163 bcm
->initialized
= 0;
3164 bcm
->shutting_down
= 1;
3165 bcm43xx_unlock(bcm
, flags
);
3167 for (i
= 0; i
< BCM43xx_MAX_80211_CORES
; i
++) {
3168 if (!bcm
->core_80211
[i
].available
)
3170 if (!bcm
->core_80211
[i
].initialized
)
3173 err
= bcm43xx_switch_core(bcm
, &bcm
->core_80211
[i
]);
3175 bcm43xx_wireless_core_cleanup(bcm
);
3178 bcm43xx_pctl_set_crystal(bcm
, 0);
3180 bcm43xx_lock(bcm
, flags
);
3181 bcm
->shutting_down
= 0;
3182 bcm43xx_unlock(bcm
, flags
);
3185 static int bcm43xx_init_board(struct bcm43xx_private
*bcm
)
3189 unsigned long flags
;
3193 bcm43xx_lock(bcm
, flags
);
3194 bcm
->initialized
= 0;
3195 bcm
->shutting_down
= 0;
3196 bcm43xx_unlock(bcm
, flags
);
3198 err
= bcm43xx_pctl_set_crystal(bcm
, 1);
3201 err
= bcm43xx_pctl_init(bcm
);
3203 goto err_crystal_off
;
3204 err
= bcm43xx_pctl_set_clock(bcm
, BCM43xx_PCTL_CLK_FAST
);
3206 goto err_crystal_off
;
3208 tasklet_enable(&bcm
->isr_tasklet
);
3209 for (i
= 0; i
< bcm
->nr_80211_available
; i
++) {
3210 err
= bcm43xx_switch_core(bcm
, &bcm
->core_80211
[i
]);
3211 assert(err
!= -ENODEV
);
3213 goto err_80211_unwind
;
3215 /* Enable the selected wireless core.
3216 * Connect PHY only on the first core.
3218 if (!bcm43xx_core_enabled(bcm
)) {
3219 if (bcm
->nr_80211_available
== 1) {
3220 connect_phy
= bcm43xx_current_phy(bcm
)->connected
;
3227 bcm43xx_wireless_core_reset(bcm
, connect_phy
);
3231 bcm43xx_wireless_core_mark_inactive(bcm
, &bcm
->core_80211
[0]);
3233 err
= bcm43xx_wireless_core_init(bcm
);
3235 goto err_80211_unwind
;
3238 bcm43xx_mac_suspend(bcm
);
3239 bcm43xx_interrupt_disable(bcm
, BCM43xx_IRQ_ALL
);
3240 bcm43xx_radio_turn_off(bcm
);
3243 bcm
->active_80211_core
= &bcm
->core_80211
[0];
3244 if (bcm
->nr_80211_available
>= 2) {
3245 bcm43xx_switch_core(bcm
, &bcm
->core_80211
[0]);
3246 bcm43xx_mac_enable(bcm
);
3248 bcm43xx_macfilter_clear(bcm
, BCM43xx_MACFILTER_ASSOC
);
3249 bcm43xx_macfilter_set(bcm
, BCM43xx_MACFILTER_SELF
, (u8
*)(bcm
->net_dev
->dev_addr
));
3250 dprintk(KERN_INFO PFX
"80211 cores initialized\n");
3251 bcm43xx_security_init(bcm
);
3252 bcm43xx_softmac_init(bcm
);
3254 bcm43xx_pctl_set_clock(bcm
, BCM43xx_PCTL_CLK_DYNAMIC
);
3256 if (bcm43xx_current_radio(bcm
)->initial_channel
!= 0xFF) {
3257 bcm43xx_mac_suspend(bcm
);
3258 bcm43xx_radio_selectchannel(bcm
, bcm43xx_current_radio(bcm
)->initial_channel
, 0);
3259 bcm43xx_mac_enable(bcm
);
3262 /* Initialization of the board is done. Flag it as such. */
3263 bcm43xx_lock(bcm
, flags
);
3264 bcm
->initialized
= 1;
3265 bcm43xx_unlock(bcm
, flags
);
3267 bcm43xx_periodic_tasks_setup(bcm
);
3268 bcm43xx_sysfs_register(bcm
);
3269 //FIXME: check for bcm43xx_sysfs_register failure. This function is a bit messy regarding unwinding, though...
3276 tasklet_disable(&bcm
->isr_tasklet
);
3277 /* unwind all 80211 initialization */
3278 for (i
= 0; i
< bcm
->nr_80211_available
; i
++) {
3279 if (!bcm
->core_80211
[i
].initialized
)
3281 bcm43xx_interrupt_disable(bcm
, BCM43xx_IRQ_ALL
);
3282 bcm43xx_wireless_core_cleanup(bcm
);
3285 bcm43xx_pctl_set_crystal(bcm
, 0);
3289 static void bcm43xx_detach_board(struct bcm43xx_private
*bcm
)
3291 struct pci_dev
*pci_dev
= bcm
->pci_dev
;
3294 bcm43xx_chipset_detach(bcm
);
3295 /* Do _not_ access the chip, after it is detached. */
3296 iounmap(bcm
->mmio_addr
);
3298 pci_release_regions(pci_dev
);
3299 pci_disable_device(pci_dev
);
3301 /* Free allocated structures/fields */
3302 for (i
= 0; i
< BCM43xx_MAX_80211_CORES
; i
++) {
3303 kfree(bcm
->core_80211_ext
[i
].phy
._lo_pairs
);
3304 if (bcm
->core_80211_ext
[i
].phy
.dyn_tssi_tbl
)
3305 kfree(bcm
->core_80211_ext
[i
].phy
.tssi2dbm
);
3309 static int bcm43xx_read_phyinfo(struct bcm43xx_private
*bcm
)
3311 struct bcm43xx_phyinfo
*phy
= bcm43xx_current_phy(bcm
);
3319 value
= bcm43xx_read16(bcm
, BCM43xx_MMIO_PHY_VER
);
3321 phy_version
= (value
& 0xF000) >> 12;
3322 phy_type
= (value
& 0x0F00) >> 8;
3323 phy_rev
= (value
& 0x000F);
3325 dprintk(KERN_INFO PFX
"Detected PHY: Version: %x, Type %x, Revision %x\n",
3326 phy_version
, phy_type
, phy_rev
);
3329 case BCM43xx_PHYTYPE_A
:
3332 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3333 * if we switch 80211 cores after init is done.
3334 * As we do not implement on the fly switching between
3335 * wireless cores, I will leave this as a future task.
3337 bcm
->ieee
->modulation
= IEEE80211_OFDM_MODULATION
;
3338 bcm
->ieee
->mode
= IEEE_A
;
3339 bcm
->ieee
->freq_band
= IEEE80211_52GHZ_BAND
|
3340 IEEE80211_24GHZ_BAND
;
3342 case BCM43xx_PHYTYPE_B
:
3343 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6 && phy_rev
!= 7)
3345 bcm
->ieee
->modulation
= IEEE80211_CCK_MODULATION
;
3346 bcm
->ieee
->mode
= IEEE_B
;
3347 bcm
->ieee
->freq_band
= IEEE80211_24GHZ_BAND
;
3349 case BCM43xx_PHYTYPE_G
:
3352 bcm
->ieee
->modulation
= IEEE80211_OFDM_MODULATION
|
3353 IEEE80211_CCK_MODULATION
;
3354 bcm
->ieee
->mode
= IEEE_G
;
3355 bcm
->ieee
->freq_band
= IEEE80211_24GHZ_BAND
;
3358 printk(KERN_ERR PFX
"Error: Unknown PHY Type %x\n",
3363 printk(KERN_WARNING PFX
"Invalid PHY Revision %x\n",
3367 phy
->version
= phy_version
;
3368 phy
->type
= phy_type
;
3370 if ((phy_type
== BCM43xx_PHYTYPE_B
) || (phy_type
== BCM43xx_PHYTYPE_G
)) {
3371 p
= kzalloc(sizeof(struct bcm43xx_lopair
) * BCM43xx_LO_COUNT
,
3381 static int bcm43xx_attach_board(struct bcm43xx_private
*bcm
)
3383 struct pci_dev
*pci_dev
= bcm
->pci_dev
;
3384 struct net_device
*net_dev
= bcm
->net_dev
;
3387 void __iomem
*ioaddr
;
3388 unsigned long mmio_start
, mmio_end
, mmio_flags
, mmio_len
;
3391 err
= pci_enable_device(pci_dev
);
3393 printk(KERN_ERR PFX
"unable to wake up pci device (%i)\n", err
);
3398 mmio_start
= pci_resource_start(pci_dev
, 0);
3399 mmio_end
= pci_resource_end(pci_dev
, 0);
3400 mmio_flags
= pci_resource_flags(pci_dev
, 0);
3401 mmio_len
= pci_resource_len(pci_dev
, 0);
3403 /* make sure PCI base addr is MMIO */
3404 if (!(mmio_flags
& IORESOURCE_MEM
)) {
3406 "%s, region #0 not an MMIO resource, aborting\n",
3409 goto err_pci_disable
;
3411 //FIXME: Why is this check disabled for BCM947XX? What is the IO_SIZE there?
3412 #ifndef CONFIG_BCM947XX
3413 if (mmio_len
!= BCM43xx_IO_SIZE
) {
3415 "%s: invalid PCI mem region size(s), aborting\n",
3418 goto err_pci_disable
;
3422 err
= pci_request_regions(pci_dev
, KBUILD_MODNAME
);
3425 "could not access PCI resources (%i)\n", err
);
3426 goto err_pci_disable
;
3429 /* enable PCI bus-mastering */
3430 pci_set_master(pci_dev
);
3432 /* ioremap MMIO region */
3433 ioaddr
= ioremap(mmio_start
, mmio_len
);
3435 printk(KERN_ERR PFX
"%s: cannot remap MMIO, aborting\n",
3438 goto err_pci_release
;
3441 net_dev
->base_addr
= (unsigned long)ioaddr
;
3442 bcm
->mmio_addr
= ioaddr
;
3443 bcm
->mmio_len
= mmio_len
;
3445 bcm43xx_pci_read_config16(bcm
, PCI_SUBSYSTEM_VENDOR_ID
,
3446 &bcm
->board_vendor
);
3447 bcm43xx_pci_read_config16(bcm
, PCI_SUBSYSTEM_ID
,
3449 bcm43xx_pci_read_config16(bcm
, PCI_REVISION_ID
,
3450 &bcm
->board_revision
);
3452 err
= bcm43xx_chipset_attach(bcm
);
3455 err
= bcm43xx_pctl_init(bcm
);
3457 goto err_chipset_detach
;
3458 err
= bcm43xx_probe_cores(bcm
);
3460 goto err_chipset_detach
;
3462 /* Attach all IO cores to the backplane. */
3464 for (i
= 0; i
< bcm
->nr_80211_available
; i
++)
3465 coremask
|= (1 << bcm
->core_80211
[i
].index
);
3466 //FIXME: Also attach some non80211 cores?
3467 err
= bcm43xx_setup_backplane_pci_connection(bcm
, coremask
);
3469 printk(KERN_ERR PFX
"Backplane->PCI connection failed!\n");
3470 goto err_chipset_detach
;
3473 err
= bcm43xx_sprom_extract(bcm
);
3475 goto err_chipset_detach
;
3476 err
= bcm43xx_leds_init(bcm
);
3478 goto err_chipset_detach
;
3480 for (i
= 0; i
< bcm
->nr_80211_available
; i
++) {
3481 err
= bcm43xx_switch_core(bcm
, &bcm
->core_80211
[i
]);
3482 assert(err
!= -ENODEV
);
3484 goto err_80211_unwind
;
3486 /* Enable the selected wireless core.
3487 * Connect PHY only on the first core.
3489 bcm43xx_wireless_core_reset(bcm
, (i
== 0));
3491 err
= bcm43xx_read_phyinfo(bcm
);
3492 if (err
&& (i
== 0))
3493 goto err_80211_unwind
;
3495 err
= bcm43xx_read_radioinfo(bcm
);
3496 if (err
&& (i
== 0))
3497 goto err_80211_unwind
;
3499 err
= bcm43xx_validate_chip(bcm
);
3500 if (err
&& (i
== 0))
3501 goto err_80211_unwind
;
3503 bcm43xx_radio_turn_off(bcm
);
3504 err
= bcm43xx_phy_init_tssi2dbm_table(bcm
);
3506 goto err_80211_unwind
;
3507 bcm43xx_wireless_core_disable(bcm
);
3509 bcm43xx_pctl_set_crystal(bcm
, 0);
3511 /* Set the MAC address in the networking subsystem */
3512 if (bcm43xx_current_phy(bcm
)->type
== BCM43xx_PHYTYPE_A
)
3513 memcpy(bcm
->net_dev
->dev_addr
, bcm
->sprom
.et1macaddr
, 6);
3515 memcpy(bcm
->net_dev
->dev_addr
, bcm
->sprom
.il0macaddr
, 6);
3517 bcm43xx_geo_init(bcm
);
3519 snprintf(bcm
->nick
, IW_ESSID_MAX_SIZE
,
3520 "Broadcom %04X", bcm
->chip_id
);
3527 for (i
= 0; i
< BCM43xx_MAX_80211_CORES
; i
++) {
3528 kfree(bcm
->core_80211_ext
[i
].phy
._lo_pairs
);
3529 if (bcm
->core_80211_ext
[i
].phy
.dyn_tssi_tbl
)
3530 kfree(bcm
->core_80211_ext
[i
].phy
.tssi2dbm
);
3533 bcm43xx_chipset_detach(bcm
);
3535 iounmap(bcm
->mmio_addr
);
3537 pci_release_regions(pci_dev
);
3539 pci_disable_device(pci_dev
);
3543 /* Do the Hardware IO operations to send the txb */
3544 static inline int bcm43xx_tx(struct bcm43xx_private
*bcm
,
3545 struct ieee80211_txb
*txb
)
3549 if (bcm43xx_using_pio(bcm
))
3550 err
= bcm43xx_pio_tx(bcm
, txb
);
3552 err
= bcm43xx_dma_tx(bcm
, txb
);
3557 static void bcm43xx_ieee80211_set_chan(struct net_device
*net_dev
,
3560 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3561 unsigned long flags
;
3563 bcm43xx_lock_mmio(bcm
, flags
);
3564 bcm43xx_mac_suspend(bcm
);
3565 bcm43xx_radio_selectchannel(bcm
, channel
, 0);
3566 bcm43xx_mac_enable(bcm
);
3567 bcm43xx_unlock_mmio(bcm
, flags
);
3570 /* set_security() callback in struct ieee80211_device */
3571 static void bcm43xx_ieee80211_set_security(struct net_device
*net_dev
,
3572 struct ieee80211_security
*sec
)
3574 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3575 struct ieee80211_security
*secinfo
= &bcm
->ieee
->sec
;
3576 unsigned long flags
;
3579 dprintk(KERN_INFO PFX
"set security called\n");
3581 bcm43xx_lock_mmio(bcm
, flags
);
3583 for (keyidx
= 0; keyidx
<WEP_KEYS
; keyidx
++)
3584 if (sec
->flags
& (1<<keyidx
)) {
3585 secinfo
->encode_alg
[keyidx
] = sec
->encode_alg
[keyidx
];
3586 secinfo
->key_sizes
[keyidx
] = sec
->key_sizes
[keyidx
];
3587 memcpy(secinfo
->keys
[keyidx
], sec
->keys
[keyidx
], SCM_KEY_LEN
);
3590 if (sec
->flags
& SEC_ACTIVE_KEY
) {
3591 secinfo
->active_key
= sec
->active_key
;
3592 dprintk(KERN_INFO PFX
" .active_key = %d\n", sec
->active_key
);
3594 if (sec
->flags
& SEC_UNICAST_GROUP
) {
3595 secinfo
->unicast_uses_group
= sec
->unicast_uses_group
;
3596 dprintk(KERN_INFO PFX
" .unicast_uses_group = %d\n", sec
->unicast_uses_group
);
3598 if (sec
->flags
& SEC_LEVEL
) {
3599 secinfo
->level
= sec
->level
;
3600 dprintk(KERN_INFO PFX
" .level = %d\n", sec
->level
);
3602 if (sec
->flags
& SEC_ENABLED
) {
3603 secinfo
->enabled
= sec
->enabled
;
3604 dprintk(KERN_INFO PFX
" .enabled = %d\n", sec
->enabled
);
3606 if (sec
->flags
& SEC_ENCRYPT
) {
3607 secinfo
->encrypt
= sec
->encrypt
;
3608 dprintk(KERN_INFO PFX
" .encrypt = %d\n", sec
->encrypt
);
3610 if (bcm
->initialized
&& !bcm
->ieee
->host_encrypt
) {
3611 if (secinfo
->enabled
) {
3612 /* upload WEP keys to hardware */
3613 char null_address
[6] = { 0 };
3615 for (keyidx
= 0; keyidx
<WEP_KEYS
; keyidx
++) {
3616 if (!(sec
->flags
& (1<<keyidx
)))
3618 switch (sec
->encode_alg
[keyidx
]) {
3619 case SEC_ALG_NONE
: algorithm
= BCM43xx_SEC_ALGO_NONE
; break;
3621 algorithm
= BCM43xx_SEC_ALGO_WEP
;
3622 if (secinfo
->key_sizes
[keyidx
] == 13)
3623 algorithm
= BCM43xx_SEC_ALGO_WEP104
;
3627 algorithm
= BCM43xx_SEC_ALGO_TKIP
;
3631 algorithm
= BCM43xx_SEC_ALGO_AES
;
3637 bcm43xx_key_write(bcm
, keyidx
, algorithm
, sec
->keys
[keyidx
], secinfo
->key_sizes
[keyidx
], &null_address
[0]);
3638 bcm
->key
[keyidx
].enabled
= 1;
3639 bcm
->key
[keyidx
].algorithm
= algorithm
;
3642 bcm43xx_clear_keys(bcm
);
3644 bcm43xx_unlock_mmio(bcm
, flags
);
3647 /* hard_start_xmit() callback in struct ieee80211_device */
3648 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb
*txb
,
3649 struct net_device
*net_dev
,
3652 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3654 unsigned long flags
;
3656 bcm43xx_lock_mmio(bcm
, flags
);
3657 if (likely(bcm
->initialized
))
3658 err
= bcm43xx_tx(bcm
, txb
);
3659 bcm43xx_unlock_mmio(bcm
, flags
);
3664 static struct net_device_stats
* bcm43xx_net_get_stats(struct net_device
*net_dev
)
3666 return &(bcm43xx_priv(net_dev
)->ieee
->stats
);
3669 static void bcm43xx_net_tx_timeout(struct net_device
*net_dev
)
3671 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3672 unsigned long flags
;
3674 bcm43xx_lock_mmio(bcm
, flags
);
3675 bcm43xx_controller_restart(bcm
, "TX timeout");
3676 bcm43xx_unlock_mmio(bcm
, flags
);
3679 #ifdef CONFIG_NET_POLL_CONTROLLER
3680 static void bcm43xx_net_poll_controller(struct net_device
*net_dev
)
3682 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3683 unsigned long flags
;
3685 local_irq_save(flags
);
3686 bcm43xx_interrupt_handler(bcm
->irq
, bcm
, NULL
);
3687 local_irq_restore(flags
);
3689 #endif /* CONFIG_NET_POLL_CONTROLLER */
3691 static int bcm43xx_net_open(struct net_device
*net_dev
)
3693 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3695 return bcm43xx_init_board(bcm
);
3698 static int bcm43xx_net_stop(struct net_device
*net_dev
)
3700 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3702 ieee80211softmac_stop(net_dev
);
3703 bcm43xx_disable_interrupts_sync(bcm
, NULL
);
3704 bcm43xx_free_board(bcm
);
3709 static int bcm43xx_init_private(struct bcm43xx_private
*bcm
,
3710 struct net_device
*net_dev
,
3711 struct pci_dev
*pci_dev
)
3715 bcm
->ieee
= netdev_priv(net_dev
);
3716 bcm
->softmac
= ieee80211_priv(net_dev
);
3717 bcm
->softmac
->set_channel
= bcm43xx_ieee80211_set_chan
;
3719 bcm
->irq_savedstate
= BCM43xx_IRQ_INITIAL
;
3720 bcm
->pci_dev
= pci_dev
;
3721 bcm
->net_dev
= net_dev
;
3722 bcm
->bad_frames_preempt
= modparam_bad_frames_preempt
;
3723 spin_lock_init(&bcm
->_lock
);
3724 tasklet_init(&bcm
->isr_tasklet
,
3725 (void (*)(unsigned long))bcm43xx_interrupt_tasklet
,
3726 (unsigned long)bcm
);
3727 tasklet_disable_nosync(&bcm
->isr_tasklet
);
3729 bcm
->__using_pio
= 1;
3731 err
= pci_set_dma_mask(pci_dev
, DMA_30BIT_MASK
);
3732 err
|= pci_set_consistent_dma_mask(pci_dev
, DMA_30BIT_MASK
);
3734 #ifdef CONFIG_BCM43XX_PIO
3735 printk(KERN_WARNING PFX
"DMA not supported. Falling back to PIO.\n");
3736 bcm
->__using_pio
= 1;
3738 printk(KERN_ERR PFX
"FATAL: DMA not supported and PIO not configured. "
3739 "Recompile the driver with PIO support, please.\n");
3741 #endif /* CONFIG_BCM43XX_PIO */
3744 bcm
->rts_threshold
= BCM43xx_DEFAULT_RTS_THRESHOLD
;
3746 /* default to sw encryption for now */
3747 bcm
->ieee
->host_build_iv
= 0;
3748 bcm
->ieee
->host_encrypt
= 1;
3749 bcm
->ieee
->host_decrypt
= 1;
3751 bcm
->ieee
->iw_mode
= BCM43xx_INITIAL_IWMODE
;
3752 bcm
->ieee
->tx_headroom
= sizeof(struct bcm43xx_txhdr
);
3753 bcm
->ieee
->set_security
= bcm43xx_ieee80211_set_security
;
3754 bcm
->ieee
->hard_start_xmit
= bcm43xx_ieee80211_hard_start_xmit
;
3759 static int __devinit
bcm43xx_init_one(struct pci_dev
*pdev
,
3760 const struct pci_device_id
*ent
)
3762 struct net_device
*net_dev
;
3763 struct bcm43xx_private
*bcm
;
3766 #ifdef CONFIG_BCM947XX
3767 if ((pdev
->bus
->number
== 0) && (pdev
->device
!= 0x0800))
3771 #ifdef DEBUG_SINGLE_DEVICE_ONLY
3772 if (strcmp(pci_name(pdev
), DEBUG_SINGLE_DEVICE_ONLY
))
3776 net_dev
= alloc_ieee80211softmac(sizeof(*bcm
));
3779 "could not allocate ieee80211 device %s\n",
3784 /* initialize the net_device struct */
3785 SET_MODULE_OWNER(net_dev
);
3786 SET_NETDEV_DEV(net_dev
, &pdev
->dev
);
3788 net_dev
->open
= bcm43xx_net_open
;
3789 net_dev
->stop
= bcm43xx_net_stop
;
3790 net_dev
->get_stats
= bcm43xx_net_get_stats
;
3791 net_dev
->tx_timeout
= bcm43xx_net_tx_timeout
;
3792 #ifdef CONFIG_NET_POLL_CONTROLLER
3793 net_dev
->poll_controller
= bcm43xx_net_poll_controller
;
3795 net_dev
->wireless_handlers
= &bcm43xx_wx_handlers_def
;
3796 net_dev
->irq
= pdev
->irq
;
3797 SET_ETHTOOL_OPS(net_dev
, &bcm43xx_ethtool_ops
);
3799 /* initialize the bcm43xx_private struct */
3800 bcm
= bcm43xx_priv(net_dev
);
3801 memset(bcm
, 0, sizeof(*bcm
));
3802 err
= bcm43xx_init_private(bcm
, net_dev
, pdev
);
3804 goto err_free_netdev
;
3806 pci_set_drvdata(pdev
, net_dev
);
3808 err
= bcm43xx_attach_board(bcm
);
3810 goto err_free_netdev
;
3812 err
= register_netdev(net_dev
);
3814 printk(KERN_ERR PFX
"Cannot register net device, "
3817 goto err_detach_board
;
3820 bcm43xx_debugfs_add_device(bcm
);
3827 bcm43xx_detach_board(bcm
);
3829 free_ieee80211softmac(net_dev
);
3833 static void __devexit
bcm43xx_remove_one(struct pci_dev
*pdev
)
3835 struct net_device
*net_dev
= pci_get_drvdata(pdev
);
3836 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3838 bcm43xx_debugfs_remove_device(bcm
);
3839 unregister_netdev(net_dev
);
3840 bcm43xx_detach_board(bcm
);
3841 assert(bcm
->ucode
== NULL
);
3842 free_ieee80211softmac(net_dev
);
3845 /* Hard-reset the chip. Do not call this directly.
3846 * Use bcm43xx_controller_restart()
3848 static void bcm43xx_chip_reset(void *_bcm
)
3850 struct bcm43xx_private
*bcm
= _bcm
;
3851 struct net_device
*net_dev
= bcm
->net_dev
;
3852 struct pci_dev
*pci_dev
= bcm
->pci_dev
;
3854 int was_initialized
= bcm
->initialized
;
3856 netif_stop_queue(bcm
->net_dev
);
3857 tasklet_disable(&bcm
->isr_tasklet
);
3859 bcm
->firmware_norelease
= 1;
3860 if (was_initialized
)
3861 bcm43xx_free_board(bcm
);
3862 bcm
->firmware_norelease
= 0;
3863 bcm43xx_detach_board(bcm
);
3864 err
= bcm43xx_init_private(bcm
, net_dev
, pci_dev
);
3867 err
= bcm43xx_attach_board(bcm
);
3870 if (was_initialized
) {
3871 err
= bcm43xx_init_board(bcm
);
3875 netif_wake_queue(bcm
->net_dev
);
3876 printk(KERN_INFO PFX
"Controller restarted\n");
3880 printk(KERN_ERR PFX
"Controller restart failed\n");
3883 /* Hard-reset the chip.
3884 * This can be called from interrupt or process context.
3885 * Make sure to _not_ re-enable device interrupts after this has been called.
3887 void bcm43xx_controller_restart(struct bcm43xx_private
*bcm
, const char *reason
)
3889 bcm43xx_interrupt_disable(bcm
, BCM43xx_IRQ_ALL
);
3890 bcm43xx_read32(bcm
, BCM43xx_MMIO_STATUS_BITFIELD
); /* dummy read */
3891 printk(KERN_ERR PFX
"Controller RESET (%s) ...\n", reason
);
3892 INIT_WORK(&bcm
->restart_work
, bcm43xx_chip_reset
, bcm
);
3893 schedule_work(&bcm
->restart_work
);
3898 static int bcm43xx_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3900 struct net_device
*net_dev
= pci_get_drvdata(pdev
);
3901 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3902 unsigned long flags
;
3903 int try_to_shutdown
= 0, err
;
3905 dprintk(KERN_INFO PFX
"Suspending...\n");
3907 bcm43xx_lock(bcm
, flags
);
3908 bcm
->was_initialized
= bcm
->initialized
;
3909 if (bcm
->initialized
)
3910 try_to_shutdown
= 1;
3911 bcm43xx_unlock(bcm
, flags
);
3913 netif_device_detach(net_dev
);
3914 if (try_to_shutdown
) {
3915 ieee80211softmac_stop(net_dev
);
3916 err
= bcm43xx_disable_interrupts_sync(bcm
, &bcm
->irq_savedstate
);
3917 if (unlikely(err
)) {
3918 dprintk(KERN_ERR PFX
"Suspend failed.\n");
3921 bcm
->firmware_norelease
= 1;
3922 bcm43xx_free_board(bcm
);
3923 bcm
->firmware_norelease
= 0;
3925 bcm43xx_chipset_detach(bcm
);
3927 pci_save_state(pdev
);
3928 pci_disable_device(pdev
);
3929 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3931 dprintk(KERN_INFO PFX
"Device suspended.\n");
3936 static int bcm43xx_resume(struct pci_dev
*pdev
)
3938 struct net_device
*net_dev
= pci_get_drvdata(pdev
);
3939 struct bcm43xx_private
*bcm
= bcm43xx_priv(net_dev
);
3942 dprintk(KERN_INFO PFX
"Resuming...\n");
3944 pci_set_power_state(pdev
, 0);
3945 pci_enable_device(pdev
);
3946 pci_restore_state(pdev
);
3948 bcm43xx_chipset_attach(bcm
);
3949 if (bcm
->was_initialized
) {
3950 bcm
->irq_savedstate
= BCM43xx_IRQ_INITIAL
;
3951 err
= bcm43xx_init_board(bcm
);
3954 printk(KERN_ERR PFX
"Resume failed!\n");
3958 netif_device_attach(net_dev
);
3960 /*FIXME: This should be handled by softmac instead. */
3961 schedule_work(&bcm
->softmac
->associnfo
.work
);
3963 dprintk(KERN_INFO PFX
"Device resumed.\n");
3968 #endif /* CONFIG_PM */
3970 static struct pci_driver bcm43xx_pci_driver
= {
3971 .name
= KBUILD_MODNAME
,
3972 .id_table
= bcm43xx_pci_tbl
,
3973 .probe
= bcm43xx_init_one
,
3974 .remove
= __devexit_p(bcm43xx_remove_one
),
3976 .suspend
= bcm43xx_suspend
,
3977 .resume
= bcm43xx_resume
,
3978 #endif /* CONFIG_PM */
3981 static int __init
bcm43xx_init(void)
3983 printk(KERN_INFO KBUILD_MODNAME
" driver\n");
3984 bcm43xx_debugfs_init();
3985 return pci_register_driver(&bcm43xx_pci_driver
);
3988 static void __exit
bcm43xx_exit(void)
3990 pci_unregister_driver(&bcm43xx_pci_driver
);
3991 bcm43xx_debugfs_exit();
3994 module_init(bcm43xx_init
)
3995 module_exit(bcm43xx_exit
)
3997 /* vim: set ts=8 sw=8 sts=8: */