arch/mips/include/asm/mach-au1x00/gpio-au1000.h

   1 /*
   2  * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
   3  *
   4  * Copyright (c) 2009 Manuel Lauss.
   5  *
   6  * Licensed under the terms outlined in the file COPYING.
   7  */
   8
   9 #ifndef _ALCHEMY_GPIO_AU1000_H_
  10 #define _ALCHEMY_GPIO_AU1000_H_
  11
  12 #include <asm/mach-au1x00/au1000.h>
  13
  14 /* The default GPIO numberspace as documented in the Alchemy manuals.
  15  * GPIO0-31 from GPIO1 block,   GPIO200-215 from GPIO2 block.
  16  */
  17 #define ALCHEMY_GPIO1_BASE      0
  18 #define ALCHEMY_GPIO2_BASE      200
  19
  20 #define ALCHEMY_GPIO1_NUM       32
  21 #define ALCHEMY_GPIO2_NUM       16
  22 #define ALCHEMY_GPIO1_MAX       (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
  23 #define ALCHEMY_GPIO2_MAX       (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
  24
  25 #define MAKE_IRQ(intc, off)     (AU1000_INTC##intc##_INT_BASE + (off))
  26
  27
  28 static inline int au1000_gpio1_to_irq(int gpio)
  29 {
  30         return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
  31 }
  32
  33 static inline int au1000_gpio2_to_irq(int gpio)
  34 {
  35         return -ENXIO;
  36 }
  37
  38 #ifdef CONFIG_SOC_AU1000
  39 static inline int au1000_irq_to_gpio(int irq)
  40 {
  41         if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
  42                 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
  43
  44         return -ENXIO;
  45 }
  46 #endif
  47
  48 static inline int au1500_gpio1_to_irq(int gpio)
  49 {
  50         gpio -= ALCHEMY_GPIO1_BASE;
  51
  52         switch (gpio) {
  53         case 0 ... 15:
  54         case 20:
  55         case 23 ... 28: return MAKE_IRQ(1, gpio);
  56         }
  57
  58         return -ENXIO;
  59 }
  60
  61 static inline int au1500_gpio2_to_irq(int gpio)
  62 {
  63         gpio -= ALCHEMY_GPIO2_BASE;
  64
  65         switch (gpio) {
  66         case 0 ... 3:   return MAKE_IRQ(1, 16 + gpio - 0);
  67         case 4 ... 5:   return MAKE_IRQ(1, 21 + gpio - 4);
  68         case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
  69         }
  70
  71         return -ENXIO;
  72 }
  73
  74 #ifdef CONFIG_SOC_AU1500
  75 static inline int au1500_irq_to_gpio(int irq)
  76 {
  77         switch (irq) {
  78         case AU1000_GPIO_0 ... AU1000_GPIO_15:
  79         case AU1500_GPIO_20:
  80         case AU1500_GPIO_23 ... AU1500_GPIO_28:
  81                 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
  82         case AU1500_GPIO_200 ... AU1500_GPIO_203:
  83                 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
  84         case AU1500_GPIO_204 ... AU1500_GPIO_205:
  85                 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
  86         case AU1500_GPIO_206 ... AU1500_GPIO_207:
  87                 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
  88         case AU1500_GPIO_208_215:
  89                 return ALCHEMY_GPIO2_BASE + 8;
  90         }
  91
  92         return -ENXIO;
  93 }
  94 #endif
  95
  96 static inline int au1100_gpio1_to_irq(int gpio)
  97 {
  98         return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
  99 }
 100
 101 static inline int au1100_gpio2_to_irq(int gpio)
 102 {
 103         gpio -= ALCHEMY_GPIO2_BASE;
 104
 105         if ((gpio >= 8) && (gpio <= 15))
 106                 return MAKE_IRQ(0, 29);         /* shared GPIO208_215 */
 107
 108         return -ENXIO;
 109 }
 110
 111 #ifdef CONFIG_SOC_AU1100
 112 static inline int au1100_irq_to_gpio(int irq)
 113 {
 114         switch (irq) {
 115         case AU1000_GPIO_0 ... AU1000_GPIO_31:
 116                 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
 117         case AU1100_GPIO_208_215:
 118                 return ALCHEMY_GPIO2_BASE + 8;
 119         }
 120
 121         return -ENXIO;
 122 }
 123 #endif
 124
 125 static inline int au1550_gpio1_to_irq(int gpio)
 126 {
 127         gpio -= ALCHEMY_GPIO1_BASE;
 128
 129         switch (gpio) {
 130         case 0 ... 15:
 131         case 20 ... 28: return MAKE_IRQ(1, gpio);
 132         case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
 133         }
 134
 135         return -ENXIO;
 136 }
 137
 138 static inline int au1550_gpio2_to_irq(int gpio)
 139 {
 140         gpio -= ALCHEMY_GPIO2_BASE;
 141
 142         switch (gpio) {
 143         case 0:         return MAKE_IRQ(1, 16);
 144         case 1 ... 5:   return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
 145         case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
 146         case 8 ... 15:  return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
 147         }
 148
 149         return -ENXIO;
 150 }
 151
 152 #ifdef CONFIG_SOC_AU1550
 153 static inline int au1550_irq_to_gpio(int irq)
 154 {
 155         switch (irq) {
 156         case AU1000_GPIO_0 ... AU1000_GPIO_15:
 157                 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
 158         case AU1550_GPIO_200:
 159         case AU1500_GPIO_201_205:
 160                 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
 161         case AU1500_GPIO_16 ... AU1500_GPIO_28:
 162                 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
 163         case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
 164                 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
 165         }
 166
 167         return -ENXIO;
 168 }
 169 #endif
 170
 171 static inline int au1200_gpio1_to_irq(int gpio)
 172 {
 173         return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
 174 }
 175
 176 static inline int au1200_gpio2_to_irq(int gpio)
 177 {
 178         gpio -= ALCHEMY_GPIO2_BASE;
 179
 180         switch (gpio) {
 181         case 0 ... 2:   return MAKE_IRQ(0, 5 + gpio - 0);
 182         case 3:         return MAKE_IRQ(0, 22);
 183         case 4 ... 7:   return MAKE_IRQ(0, 24 + gpio - 4);
 184         case 8 ... 15:  return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
 185         }
 186
 187         return -ENXIO;
 188 }
 189
 190 #ifdef CONFIG_SOC_AU1200
 191 static inline int au1200_irq_to_gpio(int irq)
 192 {
 193         switch (irq) {
 194         case AU1000_GPIO_0 ... AU1000_GPIO_31:
 195                 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
 196         case AU1200_GPIO_200 ... AU1200_GPIO_202:
 197                 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
 198         case AU1200_GPIO_203:
 199                 return ALCHEMY_GPIO2_BASE + 3;
 200         case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
 201                 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
 202         }
 203
 204         return -ENXIO;
 205 }
 206 #endif
 207
 208 /*
 209  * GPIO1 block macros for common linux gpio functions.
 210  */
 211 static inline void alchemy_gpio1_set_value(int gpio, int v)
 212 {
 213         unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
 214         unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
 215         au_writel(mask, r);
 216         au_sync();
 217 }
 218
 219 static inline int alchemy_gpio1_get_value(int gpio)
 220 {
 221         unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
 222         return au_readl(SYS_PINSTATERD) & mask;
 223 }
 224
 225 static inline int alchemy_gpio1_direction_input(int gpio)
 226 {
 227         unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
 228         au_writel(mask, SYS_TRIOUTCLR);
 229         au_sync();
 230         return 0;
 231 }
 232
 233 static inline int alchemy_gpio1_direction_output(int gpio, int v)
 234 {
 235         /* hardware switches to "output" mode when one of the two
 236          * "set_value" registers is accessed.
 237          */
 238         alchemy_gpio1_set_value(gpio, v);
 239         return 0;
 240 }
 241
 242 static inline int alchemy_gpio1_is_valid(int gpio)
 243 {
 244         return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
 245 }
 246
 247 static inline int alchemy_gpio1_to_irq(int gpio)
 248 {
 249 #if defined(CONFIG_SOC_AU1000)
 250         return au1000_gpio1_to_irq(gpio);
 251 #elif defined(CONFIG_SOC_AU1100)
 252         return au1100_gpio1_to_irq(gpio);
 253 #elif defined(CONFIG_SOC_AU1500)
 254         return au1500_gpio1_to_irq(gpio);
 255 #elif defined(CONFIG_SOC_AU1550)
 256         return au1550_gpio1_to_irq(gpio);
 257 #elif defined(CONFIG_SOC_AU1200)
 258         return au1200_gpio1_to_irq(gpio);
 259 #else
 260         return -ENXIO;
 261 #endif
 262 }
 263
 264 /*
 265  * GPIO2 block macros for common linux GPIO functions. The 'gpio'
 266  * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
 267  */
 268 static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
 269 {
 270         unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
 271         unsigned long d = au_readl(GPIO2_DIR);
 272         if (to_out)
 273                 d |= mask;
 274         else
 275                 d &= ~mask;
 276         au_writel(d, GPIO2_DIR);
 277         au_sync();
 278 }
 279
 280 static inline void alchemy_gpio2_set_value(int gpio, int v)
 281 {
 282         unsigned long mask;
 283         mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
 284         au_writel(mask, GPIO2_OUTPUT);
 285         au_sync();
 286 }
 287
 288 static inline int alchemy_gpio2_get_value(int gpio)
 289 {
 290         return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
 291 }
 292
 293 static inline int alchemy_gpio2_direction_input(int gpio)
 294 {
 295         unsigned long flags;
 296         local_irq_save(flags);
 297         __alchemy_gpio2_mod_dir(gpio, 0);
 298         local_irq_restore(flags);
 299         return 0;
 300 }
 301
 302 static inline int alchemy_gpio2_direction_output(int gpio, int v)
 303 {
 304         unsigned long flags;
 305         alchemy_gpio2_set_value(gpio, v);
 306         local_irq_save(flags);
 307         __alchemy_gpio2_mod_dir(gpio, 1);
 308         local_irq_restore(flags);
 309         return 0;
 310 }
 311
 312 static inline int alchemy_gpio2_is_valid(int gpio)
 313 {
 314         return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
 315 }
 316
 317 static inline int alchemy_gpio2_to_irq(int gpio)
 318 {
 319 #if defined(CONFIG_SOC_AU1000)
 320         return au1000_gpio2_to_irq(gpio);
 321 #elif defined(CONFIG_SOC_AU1100)
 322         return au1100_gpio2_to_irq(gpio);
 323 #elif defined(CONFIG_SOC_AU1500)
 324         return au1500_gpio2_to_irq(gpio);
 325 #elif defined(CONFIG_SOC_AU1550)
 326         return au1550_gpio2_to_irq(gpio);
 327 #elif defined(CONFIG_SOC_AU1200)
 328         return au1200_gpio2_to_irq(gpio);
 329 #else
 330         return -ENXIO;
 331 #endif
 332 }
 333
 334 /**********************************************************************/
 335
 336 /* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
 337  * SYS_PININPUTEN is written to at least once.  On Au1550/Au1200 this
 338  * register enables use of GPIOs as wake source.
 339  */
 340 static inline void alchemy_gpio1_input_enable(void)
 341 {
 342         au_writel(0, SYS_PININPUTEN);   /* the write op is key */
 343         au_sync();
 344 }
 345
 346 /* GPIO2 shared interrupts and control */
 347
 348 static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
 349 {
 350         unsigned long r = au_readl(GPIO2_INTENABLE);
 351         if (en)
 352                 r |= 1 << gpio2;
 353         else
 354                 r &= ~(1 << gpio2);
 355         au_writel(r, GPIO2_INTENABLE);
 356         au_sync();
 357 }
 358
 359 /**
 360  * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
 361  * @gpio2:      The GPIO2 pin to activate (200...215).
 362  *
 363  * GPIO208-215 have one shared interrupt line to the INTC.  They are
 364  * and'ed with a per-pin enable bit and finally or'ed together to form
 365  * a single irq request (useful for active-high sources).
 366  * With this function, a pins' individual contribution to the int request
 367  * can be enabled.  As with all other GPIO-based interrupts, the INTC
 368  * must be programmed to accept the GPIO208_215 interrupt as well.
 369  *
 370  * NOTE: Calling this macro is only necessary for GPIO208-215; all other
 371  * GPIO2-based interrupts have their own request to the INTC.  Please
 372  * consult your Alchemy databook for more information!
 373  *
 374  * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
 375  * line to the INTC, GPIO201_205.  This function can be used for those
 376  * as well.
 377  *
 378  * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
 379  * (200-215 by default). No sanity checks are made,
 380  */
 381 static inline void alchemy_gpio2_enable_int(int gpio2)
 382 {
 383         unsigned long flags;
 384
 385         gpio2 -= ALCHEMY_GPIO2_BASE;
 386
 387 #if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
 388         /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
 389         gpio2 -= 8;
 390 #endif
 391         local_irq_save(flags);
 392         __alchemy_gpio2_mod_int(gpio2, 1);
 393         local_irq_restore(flags);
 394 }
 395
 396 /**
 397  * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
 398  * @gpio2:      The GPIO2 pin to activate (200...215).
 399  *
 400  * see function alchemy_gpio2_enable_int() for more information.
 401  */
 402 static inline void alchemy_gpio2_disable_int(int gpio2)
 403 {
 404         unsigned long flags;
 405
 406         gpio2 -= ALCHEMY_GPIO2_BASE;
 407
 408 #if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
 409         /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
 410         gpio2 -= 8;
 411 #endif
 412         local_irq_save(flags);
 413         __alchemy_gpio2_mod_int(gpio2, 0);
 414         local_irq_restore(flags);
 415 }
 416
 417 /**
 418  * alchemy_gpio2_enable -  Activate GPIO2 block.
 419  *
 420  * The GPIO2 block must be enabled excplicitly to work.  On systems
 421  * where this isn't done by the bootloader, this macro can be used.
 422  */
 423 static inline void alchemy_gpio2_enable(void)
 424 {
 425         au_writel(3, GPIO2_ENABLE);     /* reset, clock enabled */
 426         au_sync();
 427         au_writel(1, GPIO2_ENABLE);     /* clock enabled */
 428         au_sync();
 429 }
 430
 431 /**
 432  * alchemy_gpio2_disable - disable GPIO2 block.
 433  *
 434  * Disable and put GPIO2 block in low-power mode.
 435  */
 436 static inline void alchemy_gpio2_disable(void)
 437 {
 438         au_writel(2, GPIO2_ENABLE);     /* reset, clock disabled */
 439         au_sync();
 440 }
 441
 442 /**********************************************************************/
 443
 444 /* wrappers for on-chip gpios; can be used before gpio chips have been
 445  * registered with gpiolib.
 446  */
 447 static inline int alchemy_gpio_direction_input(int gpio)
 448 {
 449         return (gpio >= ALCHEMY_GPIO2_BASE) ?
 450                 alchemy_gpio2_direction_input(gpio) :
 451                 alchemy_gpio1_direction_input(gpio);
 452 }
 453
 454 static inline int alchemy_gpio_direction_output(int gpio, int v)
 455 {
 456         return (gpio >= ALCHEMY_GPIO2_BASE) ?
 457                 alchemy_gpio2_direction_output(gpio, v) :
 458                 alchemy_gpio1_direction_output(gpio, v);
 459 }
 460
 461 static inline int alchemy_gpio_get_value(int gpio)
 462 {
 463         return (gpio >= ALCHEMY_GPIO2_BASE) ?
 464                 alchemy_gpio2_get_value(gpio) :
 465                 alchemy_gpio1_get_value(gpio);
 466 }
 467
 468 static inline void alchemy_gpio_set_value(int gpio, int v)
 469 {
 470         if (gpio >= ALCHEMY_GPIO2_BASE)
 471                 alchemy_gpio2_set_value(gpio, v);
 472         else
 473                 alchemy_gpio1_set_value(gpio, v);
 474 }
 475
 476 static inline int alchemy_gpio_is_valid(int gpio)
 477 {
 478         return (gpio >= ALCHEMY_GPIO2_BASE) ?
 479                 alchemy_gpio2_is_valid(gpio) :
 480                 alchemy_gpio1_is_valid(gpio);
 481 }
 482
 483 static inline int alchemy_gpio_cansleep(int gpio)
 484 {
 485         return 0;       /* Alchemy never gets tired */
 486 }
 487
 488 static inline int alchemy_gpio_to_irq(int gpio)
 489 {
 490         return (gpio >= ALCHEMY_GPIO2_BASE) ?
 491                 alchemy_gpio2_to_irq(gpio) :
 492                 alchemy_gpio1_to_irq(gpio);
 493 }
 494
 495 static inline int alchemy_irq_to_gpio(int irq)
 496 {
 497 #if defined(CONFIG_SOC_AU1000)
 498         return au1000_irq_to_gpio(irq);
 499 #elif defined(CONFIG_SOC_AU1100)
 500         return au1100_irq_to_gpio(irq);
 501 #elif defined(CONFIG_SOC_AU1500)
 502         return au1500_irq_to_gpio(irq);
 503 #elif defined(CONFIG_SOC_AU1550)
 504         return au1550_irq_to_gpio(irq);
 505 #elif defined(CONFIG_SOC_AU1200)
 506         return au1200_irq_to_gpio(irq);
 507 #else
 508         return -ENXIO;
 509 #endif
 510 }
 511
 512 /**********************************************************************/
 513
 514 /* Linux gpio framework integration.
 515  *
 516  * 4 use cases of Au1000-Au1200 GPIOS:
 517  *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
 518  *      Board must register gpiochips.
 519  *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
 520  *      2 (1 for Au1000) gpio_chips are registered.
 521  *
 522  *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
 523  *      the boards' gpio.h must provide the linux gpio wrapper functions,
 524  *
 525  *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
 526  *      inlinable gpio functions are provided which enable access to the
 527  *      Au1000 gpios only by using the numbers straight out of the data-
 528  *      sheets.
 529
 530  * Cases 1 and 3 are intended for boards which want to provide their own
 531  * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
 532  * which are in part provided by spare Au1000 GPIO pins and in part by
 533  * an external FPGA but you still want them to be accssible in linux
 534  * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
 535  * as required).
 536  */
 537
 538 #ifndef CONFIG_GPIOLIB
 539
 540
 541 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (4) */
 542
 543 static inline int gpio_direction_input(int gpio)
 544 {
 545         return alchemy_gpio_direction_input(gpio);
 546 }
 547
 548 static inline int gpio_direction_output(int gpio, int v)
 549 {
 550         return alchemy_gpio_direction_output(gpio, v);
 551 }
 552
 553 static inline int gpio_get_value(int gpio)
 554 {
 555         return alchemy_gpio_get_value(gpio);
 556 }
 557
 558 static inline void gpio_set_value(int gpio, int v)
 559 {
 560         alchemy_gpio_set_value(gpio, v);
 561 }
 562
 563 static inline int gpio_is_valid(int gpio)
 564 {
 565         return alchemy_gpio_is_valid(gpio);
 566 }
 567
 568 static inline int gpio_cansleep(int gpio)
 569 {
 570         return alchemy_gpio_cansleep(gpio);
 571 }
 572
 573 static inline int gpio_to_irq(int gpio)
 574 {
 575         return alchemy_gpio_to_irq(gpio);
 576 }
 577
 578 static inline int irq_to_gpio(int irq)
 579 {
 580         return alchemy_irq_to_gpio(irq);
 581 }
 582
 583 static inline int gpio_request(unsigned gpio, const char *label)
 584 {
 585         return 0;
 586 }
 587
 588 static inline void gpio_free(unsigned gpio)
 589 {
 590 }
 591
 592 #endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
 593
 594
 595 #else   /* CONFIG GPIOLIB */
 596
 597
 598  /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
 599 #ifndef CONFIG_ALCHEMY_GPIO_INDIRECT    /* case (2) */
 600
 601 /* get everything through gpiolib */
 602 #define gpio_to_irq     __gpio_to_irq
 603 #define gpio_get_value  __gpio_get_value
 604 #define gpio_set_value  __gpio_set_value
 605 #define gpio_cansleep   __gpio_cansleep
 606 #define irq_to_gpio     alchemy_irq_to_gpio
 607
 608 #include <asm-generic/gpio.h>
 609
 610 #endif  /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
 611
 612
 613 #endif  /* !CONFIG_GPIOLIB */
 614
 615 #endif /* _ALCHEMY_GPIO_AU1000_H_ */