drivers/ata/sata_vsc.c

   1 /*
   2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
   3  *
   4  *  Maintained by:  Jeremy Higdon @ SGI
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 SGI
   9  *
  10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  11  *
  12  *
  13  *  This program is free software; you can redistribute it and/or modify
  14  *  it under the terms of the GNU General Public License as published by
  15  *  the Free Software Foundation; either version 2, or (at your option)
  16  *  any later version.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  *  libata documentation is available via 'make {ps|pdf}docs',
  29  *  as Documentation/DocBook/libata.*
  30  *
  31  *  Vitesse hardware documentation presumably available under NDA.
  32  *  Intel 31244 (same hardware interface) documentation presumably
  33  *  available from http://developer.intel.com/
  34  *
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/init.h>
  41 #include <linux/blkdev.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/device.h>
  46 #include <scsi/scsi_host.h>
  47 #include <linux/libata.h>
  48
  49 #define DRV_NAME        "sata_vsc"
  50 #define DRV_VERSION     "2.3"
  51
  52 enum {
  53         VSC_MMIO_BAR                    = 0,
  54
  55         /* Interrupt register offsets (from chip base address) */
  56         VSC_SATA_INT_STAT_OFFSET        = 0x00,
  57         VSC_SATA_INT_MASK_OFFSET        = 0x04,
  58
  59         /* Taskfile registers offsets */
  60         VSC_SATA_TF_CMD_OFFSET          = 0x00,
  61         VSC_SATA_TF_DATA_OFFSET         = 0x00,
  62         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
  63         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
  64         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
  65         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
  66         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
  67         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
  68         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
  69         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
  70         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
  71         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
  72         VSC_SATA_TF_CTL_OFFSET          = 0x29,
  73
  74         /* DMA base */
  75         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
  76         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
  77         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
  78
  79         /* SCRs base */
  80         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
  81         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
  82         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
  83
  84         /* Port stride */
  85         VSC_SATA_PORT_OFFSET            = 0x200,
  86
  87         /* Error interrupt status bit offsets */
  88         VSC_SATA_INT_ERROR_CRC          = 0x40,
  89         VSC_SATA_INT_ERROR_T            = 0x20,
  90         VSC_SATA_INT_ERROR_P            = 0x10,
  91         VSC_SATA_INT_ERROR_R            = 0x8,
  92         VSC_SATA_INT_ERROR_E            = 0x4,
  93         VSC_SATA_INT_ERROR_M            = 0x2,
  94         VSC_SATA_INT_PHY_CHANGE         = 0x1,
  95         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
  96                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
  97                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
  98                               VSC_SATA_INT_PHY_CHANGE),
  99 };
 100
 101 static int vsc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
 102 {
 103         if (sc_reg > SCR_CONTROL)
 104                 return -EINVAL;
 105         *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4));
 106         return 0;
 107 }
 108
 109
 110 static int vsc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
 111 {
 112         if (sc_reg > SCR_CONTROL)
 113                 return -EINVAL;
 114         writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
 115         return 0;
 116 }
 117
 118
 119 static void vsc_freeze(struct ata_port *ap)
 120 {
 121         void __iomem *mask_addr;
 122
 123         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
 124                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 125
 126         writeb(0, mask_addr);
 127 }
 128
 129
 130 static void vsc_thaw(struct ata_port *ap)
 131 {
 132         void __iomem *mask_addr;
 133
 134         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
 135                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 136
 137         writeb(0xff, mask_addr);
 138 }
 139
 140
 141 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
 142 {
 143         void __iomem *mask_addr;
 144         u8 mask;
 145
 146         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
 147                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 148         mask = readb(mask_addr);
 149         if (ctl & ATA_NIEN)
 150                 mask |= 0x80;
 151         else
 152                 mask &= 0x7F;
 153         writeb(mask, mask_addr);
 154 }
 155
 156
 157 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
 158 {
 159         struct ata_ioports *ioaddr = &ap->ioaddr;
 160         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 161
 162         /*
 163          * The only thing the ctl register is used for is SRST.
 164          * That is not enabled or disabled via tf_load.
 165          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
 166          */
 167         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
 168                 ap->last_ctl = tf->ctl;
 169                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
 170         }
 171         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 172                 writew(tf->feature | (((u16)tf->hob_feature) << 8),
 173                        ioaddr->feature_addr);
 174                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
 175                        ioaddr->nsect_addr);
 176                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
 177                        ioaddr->lbal_addr);
 178                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
 179                        ioaddr->lbam_addr);
 180                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
 181                        ioaddr->lbah_addr);
 182         } else if (is_addr) {
 183                 writew(tf->feature, ioaddr->feature_addr);
 184                 writew(tf->nsect, ioaddr->nsect_addr);
 185                 writew(tf->lbal, ioaddr->lbal_addr);
 186                 writew(tf->lbam, ioaddr->lbam_addr);
 187                 writew(tf->lbah, ioaddr->lbah_addr);
 188         }
 189
 190         if (tf->flags & ATA_TFLAG_DEVICE)
 191                 writeb(tf->device, ioaddr->device_addr);
 192
 193         ata_wait_idle(ap);
 194 }
 195
 196
 197 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 198 {
 199         struct ata_ioports *ioaddr = &ap->ioaddr;
 200         u16 nsect, lbal, lbam, lbah, feature;
 201
 202         tf->command = ata_check_status(ap);
 203         tf->device = readw(ioaddr->device_addr);
 204         feature = readw(ioaddr->error_addr);
 205         nsect = readw(ioaddr->nsect_addr);
 206         lbal = readw(ioaddr->lbal_addr);
 207         lbam = readw(ioaddr->lbam_addr);
 208         lbah = readw(ioaddr->lbah_addr);
 209
 210         tf->feature = feature;
 211         tf->nsect = nsect;
 212         tf->lbal = lbal;
 213         tf->lbam = lbam;
 214         tf->lbah = lbah;
 215
 216         if (tf->flags & ATA_TFLAG_LBA48) {
 217                 tf->hob_feature = feature >> 8;
 218                 tf->hob_nsect = nsect >> 8;
 219                 tf->hob_lbal = lbal >> 8;
 220                 tf->hob_lbam = lbam >> 8;
 221                 tf->hob_lbah = lbah >> 8;
 222         }
 223 }
 224
 225 static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
 226 {
 227         if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
 228                 ata_port_freeze(ap);
 229         else
 230                 ata_port_abort(ap);
 231 }
 232
 233 static void vsc_port_intr(u8 port_status, struct ata_port *ap)
 234 {
 235         struct ata_queued_cmd *qc;
 236         int handled = 0;
 237
 238         if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
 239                 vsc_error_intr(port_status, ap);
 240                 return;
 241         }
 242
 243         qc = ata_qc_from_tag(ap, ap->link.active_tag);
 244         if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
 245                 handled = ata_host_intr(ap, qc);
 246
 247         /* We received an interrupt during a polled command,
 248          * or some other spurious condition.  Interrupt reporting
 249          * with this hardware is fairly reliable so it is safe to
 250          * simply clear the interrupt
 251          */
 252         if (unlikely(!handled))
 253                 ata_chk_status(ap);
 254 }
 255
 256 /*
 257  * vsc_sata_interrupt
 258  *
 259  * Read the interrupt register and process for the devices that have them pending.
 260  */
 261 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
 262 {
 263         struct ata_host *host = dev_instance;
 264         unsigned int i;
 265         unsigned int handled = 0;
 266         u32 status;
 267
 268         status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
 269
 270         if (unlikely(status == 0xffffffff || status == 0)) {
 271                 if (status)
 272                         dev_printk(KERN_ERR, host->dev,
 273                                 ": IRQ status == 0xffffffff, "
 274                                 "PCI fault or device removal?\n");
 275                 goto out;
 276         }
 277
 278         spin_lock(&host->lock);
 279
 280         for (i = 0; i < host->n_ports; i++) {
 281                 u8 port_status = (status >> (8 * i)) & 0xff;
 282                 if (port_status) {
 283                         struct ata_port *ap = host->ports[i];
 284
 285                         if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
 286                                 vsc_port_intr(port_status, ap);
 287                                 handled++;
 288                         } else
 289                                 dev_printk(KERN_ERR, host->dev,
 290                                         ": interrupt from disabled port %d\n", i);
 291                 }
 292         }
 293
 294         spin_unlock(&host->lock);
 295 out:
 296         return IRQ_RETVAL(handled);
 297 }
 298
 299
 300 static struct scsi_host_template vsc_sata_sht = {
 301         .module                 = THIS_MODULE,
 302         .name                   = DRV_NAME,
 303         .ioctl                  = ata_scsi_ioctl,
 304         .queuecommand           = ata_scsi_queuecmd,
 305         .can_queue              = ATA_DEF_QUEUE,
 306         .this_id                = ATA_SHT_THIS_ID,
 307         .sg_tablesize           = LIBATA_MAX_PRD,
 308         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 309         .emulated               = ATA_SHT_EMULATED,
 310         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 311         .proc_name              = DRV_NAME,
 312         .dma_boundary           = ATA_DMA_BOUNDARY,
 313         .slave_configure        = ata_scsi_slave_config,
 314         .slave_destroy          = ata_scsi_slave_destroy,
 315         .bios_param             = ata_std_bios_param,
 316 };
 317
 318
 319 static const struct ata_port_operations vsc_sata_ops = {
 320         .tf_load                = vsc_sata_tf_load,
 321         .tf_read                = vsc_sata_tf_read,
 322         .exec_command           = ata_exec_command,
 323         .check_status           = ata_check_status,
 324         .dev_select             = ata_std_dev_select,
 325         .bmdma_setup            = ata_bmdma_setup,
 326         .bmdma_start            = ata_bmdma_start,
 327         .bmdma_stop             = ata_bmdma_stop,
 328         .bmdma_status           = ata_bmdma_status,
 329         .qc_prep                = ata_qc_prep,
 330         .qc_issue               = ata_qc_issue_prot,
 331         .data_xfer              = ata_data_xfer,
 332         .freeze                 = vsc_freeze,
 333         .thaw                   = vsc_thaw,
 334         .error_handler          = ata_bmdma_error_handler,
 335         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
 336         .irq_clear              = ata_bmdma_irq_clear,
 337         .irq_on                 = ata_irq_on,
 338         .scr_read               = vsc_sata_scr_read,
 339         .scr_write              = vsc_sata_scr_write,
 340         .port_start             = ata_port_start,
 341 };
 342
 343 static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
 344                                           void __iomem *base)
 345 {
 346         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
 347         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
 348         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
 349         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
 350         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
 351         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
 352         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
 353         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
 354         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
 355         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
 356         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
 357         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
 358         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
 359         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
 360         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
 361         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
 362         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
 363 }
 364
 365
 366 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 367 {
 368         static const struct ata_port_info pi = {
 369                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 370                                   ATA_FLAG_MMIO,
 371                 .pio_mask       = 0x1f,
 372                 .mwdma_mask     = 0x07,
 373                 .udma_mask      = ATA_UDMA6,
 374                 .port_ops       = &vsc_sata_ops,
 375         };
 376         const struct ata_port_info *ppi[] = { &pi, NULL };
 377         static int printed_version;
 378         struct ata_host *host;
 379         void __iomem *mmio_base;
 380         int i, rc;
 381         u8 cls;
 382
 383         if (!printed_version++)
 384                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 385
 386         /* allocate host */
 387         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
 388         if (!host)
 389                 return -ENOMEM;
 390
 391         rc = pcim_enable_device(pdev);
 392         if (rc)
 393                 return rc;
 394
 395         /* check if we have needed resource mapped */
 396         if (pci_resource_len(pdev, 0) == 0)
 397                 return -ENODEV;
 398
 399         /* map IO regions and intialize host accordingly */
 400         rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
 401         if (rc == -EBUSY)
 402                 pcim_pin_device(pdev);
 403         if (rc)
 404                 return rc;
 405         host->iomap = pcim_iomap_table(pdev);
 406
 407         mmio_base = host->iomap[VSC_MMIO_BAR];
 408
 409         for (i = 0; i < host->n_ports; i++) {
 410                 struct ata_port *ap = host->ports[i];
 411                 unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
 412
 413                 vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
 414
 415                 ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
 416                 ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
 417         }
 418
 419         /*
 420          * Use 32 bit DMA mask, because 64 bit address support is poor.
 421          */
 422         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 423         if (rc)
 424                 return rc;
 425         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 426         if (rc)
 427                 return rc;
 428
 429         /*
 430          * Due to a bug in the chip, the default cache line size can't be
 431          * used (unless the default is non-zero).
 432          */
 433         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
 434         if (cls == 0x00)
 435                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 436
 437         if (pci_enable_msi(pdev) == 0)
 438                 pci_intx(pdev, 0);
 439
 440         /*
 441          * Config offset 0x98 is "Extended Control and Status Register 0"
 442          * Default value is (1 << 28).  All bits except bit 28 are reserved in
 443          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
 444          * If bit 28 is clear, each port has its own LED.
 445          */
 446         pci_write_config_dword(pdev, 0x98, 0);
 447
 448         pci_set_master(pdev);
 449         return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
 450                                  IRQF_SHARED, &vsc_sata_sht);
 451 }
 452
 453 static const struct pci_device_id vsc_sata_pci_tbl[] = {
 454         { PCI_VENDOR_ID_VITESSE, 0x7174,
 455           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 456         { PCI_VENDOR_ID_INTEL, 0x3200,
 457           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 458
 459         { }     /* terminate list */
 460 };
 461
 462 static struct pci_driver vsc_sata_pci_driver = {
 463         .name                   = DRV_NAME,
 464         .id_table               = vsc_sata_pci_tbl,
 465         .probe                  = vsc_sata_init_one,
 466         .remove                 = ata_pci_remove_one,
 467 };
 468
 469 static int __init vsc_sata_init(void)
 470 {
 471         return pci_register_driver(&vsc_sata_pci_driver);
 472 }
 473
 474 static void __exit vsc_sata_exit(void)
 475 {
 476         pci_unregister_driver(&vsc_sata_pci_driver);
 477 }
 478
 479 MODULE_AUTHOR("Jeremy Higdon");
 480 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
 481 MODULE_LICENSE("GPL");
 482 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
 483 MODULE_VERSION(DRV_VERSION);
 484
 485 module_init(vsc_sata_init);
 486 module_exit(vsc_sata_exit);