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ath9k: Remove ath9k_rate_table
[linux-2.6/linux-2.6-openrd.git] / drivers / net / wireless / ath9k / hw.c
bloba26867c56a8256e1b6410fca11f29cebcc248e1a
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "core.h"
21 #include "hw.h"
22 #include "reg.h"
23 #include "phy.h"
24 #include "initvals.h"
25
26 static const u8 CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
27
28 extern struct hal_percal_data iq_cal_multi_sample;
29 extern struct hal_percal_data iq_cal_single_sample;
30 extern struct hal_percal_data adc_gain_cal_multi_sample;
31 extern struct hal_percal_data adc_gain_cal_single_sample;
32 extern struct hal_percal_data adc_dc_cal_multi_sample;
33 extern struct hal_percal_data adc_dc_cal_single_sample;
34 extern struct hal_percal_data adc_init_dc_cal;
35
36 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
37 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
38 enum ath9k_ht_macmode macmode);
39 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
40 struct ar5416_eeprom *pEepData,
41 u32 reg, u32 value);
42 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
43 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
44
45 /********************/
46 /* Helper Functions */
47 /********************/
48
49 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
50 {
51 if (ah->ah_curchan != NULL)
52 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, ah->ah_curchan)];
53 else
54 return clks / CLOCK_RATE[ATH9K_MODE_11B];
55 }
56
57 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
58 {
59 struct ath9k_channel *chan = ah->ah_curchan;
60
61 if (chan && IS_CHAN_HT40(chan))
62 return ath9k_hw_mac_usec(ah, clks) / 2;
63 else
64 return ath9k_hw_mac_usec(ah, clks);
65 }
66
67 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
68 {
69 if (ah->ah_curchan != NULL)
70 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah,
71 ah->ah_curchan)];
72 else
73 return usecs * CLOCK_RATE[ATH9K_MODE_11B];
74 }
75
76 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
77 {
78 struct ath9k_channel *chan = ah->ah_curchan;
79
80 if (chan && IS_CHAN_HT40(chan))
81 return ath9k_hw_mac_clks(ah, usecs) * 2;
82 else
83 return ath9k_hw_mac_clks(ah, usecs);
84 }
85
86 enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
87 const struct ath9k_channel *chan)
88 {
89 if (IS_CHAN_CCK(chan))
90 return ATH9K_MODE_11A;
91 if (IS_CHAN_G(chan))
92 return ATH9K_MODE_11G;
93 return ATH9K_MODE_11A;
94 }
95
96 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
97 {
98 int i;
99
100 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
101 if ((REG_READ(ah, reg) & mask) == val)
102 return true;
103
104 udelay(AH_TIME_QUANTUM);
105 }
106 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
107 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
108 __func__, reg, REG_READ(ah, reg), mask, val);
109
110 return false;
111 }
112
113 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
114 {
115 u32 retval;
116 int i;
117
118 for (i = 0, retval = 0; i < n; i++) {
119 retval = (retval << 1) | (val & 1);
120 val >>= 1;
121 }
122 return retval;
123 }
124
125 bool ath9k_get_channel_edges(struct ath_hal *ah,
126 u16 flags, u16 *low,
127 u16 *high)
128 {
129 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
130
131 if (flags & CHANNEL_5GHZ) {
132 *low = pCap->low_5ghz_chan;
133 *high = pCap->high_5ghz_chan;
134 return true;
135 }
136 if ((flags & CHANNEL_2GHZ)) {
137 *low = pCap->low_2ghz_chan;
138 *high = pCap->high_2ghz_chan;
139 return true;
140 }
141 return false;
142 }
143
144 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
145 struct ath_rate_table *rates,
146 u32 frameLen, u16 rateix,
147 bool shortPreamble)
148 {
149 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
150 u32 kbps;
151
152 kbps = rates->info[rateix].ratekbps;
153
154 if (kbps == 0)
155 return 0;
156
157 switch (rates->info[rateix].phy) {
158 case PHY_CCK:
159 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
160 if (shortPreamble && rates->info[rateix].short_preamble)
161 phyTime >>= 1;
162 numBits = frameLen << 3;
163 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
164 break;
165 case PHY_OFDM:
166 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
167 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
168 numBits = OFDM_PLCP_BITS + (frameLen << 3);
169 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
170 txTime = OFDM_SIFS_TIME_QUARTER
171 + OFDM_PREAMBLE_TIME_QUARTER
172 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
173 } else if (ah->ah_curchan &&
174 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
175 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
176 numBits = OFDM_PLCP_BITS + (frameLen << 3);
177 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
178 txTime = OFDM_SIFS_TIME_HALF +
179 OFDM_PREAMBLE_TIME_HALF
180 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
181 } else {
182 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
183 numBits = OFDM_PLCP_BITS + (frameLen << 3);
184 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
185 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
186 + (numSymbols * OFDM_SYMBOL_TIME);
187 }
188 break;
189 default:
190 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
191 "%s: unknown phy %u (rate ix %u)\n", __func__,
192 rates->info[rateix].phy, rateix);
193 txTime = 0;
194 break;
195 }
196
197 return txTime;
198 }
199
200 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags)
201 {
202 if (flags & CHANNEL_2GHZ) {
203 if (freq == 2484)
204 return 14;
205 if (freq < 2484)
206 return (freq - 2407) / 5;
207 else
208 return 15 + ((freq - 2512) / 20);
209 } else if (flags & CHANNEL_5GHZ) {
210 if (ath9k_regd_is_public_safety_sku(ah) &&
211 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
212 return ((freq * 10) +
213 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
214 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
215 return (freq - 4000) / 5;
216 } else {
217 return (freq - 5000) / 5;
218 }
219 } else {
220 if (freq == 2484)
221 return 14;
222 if (freq < 2484)
223 return (freq - 2407) / 5;
224 if (freq < 5000) {
225 if (ath9k_regd_is_public_safety_sku(ah)
226 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
227 return ((freq * 10) +
228 (((freq % 5) ==
229 2) ? 5 : 0) - 49400) / 5;
230 } else if (freq > 4900) {
231 return (freq - 4000) / 5;
232 } else {
233 return 15 + ((freq - 2512) / 20);
234 }
235 }
236 return (freq - 5000) / 5;
237 }
238 }
239
240 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
241 struct ath9k_channel *chan,
242 struct chan_centers *centers)
243 {
244 int8_t extoff;
245 struct ath_hal_5416 *ahp = AH5416(ah);
246
247 if (!IS_CHAN_HT40(chan)) {
248 centers->ctl_center = centers->ext_center =
249 centers->synth_center = chan->channel;
250 return;
251 }
252
253 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
254 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
255 centers->synth_center =
256 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
257 extoff = 1;
258 } else {
259 centers->synth_center =
260 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
261 extoff = -1;
262 }
263
264 centers->ctl_center =
265 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
266 centers->ext_center =
267 centers->synth_center + (extoff *
268 ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
269 HT40_CHANNEL_CENTER_SHIFT : 15));
270
271 }
272
273 /******************/
274 /* Chip Revisions */
275 /******************/
276
277 static void ath9k_hw_read_revisions(struct ath_hal *ah)
278 {
279 u32 val;
280
281 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
282
283 if (val == 0xFF) {
284 val = REG_READ(ah, AR_SREV);
285 ah->ah_macVersion = (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
287 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
288 } else {
289 if (!AR_SREV_9100(ah))
290 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
291
292 ah->ah_macRev = val & AR_SREV_REVISION;
293
294 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->ah_isPciExpress = true;
296 }
297 }
298
299 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
300 {
301 u32 val;
302 int i;
303
304 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
305
306 for (i = 0; i < 8; i++)
307 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
308 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
309 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
310
311 return ath9k_hw_reverse_bits(val, 8);
312 }
313
314 /************************************/
315 /* HW Attach, Detach, Init Routines */
316 /************************************/
317
318 static void ath9k_hw_disablepcie(struct ath_hal *ah)
319 {
320 if (!AR_SREV_9100(ah))
321 return;
322
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
324 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
326 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
327 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
328 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
329 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
330 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
332
333 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
334 }
335
336 static bool ath9k_hw_chip_test(struct ath_hal *ah)
337 {
338 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
339 u32 regHold[2];
340 u32 patternData[4] = { 0x55555555,
341 0xaaaaaaaa,
342 0x66666666,
343 0x99999999 };
344 int i, j;
345
346 for (i = 0; i < 2; i++) {
347 u32 addr = regAddr[i];
348 u32 wrData, rdData;
349
350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
356 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
357 "%s: address test failed "
358 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
359 __func__, addr, wrData, rdData);
360 return false;
361 }
362 }
363 for (j = 0; j < 4; j++) {
364 wrData = patternData[j];
365 REG_WRITE(ah, addr, wrData);
366 rdData = REG_READ(ah, addr);
367 if (wrData != rdData) {
368 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
369 "%s: address test failed "
370 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
371 __func__, addr, wrData, rdData);
372 return false;
373 }
374 }
375 REG_WRITE(ah, regAddr[i], regHold[i]);
376 }
377 udelay(100);
378 return true;
379 }
380
381 static const char *ath9k_hw_devname(u16 devid)
382 {
383 switch (devid) {
384 case AR5416_DEVID_PCI:
385 return "Atheros 5416";
386 case AR5416_DEVID_PCIE:
387 return "Atheros 5418";
388 case AR9160_DEVID_PCI:
389 return "Atheros 9160";
390 case AR9280_DEVID_PCI:
391 case AR9280_DEVID_PCIE:
392 return "Atheros 9280";
393 }
394
395 return NULL;
396 }
397
398 static void ath9k_hw_set_defaults(struct ath_hal *ah)
399 {
400 int i;
401
402 ah->ah_config.dma_beacon_response_time = 2;
403 ah->ah_config.sw_beacon_response_time = 10;
404 ah->ah_config.additional_swba_backoff = 0;
405 ah->ah_config.ack_6mb = 0x0;
406 ah->ah_config.cwm_ignore_extcca = 0;
407 ah->ah_config.pcie_powersave_enable = 0;
408 ah->ah_config.pcie_l1skp_enable = 0;
409 ah->ah_config.pcie_clock_req = 0;
410 ah->ah_config.pcie_power_reset = 0x100;
411 ah->ah_config.pcie_restore = 0;
412 ah->ah_config.pcie_waen = 0;
413 ah->ah_config.analog_shiftreg = 1;
414 ah->ah_config.ht_enable = 1;
415 ah->ah_config.ofdm_trig_low = 200;
416 ah->ah_config.ofdm_trig_high = 500;
417 ah->ah_config.cck_trig_high = 200;
418 ah->ah_config.cck_trig_low = 100;
419 ah->ah_config.enable_ani = 1;
420 ah->ah_config.noise_immunity_level = 4;
421 ah->ah_config.ofdm_weaksignal_det = 1;
422 ah->ah_config.cck_weaksignal_thr = 0;
423 ah->ah_config.spur_immunity_level = 2;
424 ah->ah_config.firstep_level = 0;
425 ah->ah_config.rssi_thr_high = 40;
426 ah->ah_config.rssi_thr_low = 7;
427 ah->ah_config.diversity_control = 0;
428 ah->ah_config.antenna_switch_swap = 0;
429
430 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
431 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
432 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
433 }
434
435 ah->ah_config.intr_mitigation = 1;
436 }
437
438 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
439 struct ath_softc *sc,
440 void __iomem *mem,
441 int *status)
442 {
443 static const u8 defbssidmask[ETH_ALEN] =
444 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
445 struct ath_hal_5416 *ahp;
446 struct ath_hal *ah;
447
448 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
449 if (ahp == NULL) {
450 DPRINTF(sc, ATH_DBG_FATAL,
451 "%s: cannot allocate memory for state block\n",
452 __func__);
453 *status = -ENOMEM;
454 return NULL;
455 }
456
457 ah = &ahp->ah;
458 ah->ah_sc = sc;
459 ah->ah_sh = mem;
460 ah->ah_magic = AR5416_MAGIC;
461 ah->ah_countryCode = CTRY_DEFAULT;
462 ah->ah_devid = devid;
463 ah->ah_subvendorid = 0;
464
465 ah->ah_flags = 0;
466 if ((devid == AR5416_AR9100_DEVID))
467 ah->ah_macVersion = AR_SREV_VERSION_9100;
468 if (!AR_SREV_9100(ah))
469 ah->ah_flags = AH_USE_EEPROM;
470
471 ah->ah_powerLimit = MAX_RATE_POWER;
472 ah->ah_tpScale = ATH9K_TP_SCALE_MAX;
473 ahp->ah_atimWindow = 0;
474 ahp->ah_diversityControl = ah->ah_config.diversity_control;
475 ahp->ah_antennaSwitchSwap =
476 ah->ah_config.antenna_switch_swap;
477 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
478 ahp->ah_beaconInterval = 100;
479 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
480 ahp->ah_slottime = (u32) -1;
481 ahp->ah_acktimeout = (u32) -1;
482 ahp->ah_ctstimeout = (u32) -1;
483 ahp->ah_globaltxtimeout = (u32) -1;
484 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
485
486 ahp->ah_gBeaconRate = 0;
487
488 return ahp;
489 }
490
491 static int ath9k_hw_rfattach(struct ath_hal *ah)
492 {
493 bool rfStatus = false;
494 int ecode = 0;
495
496 rfStatus = ath9k_hw_init_rf(ah, &ecode);
497 if (!rfStatus) {
498 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
499 "%s: RF setup failed, status %u\n", __func__,
500 ecode);
501 return ecode;
502 }
503
504 return 0;
505 }
506
507 static int ath9k_hw_rf_claim(struct ath_hal *ah)
508 {
509 u32 val;
510
511 REG_WRITE(ah, AR_PHY(0), 0x00000007);
512
513 val = ath9k_hw_get_radiorev(ah);
514 switch (val & AR_RADIO_SREV_MAJOR) {
515 case 0:
516 val = AR_RAD5133_SREV_MAJOR;
517 break;
518 case AR_RAD5133_SREV_MAJOR:
519 case AR_RAD5122_SREV_MAJOR:
520 case AR_RAD2133_SREV_MAJOR:
521 case AR_RAD2122_SREV_MAJOR:
522 break;
523 default:
524 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
525 "%s: 5G Radio Chip Rev 0x%02X is not "
526 "supported by this driver\n",
527 __func__, ah->ah_analog5GhzRev);
528 return -EOPNOTSUPP;
529 }
530
531 ah->ah_analog5GhzRev = val;
532
533 return 0;
534 }
535
536 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
537 {
538 u32 sum;
539 int i;
540 u16 eeval;
541 struct ath_hal_5416 *ahp = AH5416(ah);
542
543 sum = 0;
544 for (i = 0; i < 3; i++) {
545 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
546 sum += eeval;
547 ahp->ah_macaddr[2 * i] = eeval >> 8;
548 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
549 }
550 if (sum == 0 || sum == 0xffff * 3) {
551 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
552 "%s: mac address read failed: %pM\n", __func__,
553 ahp->ah_macaddr);
554 return -EADDRNOTAVAIL;
555 }
556
557 return 0;
558 }
559
560 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
561 {
562 u32 rxgain_type;
563 struct ath_hal_5416 *ahp = AH5416(ah);
564
565 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
566 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
567
568 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
569 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
570 ar9280Modes_backoff_13db_rxgain_9280_2,
571 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
572 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
573 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
574 ar9280Modes_backoff_23db_rxgain_9280_2,
575 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
576 else
577 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
578 ar9280Modes_original_rxgain_9280_2,
579 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
580 } else
581 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
582 ar9280Modes_original_rxgain_9280_2,
583 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
584 }
585
586 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
587 {
588 u32 txgain_type;
589 struct ath_hal_5416 *ahp = AH5416(ah);
590
591 if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
592 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
593
594 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
595 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
596 ar9280Modes_high_power_tx_gain_9280_2,
597 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
598 else
599 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
600 ar9280Modes_original_tx_gain_9280_2,
601 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
602 } else
603 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
604 ar9280Modes_original_tx_gain_9280_2,
605 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
606 }
607
608 static int ath9k_hw_post_attach(struct ath_hal *ah)
609 {
610 int ecode;
611
612 if (!ath9k_hw_chip_test(ah)) {
613 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
614 "%s: hardware self-test failed\n", __func__);
615 return -ENODEV;
616 }
617
618 ecode = ath9k_hw_rf_claim(ah);
619 if (ecode != 0)
620 return ecode;
621
622 ecode = ath9k_hw_eeprom_attach(ah);
623 if (ecode != 0)
624 return ecode;
625 ecode = ath9k_hw_rfattach(ah);
626 if (ecode != 0)
627 return ecode;
628
629 if (!AR_SREV_9100(ah)) {
630 ath9k_hw_ani_setup(ah);
631 ath9k_hw_ani_attach(ah);
632 }
633
634 return 0;
635 }
636
637 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
638 void __iomem *mem, int *status)
639 {
640 struct ath_hal_5416 *ahp;
641 struct ath_hal *ah;
642 int ecode;
643 #ifndef CONFIG_SLOW_ANT_DIV
644 u32 i;
645 u32 j;
646 #endif
647
648 ahp = ath9k_hw_newstate(devid, sc, mem, status);
649 if (ahp == NULL)
650 return NULL;
651
652 ah = &ahp->ah;
653
654 ath9k_hw_set_defaults(ah);
655
656 if (ah->ah_config.intr_mitigation != 0)
657 ahp->ah_intrMitigation = true;
658
659 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
660 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't reset chip\n",
661 __func__);
662 ecode = -EIO;
663 goto bad;
664 }
665
666 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
667 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: couldn't wakeup chip\n",
668 __func__);
669 ecode = -EIO;
670 goto bad;
671 }
672
673 if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
674 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
675 ah->ah_config.serialize_regmode =
676 SER_REG_MODE_ON;
677 } else {
678 ah->ah_config.serialize_regmode =
679 SER_REG_MODE_OFF;
680 }
681 }
682
683 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
684 "%s: serialize_regmode is %d\n",
685 __func__, ah->ah_config.serialize_regmode);
686
687 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
688 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
689 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
690 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
691 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
692 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
693 "this driver\n", __func__,
694 ah->ah_macVersion, ah->ah_macRev);
695 ecode = -EOPNOTSUPP;
696 goto bad;
697 }
698
699 if (AR_SREV_9100(ah)) {
700 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
701 ahp->ah_suppCals = IQ_MISMATCH_CAL;
702 ah->ah_isPciExpress = false;
703 }
704 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
705
706 if (AR_SREV_9160_10_OR_LATER(ah)) {
707 if (AR_SREV_9280_10_OR_LATER(ah)) {
708 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
709 ahp->ah_adcGainCalData.calData =
710 &adc_gain_cal_single_sample;
711 ahp->ah_adcDcCalData.calData =
712 &adc_dc_cal_single_sample;
713 ahp->ah_adcDcCalInitData.calData =
714 &adc_init_dc_cal;
715 } else {
716 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
717 ahp->ah_adcGainCalData.calData =
718 &adc_gain_cal_multi_sample;
719 ahp->ah_adcDcCalData.calData =
720 &adc_dc_cal_multi_sample;
721 ahp->ah_adcDcCalInitData.calData =
722 &adc_init_dc_cal;
723 }
724 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
725 }
726
727 if (AR_SREV_9160(ah)) {
728 ah->ah_config.enable_ani = 1;
729 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
730 ATH9K_ANI_FIRSTEP_LEVEL);
731 } else {
732 ahp->ah_ani_function = ATH9K_ANI_ALL;
733 if (AR_SREV_9280_10_OR_LATER(ah)) {
734 ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
735 }
736 }
737
738 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
739 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
740 ah->ah_macVersion, ah->ah_macRev);
741
742 if (AR_SREV_9280_20_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
744 ARRAY_SIZE(ar9280Modes_9280_2), 6);
745 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
746 ARRAY_SIZE(ar9280Common_9280_2), 2);
747
748 if (ah->ah_config.pcie_clock_req) {
749 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
750 ar9280PciePhy_clkreq_off_L1_9280,
751 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
752 } else {
753 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
754 ar9280PciePhy_clkreq_always_on_L1_9280,
755 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
756 }
757 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
758 ar9280Modes_fast_clock_9280_2,
759 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
760 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
761 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
762 ARRAY_SIZE(ar9280Modes_9280), 6);
763 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
764 ARRAY_SIZE(ar9280Common_9280), 2);
765 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
766 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
767 ARRAY_SIZE(ar5416Modes_9160), 6);
768 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
769 ARRAY_SIZE(ar5416Common_9160), 2);
770 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
771 ARRAY_SIZE(ar5416Bank0_9160), 2);
772 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
773 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
774 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
775 ARRAY_SIZE(ar5416Bank1_9160), 2);
776 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
777 ARRAY_SIZE(ar5416Bank2_9160), 2);
778 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
779 ARRAY_SIZE(ar5416Bank3_9160), 3);
780 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
781 ARRAY_SIZE(ar5416Bank6_9160), 3);
782 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
783 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
784 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
785 ARRAY_SIZE(ar5416Bank7_9160), 2);
786 if (AR_SREV_9160_11(ah)) {
787 INIT_INI_ARRAY(&ahp->ah_iniAddac,
788 ar5416Addac_91601_1,
789 ARRAY_SIZE(ar5416Addac_91601_1), 2);
790 } else {
791 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
792 ARRAY_SIZE(ar5416Addac_9160), 2);
793 }
794 } else if (AR_SREV_9100_OR_LATER(ah)) {
795 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
796 ARRAY_SIZE(ar5416Modes_9100), 6);
797 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
798 ARRAY_SIZE(ar5416Common_9100), 2);
799 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
800 ARRAY_SIZE(ar5416Bank0_9100), 2);
801 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
802 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
803 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
804 ARRAY_SIZE(ar5416Bank1_9100), 2);
805 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
806 ARRAY_SIZE(ar5416Bank2_9100), 2);
807 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
808 ARRAY_SIZE(ar5416Bank3_9100), 3);
809 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
810 ARRAY_SIZE(ar5416Bank6_9100), 3);
811 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
812 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
813 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
814 ARRAY_SIZE(ar5416Bank7_9100), 2);
815 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
816 ARRAY_SIZE(ar5416Addac_9100), 2);
817 } else {
818 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
819 ARRAY_SIZE(ar5416Modes), 6);
820 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
821 ARRAY_SIZE(ar5416Common), 2);
822 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
823 ARRAY_SIZE(ar5416Bank0), 2);
824 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
825 ARRAY_SIZE(ar5416BB_RfGain), 3);
826 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
827 ARRAY_SIZE(ar5416Bank1), 2);
828 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
829 ARRAY_SIZE(ar5416Bank2), 2);
830 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
831 ARRAY_SIZE(ar5416Bank3), 3);
832 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
833 ARRAY_SIZE(ar5416Bank6), 3);
834 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
835 ARRAY_SIZE(ar5416Bank6TPC), 3);
836 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
837 ARRAY_SIZE(ar5416Bank7), 2);
838 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
839 ARRAY_SIZE(ar5416Addac), 2);
840 }
841
842 if (ah->ah_isPciExpress)
843 ath9k_hw_configpcipowersave(ah, 0);
844 else
845 ath9k_hw_disablepcie(ah);
846
847 ecode = ath9k_hw_post_attach(ah);
848 if (ecode != 0)
849 goto bad;
850
851 /* rxgain table */
852 if (AR_SREV_9280_20_OR_LATER(ah))
853 ath9k_hw_init_rxgain_ini(ah);
854
855 /* txgain table */
856 if (AR_SREV_9280_20_OR_LATER(ah))
857 ath9k_hw_init_txgain_ini(ah);
858
859 #ifndef CONFIG_SLOW_ANT_DIV
860 if (ah->ah_devid == AR9280_DEVID_PCI) {
861 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
862 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
863
864 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
865 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
866
867 INI_RA(&ahp->ah_iniModes, i, j) =
868 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
869 reg, val);
870 }
871 }
872 }
873 #endif
874 if (!ath9k_hw_fill_cap_info(ah)) {
875 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
876 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
877 ecode = -EINVAL;
878 goto bad;
879 }
880
881 ecode = ath9k_hw_init_macaddr(ah);
882 if (ecode != 0) {
883 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
884 "%s: failed initializing mac address\n",
885 __func__);
886 goto bad;
887 }
888
889 if (AR_SREV_9285(ah))
890 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
891 else
892 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
893
894 ath9k_init_nfcal_hist_buffer(ah);
895
896 return ah;
897 bad:
898 if (ahp)
899 ath9k_hw_detach((struct ath_hal *) ahp);
900 if (status)
901 *status = ecode;
902
903 return NULL;
904 }
905
906 static void ath9k_hw_init_bb(struct ath_hal *ah,
907 struct ath9k_channel *chan)
908 {
909 u32 synthDelay;
910
911 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
912 if (IS_CHAN_CCK(chan))
913 synthDelay = (4 * synthDelay) / 22;
914 else
915 synthDelay /= 10;
916
917 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
918
919 udelay(synthDelay + BASE_ACTIVATE_DELAY);
920 }
921
922 static void ath9k_hw_init_qos(struct ath_hal *ah)
923 {
924 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
925 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
926
927 REG_WRITE(ah, AR_QOS_NO_ACK,
928 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
929 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
930 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
931
932 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
933 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
934 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
935 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
936 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
937 }
938
939 static void ath9k_hw_init_pll(struct ath_hal *ah,
940 struct ath9k_channel *chan)
941 {
942 u32 pll;
943
944 if (AR_SREV_9100(ah)) {
945 if (chan && IS_CHAN_5GHZ(chan))
946 pll = 0x1450;
947 else
948 pll = 0x1458;
949 } else {
950 if (AR_SREV_9280_10_OR_LATER(ah)) {
951 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
952
953 if (chan && IS_CHAN_HALF_RATE(chan))
954 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
955 else if (chan && IS_CHAN_QUARTER_RATE(chan))
956 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
957
958 if (chan && IS_CHAN_5GHZ(chan)) {
959 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
960
961
962 if (AR_SREV_9280_20(ah)) {
963 if (((chan->channel % 20) == 0)
964 || ((chan->channel % 10) == 0))
965 pll = 0x2850;
966 else
967 pll = 0x142c;
968 }
969 } else {
970 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
971 }
972
973 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
974
975 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
976
977 if (chan && IS_CHAN_HALF_RATE(chan))
978 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
979 else if (chan && IS_CHAN_QUARTER_RATE(chan))
980 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
981
982 if (chan && IS_CHAN_5GHZ(chan))
983 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
984 else
985 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
986 } else {
987 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
988
989 if (chan && IS_CHAN_HALF_RATE(chan))
990 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
991 else if (chan && IS_CHAN_QUARTER_RATE(chan))
992 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
993
994 if (chan && IS_CHAN_5GHZ(chan))
995 pll |= SM(0xa, AR_RTC_PLL_DIV);
996 else
997 pll |= SM(0xb, AR_RTC_PLL_DIV);
998 }
999 }
1000 REG_WRITE(ah, (u16) (AR_RTC_PLL_CONTROL), pll);
1001
1002 udelay(RTC_PLL_SETTLE_DELAY);
1003
1004 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1005 }
1006
1007 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
1008 {
1009 struct ath_hal_5416 *ahp = AH5416(ah);
1010 int rx_chainmask, tx_chainmask;
1011
1012 rx_chainmask = ahp->ah_rxchainmask;
1013 tx_chainmask = ahp->ah_txchainmask;
1014
1015 switch (rx_chainmask) {
1016 case 0x5:
1017 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1018 AR_PHY_SWAP_ALT_CHAIN);
1019 case 0x3:
1020 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
1021 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1022 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1023 break;
1024 }
1025 case 0x1:
1026 case 0x2:
1027 if (!AR_SREV_9280(ah))
1028 break;
1029 case 0x7:
1030 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1031 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1032 break;
1033 default:
1034 break;
1035 }
1036
1037 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1038 if (tx_chainmask == 0x5) {
1039 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1040 AR_PHY_SWAP_ALT_CHAIN);
1041 }
1042 if (AR_SREV_9100(ah))
1043 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1044 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1045 }
1046
1047 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah, enum ath9k_opmode opmode)
1048 {
1049 struct ath_hal_5416 *ahp = AH5416(ah);
1050
1051 ahp->ah_maskReg = AR_IMR_TXERR |
1052 AR_IMR_TXURN |
1053 AR_IMR_RXERR |
1054 AR_IMR_RXORN |
1055 AR_IMR_BCNMISC;
1056
1057 if (ahp->ah_intrMitigation)
1058 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1059 else
1060 ahp->ah_maskReg |= AR_IMR_RXOK;
1061
1062 ahp->ah_maskReg |= AR_IMR_TXOK;
1063
1064 if (opmode == ATH9K_M_HOSTAP)
1065 ahp->ah_maskReg |= AR_IMR_MIB;
1066
1067 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1068 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1069
1070 if (!AR_SREV_9100(ah)) {
1071 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1072 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1073 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1074 }
1075 }
1076
1077 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1078 {
1079 struct ath_hal_5416 *ahp = AH5416(ah);
1080
1081 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1082 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad ack timeout %u\n",
1083 __func__, us);
1084 ahp->ah_acktimeout = (u32) -1;
1085 return false;
1086 } else {
1087 REG_RMW_FIELD(ah, AR_TIME_OUT,
1088 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1089 ahp->ah_acktimeout = us;
1090 return true;
1091 }
1092 }
1093
1094 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1095 {
1096 struct ath_hal_5416 *ahp = AH5416(ah);
1097
1098 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1099 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad cts timeout %u\n",
1100 __func__, us);
1101 ahp->ah_ctstimeout = (u32) -1;
1102 return false;
1103 } else {
1104 REG_RMW_FIELD(ah, AR_TIME_OUT,
1105 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1106 ahp->ah_ctstimeout = us;
1107 return true;
1108 }
1109 }
1110
1111 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1112 {
1113 struct ath_hal_5416 *ahp = AH5416(ah);
1114
1115 if (tu > 0xFFFF) {
1116 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1117 "%s: bad global tx timeout %u\n", __func__, tu);
1118 ahp->ah_globaltxtimeout = (u32) -1;
1119 return false;
1120 } else {
1121 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1122 ahp->ah_globaltxtimeout = tu;
1123 return true;
1124 }
1125 }
1126
1127 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1128 {
1129 struct ath_hal_5416 *ahp = AH5416(ah);
1130
1131 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
1132 __func__, ahp->ah_miscMode);
1133
1134 if (ahp->ah_miscMode != 0)
1135 REG_WRITE(ah, AR_PCU_MISC,
1136 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1137 if (ahp->ah_slottime != (u32) -1)
1138 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1139 if (ahp->ah_acktimeout != (u32) -1)
1140 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1141 if (ahp->ah_ctstimeout != (u32) -1)
1142 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1143 if (ahp->ah_globaltxtimeout != (u32) -1)
1144 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1145 }
1146
1147 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1148 {
1149 return vendorid == ATHEROS_VENDOR_ID ?
1150 ath9k_hw_devname(devid) : NULL;
1151 }
1152
1153 void ath9k_hw_detach(struct ath_hal *ah)
1154 {
1155 if (!AR_SREV_9100(ah))
1156 ath9k_hw_ani_detach(ah);
1157
1158 ath9k_hw_rfdetach(ah);
1159 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1160 kfree(ah);
1161 }
1162
1163 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1164 void __iomem *mem, int *error)
1165 {
1166 struct ath_hal *ah = NULL;
1167
1168 switch (devid) {
1169 case AR5416_DEVID_PCI:
1170 case AR5416_DEVID_PCIE:
1171 case AR9160_DEVID_PCI:
1172 case AR9280_DEVID_PCI:
1173 case AR9280_DEVID_PCIE:
1174 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1175 break;
1176 default:
1177 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1178 "devid=0x%x not supported.\n", devid);
1179 ah = NULL;
1180 *error = -ENXIO;
1181 break;
1182 }
1183
1184 return ah;
1185 }
1186
1187 /*******/
1188 /* INI */
1189 /*******/
1190
1191 static void ath9k_hw_override_ini(struct ath_hal *ah,
1192 struct ath9k_channel *chan)
1193 {
1194 if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1195 AR_SREV_9280_10_OR_LATER(ah))
1196 return;
1197
1198 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1199 }
1200
1201 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1202 struct ar5416_eeprom *pEepData,
1203 u32 reg, u32 value)
1204 {
1205 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1206
1207 switch (ah->ah_devid) {
1208 case AR9280_DEVID_PCI:
1209 if (reg == 0x7894) {
1210 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1211 "ini VAL: %x EEPROM: %x\n", value,
1212 (pBase->version & 0xff));
1213
1214 if ((pBase->version & 0xff) > 0x0a) {
1215 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1216 "PWDCLKIND: %d\n",
1217 pBase->pwdclkind);
1218 value &= ~AR_AN_TOP2_PWDCLKIND;
1219 value |= AR_AN_TOP2_PWDCLKIND &
1220 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1221 } else {
1222 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1223 "PWDCLKIND Earlier Rev\n");
1224 }
1225
1226 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1227 "final ini VAL: %x\n", value);
1228 }
1229 break;
1230 }
1231
1232 return value;
1233 }
1234
1235 static int ath9k_hw_process_ini(struct ath_hal *ah,
1236 struct ath9k_channel *chan,
1237 enum ath9k_ht_macmode macmode)
1238 {
1239 int i, regWrites = 0;
1240 struct ath_hal_5416 *ahp = AH5416(ah);
1241 u32 modesIndex, freqIndex;
1242 int status;
1243
1244 switch (chan->chanmode) {
1245 case CHANNEL_A:
1246 case CHANNEL_A_HT20:
1247 modesIndex = 1;
1248 freqIndex = 1;
1249 break;
1250 case CHANNEL_A_HT40PLUS:
1251 case CHANNEL_A_HT40MINUS:
1252 modesIndex = 2;
1253 freqIndex = 1;
1254 break;
1255 case CHANNEL_G:
1256 case CHANNEL_G_HT20:
1257 case CHANNEL_B:
1258 modesIndex = 4;
1259 freqIndex = 2;
1260 break;
1261 case CHANNEL_G_HT40PLUS:
1262 case CHANNEL_G_HT40MINUS:
1263 modesIndex = 3;
1264 freqIndex = 2;
1265 break;
1266
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1272
1273 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1274
1275 ath9k_hw_set_addac(ah, chan);
1276
1277 if (AR_SREV_5416_V22_OR_LATER(ah)) {
1278 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1279 } else {
1280 struct ar5416IniArray temp;
1281 u32 addacSize =
1282 sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1283 ahp->ah_iniAddac.ia_columns;
1284
1285 memcpy(ahp->ah_addac5416_21,
1286 ahp->ah_iniAddac.ia_array, addacSize);
1287
1288 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1289
1290 temp.ia_array = ahp->ah_addac5416_21;
1291 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1292 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1293 REG_WRITE_ARRAY(&temp, 1, regWrites);
1294 }
1295
1296 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1297
1298 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1299 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1300 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1301
1302 #ifdef CONFIG_SLOW_ANT_DIV
1303 if (ah->ah_devid == AR9280_DEVID_PCI)
1304 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg, val);
1305 #endif
1306
1307 REG_WRITE(ah, reg, val);
1308
1309 if (reg >= 0x7800 && reg < 0x78a0
1310 && ah->ah_config.analog_shiftreg) {
1311 udelay(100);
1312 }
1313
1314 DO_DELAY(regWrites);
1315 }
1316
1317 if (AR_SREV_9280_20_OR_LATER(ah))
1318 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1319
1320 if (AR_SREV_9280_20_OR_LATER(ah))
1321 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1322
1323 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1324 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1325 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1326
1327 REG_WRITE(ah, reg, val);
1328
1329 if (reg >= 0x7800 && reg < 0x78a0
1330 && ah->ah_config.analog_shiftreg) {
1331 udelay(100);
1332 }
1333
1334 DO_DELAY(regWrites);
1335 }
1336
1337 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1338
1339 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1340 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1341 regWrites);
1342 }
1343
1344 ath9k_hw_override_ini(ah, chan);
1345 ath9k_hw_set_regs(ah, chan, macmode);
1346 ath9k_hw_init_chain_masks(ah);
1347
1348 status = ath9k_hw_set_txpower(ah, chan,
1349 ath9k_regd_get_ctl(ah, chan),
1350 ath9k_regd_get_antenna_allowed(ah,
1351 chan),
1352 chan->maxRegTxPower * 2,
1353 min((u32) MAX_RATE_POWER,
1354 (u32) ah->ah_powerLimit));
1355 if (status != 0) {
1356 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1357 "%s: error init'ing transmit power\n", __func__);
1358 return -EIO;
1359 }
1360
1361 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1362 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1363 "%s: ar5416SetRfRegs failed\n", __func__);
1364 return -EIO;
1365 }
1366
1367 return 0;
1368 }
1369
1370 /****************************************/
1371 /* Reset and Channel Switching Routines */
1372 /****************************************/
1373
1374 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1375 {
1376 u32 rfMode = 0;
1377
1378 if (chan == NULL)
1379 return;
1380
1381 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1382 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1383
1384 if (!AR_SREV_9280_10_OR_LATER(ah))
1385 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1386 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1387
1388 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1389 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1390
1391 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1392 }
1393
1394 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1395 {
1396 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1397 }
1398
1399 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1400 {
1401 u32 regval;
1402
1403 regval = REG_READ(ah, AR_AHB_MODE);
1404 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1405
1406 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1407 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1408
1409 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1410
1411 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1412 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1413
1414 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1415
1416 if (AR_SREV_9285(ah)) {
1417 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1418 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1419 } else {
1420 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1421 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1422 }
1423 }
1424
1425 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1426 {
1427 u32 val;
1428
1429 val = REG_READ(ah, AR_STA_ID1);
1430 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1431 switch (opmode) {
1432 case ATH9K_M_HOSTAP:
1433 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1434 | AR_STA_ID1_KSRCH_MODE);
1435 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1436 break;
1437 case ATH9K_M_IBSS:
1438 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1439 | AR_STA_ID1_KSRCH_MODE);
1440 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1441 break;
1442 case ATH9K_M_STA:
1443 case ATH9K_M_MONITOR:
1444 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1445 break;
1446 }
1447 }
1448
1449 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1450 u32 coef_scaled,
1451 u32 *coef_mantissa,
1452 u32 *coef_exponent)
1453 {
1454 u32 coef_exp, coef_man;
1455
1456 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1457 if ((coef_scaled >> coef_exp) & 0x1)
1458 break;
1459
1460 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1461
1462 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1463
1464 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1465 *coef_exponent = coef_exp - 16;
1466 }
1467
1468 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1469 struct ath9k_channel *chan)
1470 {
1471 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1472 u32 clockMhzScaled = 0x64000000;
1473 struct chan_centers centers;
1474
1475 if (IS_CHAN_HALF_RATE(chan))
1476 clockMhzScaled = clockMhzScaled >> 1;
1477 else if (IS_CHAN_QUARTER_RATE(chan))
1478 clockMhzScaled = clockMhzScaled >> 2;
1479
1480 ath9k_hw_get_channel_centers(ah, chan, &centers);
1481 coef_scaled = clockMhzScaled / centers.synth_center;
1482
1483 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1484 &ds_coef_exp);
1485
1486 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1487 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1488 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1489 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1490
1491 coef_scaled = (9 * coef_scaled) / 10;
1492
1493 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1494 &ds_coef_exp);
1495
1496 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1497 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1498 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1499 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1500 }
1501
1502 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1503 {
1504 u32 rst_flags;
1505 u32 tmpReg;
1506
1507 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1508 AR_RTC_FORCE_WAKE_ON_INT);
1509
1510 if (AR_SREV_9100(ah)) {
1511 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1512 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1513 } else {
1514 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1515 if (tmpReg &
1516 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1517 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1518 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1519 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1520 } else {
1521 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1522 }
1523
1524 rst_flags = AR_RTC_RC_MAC_WARM;
1525 if (type == ATH9K_RESET_COLD)
1526 rst_flags |= AR_RTC_RC_MAC_COLD;
1527 }
1528
1529 REG_WRITE(ah, (u16) (AR_RTC_RC), rst_flags);
1530 udelay(50);
1531
1532 REG_WRITE(ah, (u16) (AR_RTC_RC), 0);
1533 if (!ath9k_hw_wait(ah, (u16) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1534 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1535 "%s: RTC stuck in MAC reset\n",
1536 __func__);
1537 return false;
1538 }
1539
1540 if (!AR_SREV_9100(ah))
1541 REG_WRITE(ah, AR_RC, 0);
1542
1543 ath9k_hw_init_pll(ah, NULL);
1544
1545 if (AR_SREV_9100(ah))
1546 udelay(50);
1547
1548 return true;
1549 }
1550
1551 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1552 {
1553 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1554 AR_RTC_FORCE_WAKE_ON_INT);
1555
1556 REG_WRITE(ah, (u16) (AR_RTC_RESET), 0);
1557 REG_WRITE(ah, (u16) (AR_RTC_RESET), 1);
1558
1559 if (!ath9k_hw_wait(ah,
1560 AR_RTC_STATUS,
1561 AR_RTC_STATUS_M,
1562 AR_RTC_STATUS_ON)) {
1563 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: RTC not waking up\n",
1564 __func__);
1565 return false;
1566 }
1567
1568 ath9k_hw_read_revisions(ah);
1569
1570 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1571 }
1572
1573 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1574 {
1575 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1576 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1577
1578 switch (type) {
1579 case ATH9K_RESET_POWER_ON:
1580 return ath9k_hw_set_reset_power_on(ah);
1581 break;
1582 case ATH9K_RESET_WARM:
1583 case ATH9K_RESET_COLD:
1584 return ath9k_hw_set_reset(ah, type);
1585 break;
1586 default:
1587 return false;
1588 }
1589 }
1590
1591 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1592 enum ath9k_ht_macmode macmode)
1593 {
1594 u32 phymode;
1595 struct ath_hal_5416 *ahp = AH5416(ah);
1596
1597 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1598 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1599
1600 if (IS_CHAN_HT40(chan)) {
1601 phymode |= AR_PHY_FC_DYN2040_EN;
1602
1603 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1604 (chan->chanmode == CHANNEL_G_HT40PLUS))
1605 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1606
1607 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1608 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1609 }
1610 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1611
1612 ath9k_hw_set11nmac2040(ah, macmode);
1613
1614 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1615 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1616 }
1617
1618 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1619 struct ath9k_channel *chan)
1620 {
1621 struct ath_hal_5416 *ahp = AH5416(ah);
1622
1623 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1624 return false;
1625
1626 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1627 return false;
1628
1629 ahp->ah_chipFullSleep = false;
1630
1631 ath9k_hw_init_pll(ah, chan);
1632
1633 ath9k_hw_set_rfmode(ah, chan);
1634
1635 return true;
1636 }
1637
1638 static struct ath9k_channel *ath9k_hw_check_chan(struct ath_hal *ah,
1639 struct ath9k_channel *chan)
1640 {
1641 if (!(IS_CHAN_2GHZ(chan) ^ IS_CHAN_5GHZ(chan))) {
1642 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1643 "%s: invalid channel %u/0x%x; not marked as "
1644 "2GHz or 5GHz\n", __func__, chan->channel,
1645 chan->channelFlags);
1646 return NULL;
1647 }
1648
1649 if (!IS_CHAN_OFDM(chan) &&
1650 !IS_CHAN_CCK(chan) &&
1651 !IS_CHAN_HT20(chan) &&
1652 !IS_CHAN_HT40(chan)) {
1653 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1654 "%s: invalid channel %u/0x%x; not marked as "
1655 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1656 __func__, chan->channel, chan->channelFlags);
1657 return NULL;
1658 }
1659
1660 return ath9k_regd_check_channel(ah, chan);
1661 }
1662
1663 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1664 struct ath9k_channel *chan,
1665 enum ath9k_ht_macmode macmode)
1666 {
1667 u32 synthDelay, qnum;
1668
1669 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1670 if (ath9k_hw_numtxpending(ah, qnum)) {
1671 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1672 "%s: Transmit frames pending on queue %d\n",
1673 __func__, qnum);
1674 return false;
1675 }
1676 }
1677
1678 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1679 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1680 AR_PHY_RFBUS_GRANT_EN)) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_PHY_IO,
1682 "%s: Could not kill baseband RX\n", __func__);
1683 return false;
1684 }
1685
1686 ath9k_hw_set_regs(ah, chan, macmode);
1687
1688 if (AR_SREV_9280_10_OR_LATER(ah)) {
1689 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1690 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1691 "%s: failed to set channel\n", __func__);
1692 return false;
1693 }
1694 } else {
1695 if (!(ath9k_hw_set_channel(ah, chan))) {
1696 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1697 "%s: failed to set channel\n", __func__);
1698 return false;
1699 }
1700 }
1701
1702 if (ath9k_hw_set_txpower(ah, chan,
1703 ath9k_regd_get_ctl(ah, chan),
1704 ath9k_regd_get_antenna_allowed(ah, chan),
1705 chan->maxRegTxPower * 2,
1706 min((u32) MAX_RATE_POWER,
1707 (u32) ah->ah_powerLimit)) != 0) {
1708 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1709 "%s: error init'ing transmit power\n", __func__);
1710 return false;
1711 }
1712
1713 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1714 if (IS_CHAN_CCK(chan))
1715 synthDelay = (4 * synthDelay) / 22;
1716 else
1717 synthDelay /= 10;
1718
1719 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1720
1721 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1722
1723 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1724 ath9k_hw_set_delta_slope(ah, chan);
1725
1726 if (AR_SREV_9280_10_OR_LATER(ah))
1727 ath9k_hw_9280_spur_mitigate(ah, chan);
1728 else
1729 ath9k_hw_spur_mitigate(ah, chan);
1730
1731 if (!chan->oneTimeCalsDone)
1732 chan->oneTimeCalsDone = true;
1733
1734 return true;
1735 }
1736
1737 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1738 {
1739 int bb_spur = AR_NO_SPUR;
1740 int freq;
1741 int bin, cur_bin;
1742 int bb_spur_off, spur_subchannel_sd;
1743 int spur_freq_sd;
1744 int spur_delta_phase;
1745 int denominator;
1746 int upper, lower, cur_vit_mask;
1747 int tmp, newVal;
1748 int i;
1749 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1750 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1751 };
1752 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1753 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1754 };
1755 int inc[4] = { 0, 100, 0, 0 };
1756 struct chan_centers centers;
1757
1758 int8_t mask_m[123];
1759 int8_t mask_p[123];
1760 int8_t mask_amt;
1761 int tmp_mask;
1762 int cur_bb_spur;
1763 bool is2GHz = IS_CHAN_2GHZ(chan);
1764
1765 memset(&mask_m, 0, sizeof(int8_t) * 123);
1766 memset(&mask_p, 0, sizeof(int8_t) * 123);
1767
1768 ath9k_hw_get_channel_centers(ah, chan, &centers);
1769 freq = centers.synth_center;
1770
1771 ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1772 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1773 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1774
1775 if (is2GHz)
1776 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1777 else
1778 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1779
1780 if (AR_NO_SPUR == cur_bb_spur)
1781 break;
1782 cur_bb_spur = cur_bb_spur - freq;
1783
1784 if (IS_CHAN_HT40(chan)) {
1785 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1786 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1787 bb_spur = cur_bb_spur;
1788 break;
1789 }
1790 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1791 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1792 bb_spur = cur_bb_spur;
1793 break;
1794 }
1795 }
1796
1797 if (AR_NO_SPUR == bb_spur) {
1798 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1799 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1800 return;
1801 } else {
1802 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1803 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1804 }
1805
1806 bin = bb_spur * 320;
1807
1808 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1809
1810 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1811 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1812 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1813 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1814 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1815
1816 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1817 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1818 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1819 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1820 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1821 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1822
1823 if (IS_CHAN_HT40(chan)) {
1824 if (bb_spur < 0) {
1825 spur_subchannel_sd = 1;
1826 bb_spur_off = bb_spur + 10;
1827 } else {
1828 spur_subchannel_sd = 0;
1829 bb_spur_off = bb_spur - 10;
1830 }
1831 } else {
1832 spur_subchannel_sd = 0;
1833 bb_spur_off = bb_spur;
1834 }
1835
1836 if (IS_CHAN_HT40(chan))
1837 spur_delta_phase =
1838 ((bb_spur * 262144) /
1839 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1840 else
1841 spur_delta_phase =
1842 ((bb_spur * 524288) /
1843 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1844
1845 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1846 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1847
1848 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1849 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1850 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1851 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1852
1853 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1854 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1855
1856 cur_bin = -6000;
1857 upper = bin + 100;
1858 lower = bin - 100;
1859
1860 for (i = 0; i < 4; i++) {
1861 int pilot_mask = 0;
1862 int chan_mask = 0;
1863 int bp = 0;
1864 for (bp = 0; bp < 30; bp++) {
1865 if ((cur_bin > lower) && (cur_bin < upper)) {
1866 pilot_mask = pilot_mask | 0x1 << bp;
1867 chan_mask = chan_mask | 0x1 << bp;
1868 }
1869 cur_bin += 100;
1870 }
1871 cur_bin += inc[i];
1872 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1873 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1874 }
1875
1876 cur_vit_mask = 6100;
1877 upper = bin + 120;
1878 lower = bin - 120;
1879
1880 for (i = 0; i < 123; i++) {
1881 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1882
1883 /* workaround for gcc bug #37014 */
1884 volatile int tmp = abs(cur_vit_mask - bin);
1885
1886 if (tmp < 75)
1887 mask_amt = 1;
1888 else
1889 mask_amt = 0;
1890 if (cur_vit_mask < 0)
1891 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1892 else
1893 mask_p[cur_vit_mask / 100] = mask_amt;
1894 }
1895 cur_vit_mask -= 100;
1896 }
1897
1898 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1899 | (mask_m[48] << 26) | (mask_m[49] << 24)
1900 | (mask_m[50] << 22) | (mask_m[51] << 20)
1901 | (mask_m[52] << 18) | (mask_m[53] << 16)
1902 | (mask_m[54] << 14) | (mask_m[55] << 12)
1903 | (mask_m[56] << 10) | (mask_m[57] << 8)
1904 | (mask_m[58] << 6) | (mask_m[59] << 4)
1905 | (mask_m[60] << 2) | (mask_m[61] << 0);
1906 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1907 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1908
1909 tmp_mask = (mask_m[31] << 28)
1910 | (mask_m[32] << 26) | (mask_m[33] << 24)
1911 | (mask_m[34] << 22) | (mask_m[35] << 20)
1912 | (mask_m[36] << 18) | (mask_m[37] << 16)
1913 | (mask_m[48] << 14) | (mask_m[39] << 12)
1914 | (mask_m[40] << 10) | (mask_m[41] << 8)
1915 | (mask_m[42] << 6) | (mask_m[43] << 4)
1916 | (mask_m[44] << 2) | (mask_m[45] << 0);
1917 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1918 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1919
1920 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1921 | (mask_m[18] << 26) | (mask_m[18] << 24)
1922 | (mask_m[20] << 22) | (mask_m[20] << 20)
1923 | (mask_m[22] << 18) | (mask_m[22] << 16)
1924 | (mask_m[24] << 14) | (mask_m[24] << 12)
1925 | (mask_m[25] << 10) | (mask_m[26] << 8)
1926 | (mask_m[27] << 6) | (mask_m[28] << 4)
1927 | (mask_m[29] << 2) | (mask_m[30] << 0);
1928 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1929 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1930
1931 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1932 | (mask_m[2] << 26) | (mask_m[3] << 24)
1933 | (mask_m[4] << 22) | (mask_m[5] << 20)
1934 | (mask_m[6] << 18) | (mask_m[7] << 16)
1935 | (mask_m[8] << 14) | (mask_m[9] << 12)
1936 | (mask_m[10] << 10) | (mask_m[11] << 8)
1937 | (mask_m[12] << 6) | (mask_m[13] << 4)
1938 | (mask_m[14] << 2) | (mask_m[15] << 0);
1939 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1940 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1941
1942 tmp_mask = (mask_p[15] << 28)
1943 | (mask_p[14] << 26) | (mask_p[13] << 24)
1944 | (mask_p[12] << 22) | (mask_p[11] << 20)
1945 | (mask_p[10] << 18) | (mask_p[9] << 16)
1946 | (mask_p[8] << 14) | (mask_p[7] << 12)
1947 | (mask_p[6] << 10) | (mask_p[5] << 8)
1948 | (mask_p[4] << 6) | (mask_p[3] << 4)
1949 | (mask_p[2] << 2) | (mask_p[1] << 0);
1950 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1951 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1952
1953 tmp_mask = (mask_p[30] << 28)
1954 | (mask_p[29] << 26) | (mask_p[28] << 24)
1955 | (mask_p[27] << 22) | (mask_p[26] << 20)
1956 | (mask_p[25] << 18) | (mask_p[24] << 16)
1957 | (mask_p[23] << 14) | (mask_p[22] << 12)
1958 | (mask_p[21] << 10) | (mask_p[20] << 8)
1959 | (mask_p[19] << 6) | (mask_p[18] << 4)
1960 | (mask_p[17] << 2) | (mask_p[16] << 0);
1961 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1962 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1963
1964 tmp_mask = (mask_p[45] << 28)
1965 | (mask_p[44] << 26) | (mask_p[43] << 24)
1966 | (mask_p[42] << 22) | (mask_p[41] << 20)
1967 | (mask_p[40] << 18) | (mask_p[39] << 16)
1968 | (mask_p[38] << 14) | (mask_p[37] << 12)
1969 | (mask_p[36] << 10) | (mask_p[35] << 8)
1970 | (mask_p[34] << 6) | (mask_p[33] << 4)
1971 | (mask_p[32] << 2) | (mask_p[31] << 0);
1972 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1973 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1974
1975 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1976 | (mask_p[59] << 26) | (mask_p[58] << 24)
1977 | (mask_p[57] << 22) | (mask_p[56] << 20)
1978 | (mask_p[55] << 18) | (mask_p[54] << 16)
1979 | (mask_p[53] << 14) | (mask_p[52] << 12)
1980 | (mask_p[51] << 10) | (mask_p[50] << 8)
1981 | (mask_p[49] << 6) | (mask_p[48] << 4)
1982 | (mask_p[47] << 2) | (mask_p[46] << 0);
1983 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1984 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1985 }
1986
1987 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1988 {
1989 int bb_spur = AR_NO_SPUR;
1990 int bin, cur_bin;
1991 int spur_freq_sd;
1992 int spur_delta_phase;
1993 int denominator;
1994 int upper, lower, cur_vit_mask;
1995 int tmp, new;
1996 int i;
1997 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1998 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1999 };
2000 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2001 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2002 };
2003 int inc[4] = { 0, 100, 0, 0 };
2004
2005 int8_t mask_m[123];
2006 int8_t mask_p[123];
2007 int8_t mask_amt;
2008 int tmp_mask;
2009 int cur_bb_spur;
2010 bool is2GHz = IS_CHAN_2GHZ(chan);
2011
2012 memset(&mask_m, 0, sizeof(int8_t) * 123);
2013 memset(&mask_p, 0, sizeof(int8_t) * 123);
2014
2015 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2016 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
2017 if (AR_NO_SPUR == cur_bb_spur)
2018 break;
2019 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2020 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2021 bb_spur = cur_bb_spur;
2022 break;
2023 }
2024 }
2025
2026 if (AR_NO_SPUR == bb_spur)
2027 return;
2028
2029 bin = bb_spur * 32;
2030
2031 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2032 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2033 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2034 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2035 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2036
2037 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2038
2039 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2040 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2041 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2042 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2043 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2044 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2045
2046 spur_delta_phase = ((bb_spur * 524288) / 100) &
2047 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2048
2049 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2050 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2051
2052 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2053 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2054 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2055 REG_WRITE(ah, AR_PHY_TIMING11, new);
2056
2057 cur_bin = -6000;
2058 upper = bin + 100;
2059 lower = bin - 100;
2060
2061 for (i = 0; i < 4; i++) {
2062 int pilot_mask = 0;
2063 int chan_mask = 0;
2064 int bp = 0;
2065 for (bp = 0; bp < 30; bp++) {
2066 if ((cur_bin > lower) && (cur_bin < upper)) {
2067 pilot_mask = pilot_mask | 0x1 << bp;
2068 chan_mask = chan_mask | 0x1 << bp;
2069 }
2070 cur_bin += 100;
2071 }
2072 cur_bin += inc[i];
2073 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2074 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2075 }
2076
2077 cur_vit_mask = 6100;
2078 upper = bin + 120;
2079 lower = bin - 120;
2080
2081 for (i = 0; i < 123; i++) {
2082 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2083
2084 /* workaround for gcc bug #37014 */
2085 volatile int tmp = abs(cur_vit_mask - bin);
2086
2087 if (tmp < 75)
2088 mask_amt = 1;
2089 else
2090 mask_amt = 0;
2091 if (cur_vit_mask < 0)
2092 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2093 else
2094 mask_p[cur_vit_mask / 100] = mask_amt;
2095 }
2096 cur_vit_mask -= 100;
2097 }
2098
2099 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2100 | (mask_m[48] << 26) | (mask_m[49] << 24)
2101 | (mask_m[50] << 22) | (mask_m[51] << 20)
2102 | (mask_m[52] << 18) | (mask_m[53] << 16)
2103 | (mask_m[54] << 14) | (mask_m[55] << 12)
2104 | (mask_m[56] << 10) | (mask_m[57] << 8)
2105 | (mask_m[58] << 6) | (mask_m[59] << 4)
2106 | (mask_m[60] << 2) | (mask_m[61] << 0);
2107 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2108 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2109
2110 tmp_mask = (mask_m[31] << 28)
2111 | (mask_m[32] << 26) | (mask_m[33] << 24)
2112 | (mask_m[34] << 22) | (mask_m[35] << 20)
2113 | (mask_m[36] << 18) | (mask_m[37] << 16)
2114 | (mask_m[48] << 14) | (mask_m[39] << 12)
2115 | (mask_m[40] << 10) | (mask_m[41] << 8)
2116 | (mask_m[42] << 6) | (mask_m[43] << 4)
2117 | (mask_m[44] << 2) | (mask_m[45] << 0);
2118 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2119 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2120
2121 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2122 | (mask_m[18] << 26) | (mask_m[18] << 24)
2123 | (mask_m[20] << 22) | (mask_m[20] << 20)
2124 | (mask_m[22] << 18) | (mask_m[22] << 16)
2125 | (mask_m[24] << 14) | (mask_m[24] << 12)
2126 | (mask_m[25] << 10) | (mask_m[26] << 8)
2127 | (mask_m[27] << 6) | (mask_m[28] << 4)
2128 | (mask_m[29] << 2) | (mask_m[30] << 0);
2129 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2130 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2131
2132 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2133 | (mask_m[2] << 26) | (mask_m[3] << 24)
2134 | (mask_m[4] << 22) | (mask_m[5] << 20)
2135 | (mask_m[6] << 18) | (mask_m[7] << 16)
2136 | (mask_m[8] << 14) | (mask_m[9] << 12)
2137 | (mask_m[10] << 10) | (mask_m[11] << 8)
2138 | (mask_m[12] << 6) | (mask_m[13] << 4)
2139 | (mask_m[14] << 2) | (mask_m[15] << 0);
2140 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2141 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2142
2143 tmp_mask = (mask_p[15] << 28)
2144 | (mask_p[14] << 26) | (mask_p[13] << 24)
2145 | (mask_p[12] << 22) | (mask_p[11] << 20)
2146 | (mask_p[10] << 18) | (mask_p[9] << 16)
2147 | (mask_p[8] << 14) | (mask_p[7] << 12)
2148 | (mask_p[6] << 10) | (mask_p[5] << 8)
2149 | (mask_p[4] << 6) | (mask_p[3] << 4)
2150 | (mask_p[2] << 2) | (mask_p[1] << 0);
2151 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2152 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2153
2154 tmp_mask = (mask_p[30] << 28)
2155 | (mask_p[29] << 26) | (mask_p[28] << 24)
2156 | (mask_p[27] << 22) | (mask_p[26] << 20)
2157 | (mask_p[25] << 18) | (mask_p[24] << 16)
2158 | (mask_p[23] << 14) | (mask_p[22] << 12)
2159 | (mask_p[21] << 10) | (mask_p[20] << 8)
2160 | (mask_p[19] << 6) | (mask_p[18] << 4)
2161 | (mask_p[17] << 2) | (mask_p[16] << 0);
2162 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2163 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2164
2165 tmp_mask = (mask_p[45] << 28)
2166 | (mask_p[44] << 26) | (mask_p[43] << 24)
2167 | (mask_p[42] << 22) | (mask_p[41] << 20)
2168 | (mask_p[40] << 18) | (mask_p[39] << 16)
2169 | (mask_p[38] << 14) | (mask_p[37] << 12)
2170 | (mask_p[36] << 10) | (mask_p[35] << 8)
2171 | (mask_p[34] << 6) | (mask_p[33] << 4)
2172 | (mask_p[32] << 2) | (mask_p[31] << 0);
2173 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2174 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2175
2176 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2177 | (mask_p[59] << 26) | (mask_p[58] << 24)
2178 | (mask_p[57] << 22) | (mask_p[56] << 20)
2179 | (mask_p[55] << 18) | (mask_p[54] << 16)
2180 | (mask_p[53] << 14) | (mask_p[52] << 12)
2181 | (mask_p[51] << 10) | (mask_p[50] << 8)
2182 | (mask_p[49] << 6) | (mask_p[48] << 4)
2183 | (mask_p[47] << 2) | (mask_p[46] << 0);
2184 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2185 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2186 }
2187
2188 bool ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2189 enum ath9k_ht_macmode macmode,
2190 u8 txchainmask, u8 rxchainmask,
2191 enum ath9k_ht_extprotspacing extprotspacing,
2192 bool bChannelChange, int *status)
2193 {
2194 u32 saveLedState;
2195 struct ath_hal_5416 *ahp = AH5416(ah);
2196 struct ath9k_channel *curchan = ah->ah_curchan;
2197 u32 saveDefAntenna;
2198 u32 macStaId1;
2199 int ecode;
2200 int i, rx_chainmask;
2201
2202 ahp->ah_extprotspacing = extprotspacing;
2203 ahp->ah_txchainmask = txchainmask;
2204 ahp->ah_rxchainmask = rxchainmask;
2205
2206 if (AR_SREV_9280(ah)) {
2207 ahp->ah_txchainmask &= 0x3;
2208 ahp->ah_rxchainmask &= 0x3;
2209 }
2210
2211 if (ath9k_hw_check_chan(ah, chan) == NULL) {
2212 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
2213 "%s: invalid channel %u/0x%x; no mapping\n",
2214 __func__, chan->channel, chan->channelFlags);
2215 ecode = -EINVAL;
2216 goto bad;
2217 }
2218
2219 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
2220 ecode = -EIO;
2221 goto bad;
2222 }
2223
2224 if (curchan)
2225 ath9k_hw_getnf(ah, curchan);
2226
2227 if (bChannelChange &&
2228 (ahp->ah_chipFullSleep != true) &&
2229 (ah->ah_curchan != NULL) &&
2230 (chan->channel != ah->ah_curchan->channel) &&
2231 ((chan->channelFlags & CHANNEL_ALL) ==
2232 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2233 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2234 !IS_CHAN_A_5MHZ_SPACED(ah->
2235 ah_curchan)))) {
2236
2237 if (ath9k_hw_channel_change(ah, chan, macmode)) {
2238 ath9k_hw_loadnf(ah, ah->ah_curchan);
2239 ath9k_hw_start_nfcal(ah);
2240 return true;
2241 }
2242 }
2243
2244 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2245 if (saveDefAntenna == 0)
2246 saveDefAntenna = 1;
2247
2248 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2249
2250 saveLedState = REG_READ(ah, AR_CFG_LED) &
2251 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2252 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2253
2254 ath9k_hw_mark_phy_inactive(ah);
2255
2256 if (!ath9k_hw_chip_reset(ah, chan)) {
2257 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: chip reset failed\n",
2258 __func__);
2259 ecode = -EINVAL;
2260 goto bad;
2261 }
2262
2263 if (AR_SREV_9280(ah)) {
2264 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2265 AR_GPIO_JTAG_DISABLE);
2266
2267 if (test_bit(ATH9K_MODE_11A, ah->ah_caps.wireless_modes)) {
2268 if (IS_CHAN_5GHZ(chan))
2269 ath9k_hw_set_gpio(ah, 9, 0);
2270 else
2271 ath9k_hw_set_gpio(ah, 9, 1);
2272 }
2273 ath9k_hw_cfg_output(ah, 9, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2274 }
2275
2276 ecode = ath9k_hw_process_ini(ah, chan, macmode);
2277 if (ecode != 0) {
2278 ecode = -EINVAL;
2279 goto bad;
2280 }
2281
2282 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2283 ath9k_hw_set_delta_slope(ah, chan);
2284
2285 if (AR_SREV_9280_10_OR_LATER(ah))
2286 ath9k_hw_9280_spur_mitigate(ah, chan);
2287 else
2288 ath9k_hw_spur_mitigate(ah, chan);
2289
2290 if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2291 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2292 "%s: error setting board options\n", __func__);
2293 ecode = -EIO;
2294 goto bad;
2295 }
2296
2297 ath9k_hw_decrease_chain_power(ah, chan);
2298
2299 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ahp->ah_macaddr));
2300 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ahp->ah_macaddr + 4)
2301 | macStaId1
2302 | AR_STA_ID1_RTS_USE_DEF
2303 | (ah->ah_config.
2304 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2305 | ahp->ah_staId1Defaults);
2306 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2307
2308 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
2309 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
2310
2311 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2312
2313 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
2314 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
2315 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
2316
2317 REG_WRITE(ah, AR_ISR, ~0);
2318
2319 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2320
2321 if (AR_SREV_9280_10_OR_LATER(ah)) {
2322 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
2323 ecode = -EIO;
2324 goto bad;
2325 }
2326 } else {
2327 if (!(ath9k_hw_set_channel(ah, chan))) {
2328 ecode = -EIO;
2329 goto bad;
2330 }
2331 }
2332
2333 for (i = 0; i < AR_NUM_DCU; i++)
2334 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2335
2336 ahp->ah_intrTxqs = 0;
2337 for (i = 0; i < ah->ah_caps.total_queues; i++)
2338 ath9k_hw_resettxqueue(ah, i);
2339
2340 ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2341 ath9k_hw_init_qos(ah);
2342
2343 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2344 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2345 ath9k_enable_rfkill(ah);
2346 #endif
2347 ath9k_hw_init_user_settings(ah);
2348
2349 REG_WRITE(ah, AR_STA_ID1,
2350 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2351
2352 ath9k_hw_set_dma(ah);
2353
2354 REG_WRITE(ah, AR_OBS, 8);
2355
2356 if (ahp->ah_intrMitigation) {
2357
2358 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2359 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2360 }
2361
2362 ath9k_hw_init_bb(ah, chan);
2363
2364 if (!ath9k_hw_init_cal(ah, chan)){
2365 ecode = -EIO;;
2366 goto bad;
2367 }
2368
2369 rx_chainmask = ahp->ah_rxchainmask;
2370 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2371 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2372 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2373 }
2374
2375 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2376
2377 if (AR_SREV_9100(ah)) {
2378 u32 mask;
2379 mask = REG_READ(ah, AR_CFG);
2380 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2381 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2382 "%s CFG Byte Swap Set 0x%x\n", __func__,
2383 mask);
2384 } else {
2385 mask =
2386 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2387 REG_WRITE(ah, AR_CFG, mask);
2388 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2389 "%s Setting CFG 0x%x\n", __func__,
2390 REG_READ(ah, AR_CFG));
2391 }
2392 } else {
2393 #ifdef __BIG_ENDIAN
2394 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2395 #endif
2396 }
2397
2398 return true;
2399 bad:
2400 if (status)
2401 *status = ecode;
2402 return false;
2403 }
2404
2405 /************************/
2406 /* Key Cache Management */
2407 /************************/
2408
2409 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2410 {
2411 u32 keyType;
2412
2413 if (entry >= ah->ah_caps.keycache_size) {
2414 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2415 "%s: entry %u out of range\n", __func__, entry);
2416 return false;
2417 }
2418
2419 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2420
2421 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2422 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2423 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2424 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2425 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2426 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2427 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2428 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2429
2430 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2431 u16 micentry = entry + 64;
2432
2433 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2434 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2435 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2436 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2437
2438 }
2439
2440 if (ah->ah_curchan == NULL)
2441 return true;
2442
2443 return true;
2444 }
2445
2446 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2447 {
2448 u32 macHi, macLo;
2449
2450 if (entry >= ah->ah_caps.keycache_size) {
2451 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2452 "%s: entry %u out of range\n", __func__, entry);
2453 return false;
2454 }
2455
2456 if (mac != NULL) {
2457 macHi = (mac[5] << 8) | mac[4];
2458 macLo = (mac[3] << 24) |
2459 (mac[2] << 16) |
2460 (mac[1] << 8) |
2461 mac[0];
2462 macLo >>= 1;
2463 macLo |= (macHi & 1) << 31;
2464 macHi >>= 1;
2465 } else {
2466 macLo = macHi = 0;
2467 }
2468 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2469 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2470
2471 return true;
2472 }
2473
2474 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2475 const struct ath9k_keyval *k,
2476 const u8 *mac, int xorKey)
2477 {
2478 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2479 u32 key0, key1, key2, key3, key4;
2480 u32 keyType;
2481 u32 xorMask = xorKey ?
2482 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2483 | ATH9K_KEY_XOR) : 0;
2484 struct ath_hal_5416 *ahp = AH5416(ah);
2485
2486 if (entry >= pCap->keycache_size) {
2487 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2488 "%s: entry %u out of range\n", __func__, entry);
2489 return false;
2490 }
2491
2492 switch (k->kv_type) {
2493 case ATH9K_CIPHER_AES_OCB:
2494 keyType = AR_KEYTABLE_TYPE_AES;
2495 break;
2496 case ATH9K_CIPHER_AES_CCM:
2497 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2498 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2499 "%s: AES-CCM not supported by "
2500 "mac rev 0x%x\n", __func__,
2501 ah->ah_macRev);
2502 return false;
2503 }
2504 keyType = AR_KEYTABLE_TYPE_CCM;
2505 break;
2506 case ATH9K_CIPHER_TKIP:
2507 keyType = AR_KEYTABLE_TYPE_TKIP;
2508 if (ATH9K_IS_MIC_ENABLED(ah)
2509 && entry + 64 >= pCap->keycache_size) {
2510 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2511 "%s: entry %u inappropriate for TKIP\n",
2512 __func__, entry);
2513 return false;
2514 }
2515 break;
2516 case ATH9K_CIPHER_WEP:
2517 if (k->kv_len < LEN_WEP40) {
2518 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2519 "%s: WEP key length %u too small\n",
2520 __func__, k->kv_len);
2521 return false;
2522 }
2523 if (k->kv_len <= LEN_WEP40)
2524 keyType = AR_KEYTABLE_TYPE_40;
2525 else if (k->kv_len <= LEN_WEP104)
2526 keyType = AR_KEYTABLE_TYPE_104;
2527 else
2528 keyType = AR_KEYTABLE_TYPE_128;
2529 break;
2530 case ATH9K_CIPHER_CLR:
2531 keyType = AR_KEYTABLE_TYPE_CLR;
2532 break;
2533 default:
2534 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2535 "%s: cipher %u not supported\n", __func__,
2536 k->kv_type);
2537 return false;
2538 }
2539
2540 key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2541 key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2542 key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2543 key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2544 key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2545 if (k->kv_len <= LEN_WEP104)
2546 key4 &= 0xff;
2547
2548 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2549 u16 micentry = entry + 64;
2550
2551 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2552 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2553 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2554 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2555 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2556 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2557 (void) ath9k_hw_keysetmac(ah, entry, mac);
2558
2559 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2560 u32 mic0, mic1, mic2, mic3, mic4;
2561
2562 mic0 = get_unaligned_le32(k->kv_mic + 0);
2563 mic2 = get_unaligned_le32(k->kv_mic + 4);
2564 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2565 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2566 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2567 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2568 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2569 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2571 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2572 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2573 AR_KEYTABLE_TYPE_CLR);
2574
2575 } else {
2576 u32 mic0, mic2;
2577
2578 mic0 = get_unaligned_le32(k->kv_mic + 0);
2579 mic2 = get_unaligned_le32(k->kv_mic + 4);
2580 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2581 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2582 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2585 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2586 AR_KEYTABLE_TYPE_CLR);
2587 }
2588 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2589 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2590 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2591 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2592 } else {
2593 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2594 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2595 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2596 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2597 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2598 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2599
2600 (void) ath9k_hw_keysetmac(ah, entry, mac);
2601 }
2602
2603 if (ah->ah_curchan == NULL)
2604 return true;
2605
2606 return true;
2607 }
2608
2609 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2610 {
2611 if (entry < ah->ah_caps.keycache_size) {
2612 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2613 if (val & AR_KEYTABLE_VALID)
2614 return true;
2615 }
2616 return false;
2617 }
2618
2619 /******************************/
2620 /* Power Management (Chipset) */
2621 /******************************/
2622
2623 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2624 {
2625 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2626 if (setChip) {
2627 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2628 AR_RTC_FORCE_WAKE_EN);
2629 if (!AR_SREV_9100(ah))
2630 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2631
2632 REG_CLR_BIT(ah, (u16) (AR_RTC_RESET),
2633 AR_RTC_RESET_EN);
2634 }
2635 }
2636
2637 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2638 {
2639 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2640 if (setChip) {
2641 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2642
2643 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2644 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2645 AR_RTC_FORCE_WAKE_ON_INT);
2646 } else {
2647 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2648 AR_RTC_FORCE_WAKE_EN);
2649 }
2650 }
2651 }
2652
2653 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2654 int setChip)
2655 {
2656 u32 val;
2657 int i;
2658
2659 if (setChip) {
2660 if ((REG_READ(ah, AR_RTC_STATUS) &
2661 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2662 if (ath9k_hw_set_reset_reg(ah,
2663 ATH9K_RESET_POWER_ON) != true) {
2664 return false;
2665 }
2666 }
2667 if (AR_SREV_9100(ah))
2668 REG_SET_BIT(ah, AR_RTC_RESET,
2669 AR_RTC_RESET_EN);
2670
2671 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2672 AR_RTC_FORCE_WAKE_EN);
2673 udelay(50);
2674
2675 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2676 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2677 if (val == AR_RTC_STATUS_ON)
2678 break;
2679 udelay(50);
2680 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2681 AR_RTC_FORCE_WAKE_EN);
2682 }
2683 if (i == 0) {
2684 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2685 "%s: Failed to wakeup in %uus\n",
2686 __func__, POWER_UP_TIME / 20);
2687 return false;
2688 }
2689 }
2690
2691 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2692
2693 return true;
2694 }
2695
2696 bool ath9k_hw_setpower(struct ath_hal *ah,
2697 enum ath9k_power_mode mode)
2698 {
2699 struct ath_hal_5416 *ahp = AH5416(ah);
2700 static const char *modes[] = {
2701 "AWAKE",
2702 "FULL-SLEEP",
2703 "NETWORK SLEEP",
2704 "UNDEFINED"
2705 };
2706 int status = true, setChip = true;
2707
2708 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
2709 modes[ahp->ah_powerMode], modes[mode],
2710 setChip ? "set chip " : "");
2711
2712 switch (mode) {
2713 case ATH9K_PM_AWAKE:
2714 status = ath9k_hw_set_power_awake(ah, setChip);
2715 break;
2716 case ATH9K_PM_FULL_SLEEP:
2717 ath9k_set_power_sleep(ah, setChip);
2718 ahp->ah_chipFullSleep = true;
2719 break;
2720 case ATH9K_PM_NETWORK_SLEEP:
2721 ath9k_set_power_network_sleep(ah, setChip);
2722 break;
2723 default:
2724 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2725 "%s: unknown power mode %u\n", __func__, mode);
2726 return false;
2727 }
2728 ahp->ah_powerMode = mode;
2729
2730 return status;
2731 }
2732
2733 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2734 {
2735 struct ath_hal_5416 *ahp = AH5416(ah);
2736 u8 i;
2737
2738 if (ah->ah_isPciExpress != true)
2739 return;
2740
2741 if (ah->ah_config.pcie_powersave_enable == 2)
2742 return;
2743
2744 if (restore)
2745 return;
2746
2747 if (AR_SREV_9280_20_OR_LATER(ah)) {
2748 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2749 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2750 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2751 }
2752 udelay(1000);
2753 } else if (AR_SREV_9280(ah) &&
2754 (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
2755 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2756 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2757
2758 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2759 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2760 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2761
2762 if (ah->ah_config.pcie_clock_req)
2763 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2764 else
2765 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2766
2767 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2768 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2769 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2770
2771 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2772
2773 udelay(1000);
2774 } else {
2775 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2776 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2777 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2778 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2779 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2780 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2781 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2782 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2783 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2784 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2785 }
2786
2787 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2788
2789 if (ah->ah_config.pcie_waen) {
2790 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2791 } else {
2792 if (AR_SREV_9280(ah))
2793 REG_WRITE(ah, AR_WA, 0x0040073f);
2794 else
2795 REG_WRITE(ah, AR_WA, 0x0000073f);
2796 }
2797 }
2798
2799 /**********************/
2800 /* Interrupt Handling */
2801 /**********************/
2802
2803 bool ath9k_hw_intrpend(struct ath_hal *ah)
2804 {
2805 u32 host_isr;
2806
2807 if (AR_SREV_9100(ah))
2808 return true;
2809
2810 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2811 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2812 return true;
2813
2814 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2815 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2816 && (host_isr != AR_INTR_SPURIOUS))
2817 return true;
2818
2819 return false;
2820 }
2821
2822 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2823 {
2824 u32 isr = 0;
2825 u32 mask2 = 0;
2826 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2827 u32 sync_cause = 0;
2828 bool fatal_int = false;
2829 struct ath_hal_5416 *ahp = AH5416(ah);
2830
2831 if (!AR_SREV_9100(ah)) {
2832 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2833 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2834 == AR_RTC_STATUS_ON) {
2835 isr = REG_READ(ah, AR_ISR);
2836 }
2837 }
2838
2839 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2840 AR_INTR_SYNC_DEFAULT;
2841
2842 *masked = 0;
2843
2844 if (!isr && !sync_cause)
2845 return false;
2846 } else {
2847 *masked = 0;
2848 isr = REG_READ(ah, AR_ISR);
2849 }
2850
2851 if (isr) {
2852 if (isr & AR_ISR_BCNMISC) {
2853 u32 isr2;
2854 isr2 = REG_READ(ah, AR_ISR_S2);
2855 if (isr2 & AR_ISR_S2_TIM)
2856 mask2 |= ATH9K_INT_TIM;
2857 if (isr2 & AR_ISR_S2_DTIM)
2858 mask2 |= ATH9K_INT_DTIM;
2859 if (isr2 & AR_ISR_S2_DTIMSYNC)
2860 mask2 |= ATH9K_INT_DTIMSYNC;
2861 if (isr2 & (AR_ISR_S2_CABEND))
2862 mask2 |= ATH9K_INT_CABEND;
2863 if (isr2 & AR_ISR_S2_GTT)
2864 mask2 |= ATH9K_INT_GTT;
2865 if (isr2 & AR_ISR_S2_CST)
2866 mask2 |= ATH9K_INT_CST;
2867 }
2868
2869 isr = REG_READ(ah, AR_ISR_RAC);
2870 if (isr == 0xffffffff) {
2871 *masked = 0;
2872 return false;
2873 }
2874
2875 *masked = isr & ATH9K_INT_COMMON;
2876
2877 if (ahp->ah_intrMitigation) {
2878 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2879 *masked |= ATH9K_INT_RX;
2880 }
2881
2882 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2883 *masked |= ATH9K_INT_RX;
2884 if (isr &
2885 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2886 AR_ISR_TXEOL)) {
2887 u32 s0_s, s1_s;
2888
2889 *masked |= ATH9K_INT_TX;
2890
2891 s0_s = REG_READ(ah, AR_ISR_S0_S);
2892 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2893 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2894
2895 s1_s = REG_READ(ah, AR_ISR_S1_S);
2896 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2897 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2898 }
2899
2900 if (isr & AR_ISR_RXORN) {
2901 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2902 "%s: receive FIFO overrun interrupt\n",
2903 __func__);
2904 }
2905
2906 if (!AR_SREV_9100(ah)) {
2907 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2908 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2909 if (isr5 & AR_ISR_S5_TIM_TIMER)
2910 *masked |= ATH9K_INT_TIM_TIMER;
2911 }
2912 }
2913
2914 *masked |= mask2;
2915 }
2916
2917 if (AR_SREV_9100(ah))
2918 return true;
2919
2920 if (sync_cause) {
2921 fatal_int =
2922 (sync_cause &
2923 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2924 ? true : false;
2925
2926 if (fatal_int) {
2927 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2928 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2929 "%s: received PCI FATAL interrupt\n",
2930 __func__);
2931 }
2932 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2933 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2934 "%s: received PCI PERR interrupt\n",
2935 __func__);
2936 }
2937 }
2938 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2939 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2940 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
2941 __func__);
2942 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2943 REG_WRITE(ah, AR_RC, 0);
2944 *masked |= ATH9K_INT_FATAL;
2945 }
2946 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2947 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2948 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
2949 __func__);
2950 }
2951
2952 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2953 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2954 }
2955
2956 return true;
2957 }
2958
2959 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2960 {
2961 return AH5416(ah)->ah_maskReg;
2962 }
2963
2964 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2965 {
2966 struct ath_hal_5416 *ahp = AH5416(ah);
2967 u32 omask = ahp->ah_maskReg;
2968 u32 mask, mask2;
2969 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2970
2971 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
2972 omask, ints);
2973
2974 if (omask & ATH9K_INT_GLOBAL) {
2975 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: disable IER\n",
2976 __func__);
2977 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2978 (void) REG_READ(ah, AR_IER);
2979 if (!AR_SREV_9100(ah)) {
2980 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2981 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2982
2983 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2984 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2985 }
2986 }
2987
2988 mask = ints & ATH9K_INT_COMMON;
2989 mask2 = 0;
2990
2991 if (ints & ATH9K_INT_TX) {
2992 if (ahp->ah_txOkInterruptMask)
2993 mask |= AR_IMR_TXOK;
2994 if (ahp->ah_txDescInterruptMask)
2995 mask |= AR_IMR_TXDESC;
2996 if (ahp->ah_txErrInterruptMask)
2997 mask |= AR_IMR_TXERR;
2998 if (ahp->ah_txEolInterruptMask)
2999 mask |= AR_IMR_TXEOL;
3000 }
3001 if (ints & ATH9K_INT_RX) {
3002 mask |= AR_IMR_RXERR;
3003 if (ahp->ah_intrMitigation)
3004 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3005 else
3006 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3007 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3008 mask |= AR_IMR_GENTMR;
3009 }
3010
3011 if (ints & (ATH9K_INT_BMISC)) {
3012 mask |= AR_IMR_BCNMISC;
3013 if (ints & ATH9K_INT_TIM)
3014 mask2 |= AR_IMR_S2_TIM;
3015 if (ints & ATH9K_INT_DTIM)
3016 mask2 |= AR_IMR_S2_DTIM;
3017 if (ints & ATH9K_INT_DTIMSYNC)
3018 mask2 |= AR_IMR_S2_DTIMSYNC;
3019 if (ints & ATH9K_INT_CABEND)
3020 mask2 |= (AR_IMR_S2_CABEND);
3021 }
3022
3023 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3024 mask |= AR_IMR_BCNMISC;
3025 if (ints & ATH9K_INT_GTT)
3026 mask2 |= AR_IMR_S2_GTT;
3027 if (ints & ATH9K_INT_CST)
3028 mask2 |= AR_IMR_S2_CST;
3029 }
3030
3031 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
3032 mask);
3033 REG_WRITE(ah, AR_IMR, mask);
3034 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3035 AR_IMR_S2_DTIM |
3036 AR_IMR_S2_DTIMSYNC |
3037 AR_IMR_S2_CABEND |
3038 AR_IMR_S2_CABTO |
3039 AR_IMR_S2_TSFOOR |
3040 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3041 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3042 ahp->ah_maskReg = ints;
3043
3044 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3045 if (ints & ATH9K_INT_TIM_TIMER)
3046 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3047 else
3048 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3049 }
3050
3051 if (ints & ATH9K_INT_GLOBAL) {
3052 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "%s: enable IER\n",
3053 __func__);
3054 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3055 if (!AR_SREV_9100(ah)) {
3056 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3057 AR_INTR_MAC_IRQ);
3058 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3059
3060
3061 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3062 AR_INTR_SYNC_DEFAULT);
3063 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3064 AR_INTR_SYNC_DEFAULT);
3065 }
3066 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3067 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3068 }
3069
3070 return omask;
3071 }
3072
3073 /*******************/
3074 /* Beacon Handling */
3075 /*******************/
3076
3077 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3078 {
3079 struct ath_hal_5416 *ahp = AH5416(ah);
3080 int flags = 0;
3081
3082 ahp->ah_beaconInterval = beacon_period;
3083
3084 switch (ah->ah_opmode) {
3085 case ATH9K_M_STA:
3086 case ATH9K_M_MONITOR:
3087 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3088 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3089 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3090 flags |= AR_TBTT_TIMER_EN;
3091 break;
3092 case ATH9K_M_IBSS:
3093 REG_SET_BIT(ah, AR_TXCFG,
3094 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3095 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3096 TU_TO_USEC(next_beacon +
3097 (ahp->ah_atimWindow ? ahp->
3098 ah_atimWindow : 1)));
3099 flags |= AR_NDP_TIMER_EN;
3100 case ATH9K_M_HOSTAP:
3101 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3102 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3103 TU_TO_USEC(next_beacon -
3104 ah->ah_config.
3105 dma_beacon_response_time));
3106 REG_WRITE(ah, AR_NEXT_SWBA,
3107 TU_TO_USEC(next_beacon -
3108 ah->ah_config.
3109 sw_beacon_response_time));
3110 flags |=
3111 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3112 break;
3113 }
3114
3115 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3116 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3117 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3118 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3119
3120 beacon_period &= ~ATH9K_BEACON_ENA;
3121 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3122 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3123 ath9k_hw_reset_tsf(ah);
3124 }
3125
3126 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3127 }
3128
3129 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3130 const struct ath9k_beacon_state *bs)
3131 {
3132 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3133 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3134
3135 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3136
3137 REG_WRITE(ah, AR_BEACON_PERIOD,
3138 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3139 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3140 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3141
3142 REG_RMW_FIELD(ah, AR_RSSI_THR,
3143 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3144
3145 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3146
3147 if (bs->bs_sleepduration > beaconintval)
3148 beaconintval = bs->bs_sleepduration;
3149
3150 dtimperiod = bs->bs_dtimperiod;
3151 if (bs->bs_sleepduration > dtimperiod)
3152 dtimperiod = bs->bs_sleepduration;
3153
3154 if (beaconintval == dtimperiod)
3155 nextTbtt = bs->bs_nextdtim;
3156 else
3157 nextTbtt = bs->bs_nexttbtt;
3158
3159 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next DTIM %d\n", __func__,
3160 bs->bs_nextdtim);
3161 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: next beacon %d\n", __func__,
3162 nextTbtt);
3163 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: beacon period %d\n", __func__,
3164 beaconintval);
3165 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "%s: DTIM period %d\n", __func__,
3166 dtimperiod);
3167
3168 REG_WRITE(ah, AR_NEXT_DTIM,
3169 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3170 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3171
3172 REG_WRITE(ah, AR_SLEEP1,
3173 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3174 | AR_SLEEP1_ASSUME_DTIM);
3175
3176 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3177 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3178 else
3179 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3180
3181 REG_WRITE(ah, AR_SLEEP2,
3182 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3183
3184 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3185 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3186
3187 REG_SET_BIT(ah, AR_TIMER_MODE,
3188 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3189 AR_DTIM_TIMER_EN);
3190
3191 }
3192
3193 /*******************/
3194 /* HW Capabilities */
3195 /*******************/
3196
3197 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3198 {
3199 struct ath_hal_5416 *ahp = AH5416(ah);
3200 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3201 u16 capField = 0, eeval;
3202
3203 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3204
3205 ah->ah_currentRD = eeval;
3206
3207 eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3208 ah->ah_currentRDExt = eeval;
3209
3210 capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3211
3212 if (ah->ah_opmode != ATH9K_M_HOSTAP &&
3213 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3214 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
3215 ah->ah_currentRD += 5;
3216 else if (ah->ah_currentRD == 0x41)
3217 ah->ah_currentRD = 0x43;
3218 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3219 "%s: regdomain mapped to 0x%x\n", __func__,
3220 ah->ah_currentRD);
3221 }
3222
3223 eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3224 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3225
3226 if (eeval & AR5416_OPFLAGS_11A) {
3227 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3228 if (ah->ah_config.ht_enable) {
3229 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3230 set_bit(ATH9K_MODE_11NA_HT20,
3231 pCap->wireless_modes);
3232 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3233 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3234 pCap->wireless_modes);
3235 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3236 pCap->wireless_modes);
3237 }
3238 }
3239 }
3240
3241 if (eeval & AR5416_OPFLAGS_11G) {
3242 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3243 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3244 if (ah->ah_config.ht_enable) {
3245 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3246 set_bit(ATH9K_MODE_11NG_HT20,
3247 pCap->wireless_modes);
3248 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3249 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3250 pCap->wireless_modes);
3251 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3252 pCap->wireless_modes);
3253 }
3254 }
3255 }
3256
3257 pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3258 if ((ah->ah_isPciExpress)
3259 || (eeval & AR5416_OPFLAGS_11A)) {
3260 pCap->rx_chainmask =
3261 ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3262 } else {
3263 pCap->rx_chainmask =
3264 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3265 }
3266
3267 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3268 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3269
3270 pCap->low_2ghz_chan = 2312;
3271 pCap->high_2ghz_chan = 2732;
3272
3273 pCap->low_5ghz_chan = 4920;
3274 pCap->high_5ghz_chan = 6100;
3275
3276 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3277 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3278 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3279
3280 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3281 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3282 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3283
3284 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3285
3286 if (ah->ah_config.ht_enable)
3287 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3288 else
3289 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3290
3291 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3292 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3293 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3294 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3295
3296 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3297 pCap->total_queues =
3298 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3299 else
3300 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3301
3302 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3303 pCap->keycache_size =
3304 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3305 else
3306 pCap->keycache_size = AR_KEYTABLE_SIZE;
3307
3308 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3309 pCap->num_mr_retries = 4;
3310 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3311
3312 if (AR_SREV_9280_10_OR_LATER(ah))
3313 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3314 else
3315 pCap->num_gpio_pins = AR_NUM_GPIO;
3316
3317 if (AR_SREV_9280_10_OR_LATER(ah)) {
3318 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3319 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3320 } else {
3321 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3322 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3323 }
3324
3325 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3326 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3327 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3328 } else {
3329 pCap->rts_aggr_limit = (8 * 1024);
3330 }
3331
3332 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3333
3334 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3335 ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3336 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3337 ah->ah_rfkill_gpio =
3338 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3339 ah->ah_rfkill_polarity =
3340 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3341
3342 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3343 }
3344 #endif
3345
3346 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3347 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3348 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3349 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3350 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3351 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3352 else
3353 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3354
3355 if (AR_SREV_9280(ah))
3356 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3357 else
3358 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3359
3360 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3361 pCap->reg_cap =
3362 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3363 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3364 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3365 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3366 } else {
3367 pCap->reg_cap =
3368 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3369 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3370 }
3371
3372 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3373
3374 pCap->num_antcfg_5ghz =
3375 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_5GHZ);
3376 pCap->num_antcfg_2ghz =
3377 ath9k_hw_get_num_ant_config(ah, IEEE80211_BAND_2GHZ);
3378
3379 return true;
3380 }
3381
3382 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3383 u32 capability, u32 *result)
3384 {
3385 struct ath_hal_5416 *ahp = AH5416(ah);
3386 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3387
3388 switch (type) {
3389 case ATH9K_CAP_CIPHER:
3390 switch (capability) {
3391 case ATH9K_CIPHER_AES_CCM:
3392 case ATH9K_CIPHER_AES_OCB:
3393 case ATH9K_CIPHER_TKIP:
3394 case ATH9K_CIPHER_WEP:
3395 case ATH9K_CIPHER_MIC:
3396 case ATH9K_CIPHER_CLR:
3397 return true;
3398 default:
3399 return false;
3400 }
3401 case ATH9K_CAP_TKIP_MIC:
3402 switch (capability) {
3403 case 0:
3404 return true;
3405 case 1:
3406 return (ahp->ah_staId1Defaults &
3407 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3408 false;
3409 }
3410 case ATH9K_CAP_TKIP_SPLIT:
3411 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3412 false : true;
3413 case ATH9K_CAP_WME_TKIPMIC:
3414 return 0;
3415 case ATH9K_CAP_PHYCOUNTERS:
3416 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3417 case ATH9K_CAP_DIVERSITY:
3418 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3419 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3420 true : false;
3421 case ATH9K_CAP_PHYDIAG:
3422 return true;
3423 case ATH9K_CAP_MCAST_KEYSRCH:
3424 switch (capability) {
3425 case 0:
3426 return true;
3427 case 1:
3428 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3429 return false;
3430 } else {
3431 return (ahp->ah_staId1Defaults &
3432 AR_STA_ID1_MCAST_KSRCH) ? true :
3433 false;
3434 }
3435 }
3436 return false;
3437 case ATH9K_CAP_TSF_ADJUST:
3438 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3439 true : false;
3440 case ATH9K_CAP_RFSILENT:
3441 if (capability == 3)
3442 return false;
3443 case ATH9K_CAP_ANT_CFG_2GHZ:
3444 *result = pCap->num_antcfg_2ghz;
3445 return true;
3446 case ATH9K_CAP_ANT_CFG_5GHZ:
3447 *result = pCap->num_antcfg_5ghz;
3448 return true;
3449 case ATH9K_CAP_TXPOW:
3450 switch (capability) {
3451 case 0:
3452 return 0;
3453 case 1:
3454 *result = ah->ah_powerLimit;
3455 return 0;
3456 case 2:
3457 *result = ah->ah_maxPowerLevel;
3458 return 0;
3459 case 3:
3460 *result = ah->ah_tpScale;
3461 return 0;
3462 }
3463 return false;
3464 default:
3465 return false;
3466 }
3467 }
3468
3469 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3470 u32 capability, u32 setting, int *status)
3471 {
3472 struct ath_hal_5416 *ahp = AH5416(ah);
3473 u32 v;
3474
3475 switch (type) {
3476 case ATH9K_CAP_TKIP_MIC:
3477 if (setting)
3478 ahp->ah_staId1Defaults |=
3479 AR_STA_ID1_CRPT_MIC_ENABLE;
3480 else
3481 ahp->ah_staId1Defaults &=
3482 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3483 return true;
3484 case ATH9K_CAP_DIVERSITY:
3485 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3486 if (setting)
3487 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3488 else
3489 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3490 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3491 return true;
3492 case ATH9K_CAP_MCAST_KEYSRCH:
3493 if (setting)
3494 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3495 else
3496 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3497 return true;
3498 case ATH9K_CAP_TSF_ADJUST:
3499 if (setting)
3500 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3501 else
3502 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3503 return true;
3504 default:
3505 return false;
3506 }
3507 }
3508
3509 /****************************/
3510 /* GPIO / RFKILL / Antennae */
3511 /****************************/
3512
3513 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3514 u32 gpio, u32 type)
3515 {
3516 int addr;
3517 u32 gpio_shift, tmp;
3518
3519 if (gpio > 11)
3520 addr = AR_GPIO_OUTPUT_MUX3;
3521 else if (gpio > 5)
3522 addr = AR_GPIO_OUTPUT_MUX2;
3523 else
3524 addr = AR_GPIO_OUTPUT_MUX1;
3525
3526 gpio_shift = (gpio % 6) * 5;
3527
3528 if (AR_SREV_9280_20_OR_LATER(ah)
3529 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3530 REG_RMW(ah, addr, (type << gpio_shift),
3531 (0x1f << gpio_shift));
3532 } else {
3533 tmp = REG_READ(ah, addr);
3534 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3535 tmp &= ~(0x1f << gpio_shift);
3536 tmp |= (type << gpio_shift);
3537 REG_WRITE(ah, addr, tmp);
3538 }
3539 }
3540
3541 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3542 {
3543 u32 gpio_shift;
3544
3545 ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3546
3547 gpio_shift = gpio << 1;
3548
3549 REG_RMW(ah,
3550 AR_GPIO_OE_OUT,
3551 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3552 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3553 }
3554
3555 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3556 {
3557 if (gpio >= ah->ah_caps.num_gpio_pins)
3558 return 0xffffffff;
3559
3560 if (AR_SREV_9280_10_OR_LATER(ah)) {
3561 return (MS
3562 (REG_READ(ah, AR_GPIO_IN_OUT),
3563 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
3564 } else {
3565 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
3566 AR_GPIO_BIT(gpio)) != 0;
3567 }
3568 }
3569
3570 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3571 u32 ah_signal_type)
3572 {
3573 u32 gpio_shift;
3574
3575 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3576
3577 gpio_shift = 2 * gpio;
3578
3579 REG_RMW(ah,
3580 AR_GPIO_OE_OUT,
3581 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3582 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3583 }
3584
3585 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3586 {
3587 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3588 AR_GPIO_BIT(gpio));
3589 }
3590
3591 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3592 void ath9k_enable_rfkill(struct ath_hal *ah)
3593 {
3594 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3595 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3596
3597 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3598 AR_GPIO_INPUT_MUX2_RFSILENT);
3599
3600 ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3601 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3602 }
3603 #endif
3604
3605 int ath9k_hw_select_antconfig(struct ath_hal *ah, u32 cfg)
3606 {
3607 struct ath9k_channel *chan = ah->ah_curchan;
3608 const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3609 u16 ant_config;
3610 u32 halNumAntConfig;
3611
3612 halNumAntConfig = IS_CHAN_2GHZ(chan) ?
3613 pCap->num_antcfg_2ghz : pCap->num_antcfg_5ghz;
3614
3615 if (cfg < halNumAntConfig) {
3616 if (!ath9k_hw_get_eeprom_antenna_cfg(ah, chan,
3617 cfg, &ant_config)) {
3618 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
3619 return 0;
3620 }
3621 }
3622
3623 return -EINVAL;
3624 }
3625
3626 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3627 {
3628 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3629 }
3630
3631 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3632 {
3633 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3634 }
3635
3636 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3637 enum ath9k_ant_setting settings,
3638 struct ath9k_channel *chan,
3639 u8 *tx_chainmask,
3640 u8 *rx_chainmask,
3641 u8 *antenna_cfgd)
3642 {
3643 struct ath_hal_5416 *ahp = AH5416(ah);
3644 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3645
3646 if (AR_SREV_9280(ah)) {
3647 if (!tx_chainmask_cfg) {
3648
3649 tx_chainmask_cfg = *tx_chainmask;
3650 rx_chainmask_cfg = *rx_chainmask;
3651 }
3652
3653 switch (settings) {
3654 case ATH9K_ANT_FIXED_A:
3655 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3656 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3657 *antenna_cfgd = true;
3658 break;
3659 case ATH9K_ANT_FIXED_B:
3660 if (ah->ah_caps.tx_chainmask >
3661 ATH9K_ANTENNA1_CHAINMASK) {
3662 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3663 }
3664 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3665 *antenna_cfgd = true;
3666 break;
3667 case ATH9K_ANT_VARIABLE:
3668 *tx_chainmask = tx_chainmask_cfg;
3669 *rx_chainmask = rx_chainmask_cfg;
3670 *antenna_cfgd = true;
3671 break;
3672 default:
3673 break;
3674 }
3675 } else {
3676 ahp->ah_diversityControl = settings;
3677 }
3678
3679 return true;
3680 }
3681
3682 /*********************/
3683 /* General Operation */
3684 /*********************/
3685
3686 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3687 {
3688 u32 bits = REG_READ(ah, AR_RX_FILTER);
3689 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3690
3691 if (phybits & AR_PHY_ERR_RADAR)
3692 bits |= ATH9K_RX_FILTER_PHYRADAR;
3693 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3694 bits |= ATH9K_RX_FILTER_PHYERR;
3695
3696 return bits;
3697 }
3698
3699 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3700 {
3701 u32 phybits;
3702
3703 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3704 phybits = 0;
3705 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3706 phybits |= AR_PHY_ERR_RADAR;
3707 if (bits & ATH9K_RX_FILTER_PHYERR)
3708 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3709 REG_WRITE(ah, AR_PHY_ERR, phybits);
3710
3711 if (phybits)
3712 REG_WRITE(ah, AR_RXCFG,
3713 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3714 else
3715 REG_WRITE(ah, AR_RXCFG,
3716 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3717 }
3718
3719 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3720 {
3721 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3722 }
3723
3724 bool ath9k_hw_disable(struct ath_hal *ah)
3725 {
3726 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3727 return false;
3728
3729 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3730 }
3731
3732 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3733 {
3734 struct ath9k_channel *chan = ah->ah_curchan;
3735
3736 ah->ah_powerLimit = min(limit, (u32) MAX_RATE_POWER);
3737
3738 if (ath9k_hw_set_txpower(ah, chan,
3739 ath9k_regd_get_ctl(ah, chan),
3740 ath9k_regd_get_antenna_allowed(ah, chan),
3741 chan->maxRegTxPower * 2,
3742 min((u32) MAX_RATE_POWER,
3743 (u32) ah->ah_powerLimit)) != 0)
3744 return false;
3745
3746 return true;
3747 }
3748
3749 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac)
3750 {
3751 struct ath_hal_5416 *ahp = AH5416(ah);
3752
3753 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
3754 }
3755
3756 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3757 {
3758 struct ath_hal_5416 *ahp = AH5416(ah);
3759
3760 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
3761
3762 return true;
3763 }
3764
3765 void ath9k_hw_setopmode(struct ath_hal *ah)
3766 {
3767 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3768 }
3769
3770 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3771 {
3772 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3773 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3774 }
3775
3776 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask)
3777 {
3778 struct ath_hal_5416 *ahp = AH5416(ah);
3779
3780 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
3781 }
3782
3783 bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask)
3784 {
3785 struct ath_hal_5416 *ahp = AH5416(ah);
3786
3787 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
3788
3789 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(ahp->ah_bssidmask));
3790 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(ahp->ah_bssidmask + 4));
3791
3792 return true;
3793 }
3794
3795 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId)
3796 {
3797 struct ath_hal_5416 *ahp = AH5416(ah);
3798
3799 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
3800 ahp->ah_assocId = assocId;
3801
3802 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(ahp->ah_bssid));
3803 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(ahp->ah_bssid + 4) |
3804 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
3805 }
3806
3807 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3808 {
3809 u64 tsf;
3810
3811 tsf = REG_READ(ah, AR_TSF_U32);
3812 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3813
3814 return tsf;
3815 }
3816
3817 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3818 {
3819 int count;
3820
3821 count = 0;
3822 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3823 count++;
3824 if (count > 10) {
3825 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3826 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
3827 __func__);
3828 break;
3829 }
3830 udelay(10);
3831 }
3832 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3833 }
3834
3835 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3836 {
3837 struct ath_hal_5416 *ahp = AH5416(ah);
3838
3839 if (setting)
3840 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3841 else
3842 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3843
3844 return true;
3845 }
3846
3847 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3848 {
3849 struct ath_hal_5416 *ahp = AH5416(ah);
3850
3851 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3852 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s: bad slot time %u\n",
3853 __func__, us);
3854 ahp->ah_slottime = (u32) -1;
3855 return false;
3856 } else {
3857 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3858 ahp->ah_slottime = us;
3859 return true;
3860 }
3861 }
3862
3863 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3864 {
3865 u32 macmode;
3866
3867 if (mode == ATH9K_HT_MACMODE_2040 &&
3868 !ah->ah_config.cwm_ignore_extcca)
3869 macmode = AR_2040_JOINED_RX_CLEAR;
3870 else
3871 macmode = 0;
3872
3873 REG_WRITE(ah, AR_2040_MODE, macmode);
3874 }
linux 2.6 git repository for openrd