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s3cmci: fix direct write to interrupt mask
[linux-2.6/linux-2.6-openrd.git] / drivers / mmc / host / s3cmci.c
blob28a4a4535f385474b8e970af2c422945770d76bc
1 /*
2 * linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
3 *
4 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
5 *
6 * Current driver maintained by Ben Dooks and Simtec Electronics
7 * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/clk.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_device.h>
19 #include <linux/cpufreq.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/io.h>
23
24 #include <mach/dma.h>
25
26 #include <mach/regs-sdi.h>
27 #include <mach/regs-gpio.h>
28
29 #include <plat/mci.h>
30
31 #include "s3cmci.h"
32
33 #define DRIVER_NAME "s3c-mci"
34
35 enum dbg_channels {
36 dbg_err = (1 << 0),
37 dbg_debug = (1 << 1),
38 dbg_info = (1 << 2),
39 dbg_irq = (1 << 3),
40 dbg_sg = (1 << 4),
41 dbg_dma = (1 << 5),
42 dbg_pio = (1 << 6),
43 dbg_fail = (1 << 7),
44 dbg_conf = (1 << 8),
45 };
46
47 static const int dbgmap_err = dbg_fail;
48 static const int dbgmap_info = dbg_info | dbg_conf;
49 static const int dbgmap_debug = dbg_err | dbg_debug;
50
51 #define dbg(host, channels, args...) \
52 do { \
53 if (dbgmap_err & channels) \
54 dev_err(&host->pdev->dev, args); \
55 else if (dbgmap_info & channels) \
56 dev_info(&host->pdev->dev, args); \
57 else if (dbgmap_debug & channels) \
58 dev_dbg(&host->pdev->dev, args); \
59 } while (0)
60
61 static struct s3c2410_dma_client s3cmci_dma_client = {
62 .name = "s3c-mci",
63 };
64
65 static void finalize_request(struct s3cmci_host *host);
66 static void s3cmci_send_request(struct mmc_host *mmc);
67 static void s3cmci_reset(struct s3cmci_host *host);
68
69 #ifdef CONFIG_MMC_DEBUG
70
71 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
72 {
73 u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
74 u32 datcon, datcnt, datsta, fsta, imask;
75
76 con = readl(host->base + S3C2410_SDICON);
77 pre = readl(host->base + S3C2410_SDIPRE);
78 cmdarg = readl(host->base + S3C2410_SDICMDARG);
79 cmdcon = readl(host->base + S3C2410_SDICMDCON);
80 cmdsta = readl(host->base + S3C2410_SDICMDSTAT);
81 r0 = readl(host->base + S3C2410_SDIRSP0);
82 r1 = readl(host->base + S3C2410_SDIRSP1);
83 r2 = readl(host->base + S3C2410_SDIRSP2);
84 r3 = readl(host->base + S3C2410_SDIRSP3);
85 timer = readl(host->base + S3C2410_SDITIMER);
86 bsize = readl(host->base + S3C2410_SDIBSIZE);
87 datcon = readl(host->base + S3C2410_SDIDCON);
88 datcnt = readl(host->base + S3C2410_SDIDCNT);
89 datsta = readl(host->base + S3C2410_SDIDSTA);
90 fsta = readl(host->base + S3C2410_SDIFSTA);
91 imask = readl(host->base + host->sdiimsk);
92
93 dbg(host, dbg_debug, "%s CON:[%08x] PRE:[%08x] TMR:[%08x]\n",
94 prefix, con, pre, timer);
95
96 dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
97 prefix, cmdcon, cmdarg, cmdsta);
98
99 dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
100 " DSTA:[%08x] DCNT:[%08x]\n",
101 prefix, datcon, fsta, datsta, datcnt);
102
103 dbg(host, dbg_debug, "%s R0:[%08x] R1:[%08x]"
104 " R2:[%08x] R3:[%08x]\n",
105 prefix, r0, r1, r2, r3);
106 }
107
108 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
109 int stop)
110 {
111 snprintf(host->dbgmsg_cmd, 300,
112 "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
113 host->ccnt, (stop ? " (STOP)" : ""),
114 cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
115
116 if (cmd->data) {
117 snprintf(host->dbgmsg_dat, 300,
118 "#%u bsize:%u blocks:%u bytes:%u",
119 host->dcnt, cmd->data->blksz,
120 cmd->data->blocks,
121 cmd->data->blocks * cmd->data->blksz);
122 } else {
123 host->dbgmsg_dat[0] = '\0';
124 }
125 }
126
127 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
128 int fail)
129 {
130 unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
131
132 if (!cmd)
133 return;
134
135 if (cmd->error == 0) {
136 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
137 host->dbgmsg_cmd, cmd->resp[0]);
138 } else {
139 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
140 cmd->error, host->dbgmsg_cmd, host->status);
141 }
142
143 if (!cmd->data)
144 return;
145
146 if (cmd->data->error == 0) {
147 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
148 } else {
149 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
150 cmd->data->error, host->dbgmsg_dat,
151 readl(host->base + S3C2410_SDIDCNT));
152 }
153 }
154 #else
155 static void dbg_dumpcmd(struct s3cmci_host *host,
156 struct mmc_command *cmd, int fail) { }
157
158 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
159 int stop) { }
160
161 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
162
163 #endif /* CONFIG_MMC_DEBUG */
164
165 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
166 {
167 u32 newmask;
168
169 newmask = readl(host->base + host->sdiimsk);
170 newmask |= imask;
171
172 writel(newmask, host->base + host->sdiimsk);
173
174 return newmask;
175 }
176
177 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
178 {
179 u32 newmask;
180
181 newmask = readl(host->base + host->sdiimsk);
182 newmask &= ~imask;
183
184 writel(newmask, host->base + host->sdiimsk);
185
186 return newmask;
187 }
188
189 static inline void clear_imask(struct s3cmci_host *host)
190 {
191 writel(0, host->base + host->sdiimsk);
192 }
193
194 static inline int get_data_buffer(struct s3cmci_host *host,
195 u32 *bytes, u32 **pointer)
196 {
197 struct scatterlist *sg;
198
199 if (host->pio_active == XFER_NONE)
200 return -EINVAL;
201
202 if ((!host->mrq) || (!host->mrq->data))
203 return -EINVAL;
204
205 if (host->pio_sgptr >= host->mrq->data->sg_len) {
206 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
207 host->pio_sgptr, host->mrq->data->sg_len);
208 return -EBUSY;
209 }
210 sg = &host->mrq->data->sg[host->pio_sgptr];
211
212 *bytes = sg->length;
213 *pointer = sg_virt(sg);
214
215 host->pio_sgptr++;
216
217 dbg(host, dbg_sg, "new buffer (%i/%i)\n",
218 host->pio_sgptr, host->mrq->data->sg_len);
219
220 return 0;
221 }
222
223 static inline u32 fifo_count(struct s3cmci_host *host)
224 {
225 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
226
227 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
228 return fifostat;
229 }
230
231 static inline u32 fifo_free(struct s3cmci_host *host)
232 {
233 u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
234
235 fifostat &= S3C2410_SDIFSTA_COUNTMASK;
236 return 63 - fifostat;
237 }
238
239 static void do_pio_read(struct s3cmci_host *host)
240 {
241 int res;
242 u32 fifo;
243 u32 *ptr;
244 u32 fifo_words;
245 void __iomem *from_ptr;
246
247 /* write real prescaler to host, it might be set slow to fix */
248 writel(host->prescaler, host->base + S3C2410_SDIPRE);
249
250 from_ptr = host->base + host->sdidata;
251
252 while ((fifo = fifo_count(host))) {
253 if (!host->pio_bytes) {
254 res = get_data_buffer(host, &host->pio_bytes,
255 &host->pio_ptr);
256 if (res) {
257 host->pio_active = XFER_NONE;
258 host->complete_what = COMPLETION_FINALIZE;
259
260 dbg(host, dbg_pio, "pio_read(): "
261 "complete (no more data).\n");
262 return;
263 }
264
265 dbg(host, dbg_pio,
266 "pio_read(): new target: [%i]@[%p]\n",
267 host->pio_bytes, host->pio_ptr);
268 }
269
270 dbg(host, dbg_pio,
271 "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
272 fifo, host->pio_bytes,
273 readl(host->base + S3C2410_SDIDCNT));
274
275 /* If we have reached the end of the block, we can
276 * read a word and get 1 to 3 bytes. If we in the
277 * middle of the block, we have to read full words,
278 * otherwise we will write garbage, so round down to
279 * an even multiple of 4. */
280 if (fifo >= host->pio_bytes)
281 fifo = host->pio_bytes;
282 else
283 fifo -= fifo & 3;
284
285 host->pio_bytes -= fifo;
286 host->pio_count += fifo;
287
288 fifo_words = fifo >> 2;
289 ptr = host->pio_ptr;
290 while (fifo_words--)
291 *ptr++ = readl(from_ptr);
292 host->pio_ptr = ptr;
293
294 if (fifo & 3) {
295 u32 n = fifo & 3;
296 u32 data = readl(from_ptr);
297 u8 *p = (u8 *)host->pio_ptr;
298
299 while (n--) {
300 *p++ = data;
301 data >>= 8;
302 }
303 }
304 }
305
306 if (!host->pio_bytes) {
307 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
308 if (res) {
309 dbg(host, dbg_pio,
310 "pio_read(): complete (no more buffers).\n");
311 host->pio_active = XFER_NONE;
312 host->complete_what = COMPLETION_FINALIZE;
313
314 return;
315 }
316 }
317
318 enable_imask(host,
319 S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
320 }
321
322 static void do_pio_write(struct s3cmci_host *host)
323 {
324 void __iomem *to_ptr;
325 int res;
326 u32 fifo;
327 u32 *ptr;
328
329 to_ptr = host->base + host->sdidata;
330
331 while ((fifo = fifo_free(host)) > 3) {
332 if (!host->pio_bytes) {
333 res = get_data_buffer(host, &host->pio_bytes,
334 &host->pio_ptr);
335 if (res) {
336 dbg(host, dbg_pio,
337 "pio_write(): complete (no more data).\n");
338 host->pio_active = XFER_NONE;
339
340 return;
341 }
342
343 dbg(host, dbg_pio,
344 "pio_write(): new source: [%i]@[%p]\n",
345 host->pio_bytes, host->pio_ptr);
346
347 }
348
349 /* If we have reached the end of the block, we have to
350 * write exactly the remaining number of bytes. If we
351 * in the middle of the block, we have to write full
352 * words, so round down to an even multiple of 4. */
353 if (fifo >= host->pio_bytes)
354 fifo = host->pio_bytes;
355 else
356 fifo -= fifo & 3;
357
358 host->pio_bytes -= fifo;
359 host->pio_count += fifo;
360
361 fifo = (fifo + 3) >> 2;
362 ptr = host->pio_ptr;
363 while (fifo--)
364 writel(*ptr++, to_ptr);
365 host->pio_ptr = ptr;
366 }
367
368 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
369 }
370
371 static void pio_tasklet(unsigned long data)
372 {
373 struct s3cmci_host *host = (struct s3cmci_host *) data;
374
375
376 disable_irq(host->irq);
377
378 if (host->pio_active == XFER_WRITE)
379 do_pio_write(host);
380
381 if (host->pio_active == XFER_READ)
382 do_pio_read(host);
383
384 if (host->complete_what == COMPLETION_FINALIZE) {
385 clear_imask(host);
386 if (host->pio_active != XFER_NONE) {
387 dbg(host, dbg_err, "unfinished %s "
388 "- pio_count:[%u] pio_bytes:[%u]\n",
389 (host->pio_active == XFER_READ) ? "read" : "write",
390 host->pio_count, host->pio_bytes);
391
392 if (host->mrq->data)
393 host->mrq->data->error = -EINVAL;
394 }
395
396 finalize_request(host);
397 } else
398 enable_irq(host->irq);
399 }
400
401 /*
402 * ISR for SDI Interface IRQ
403 * Communication between driver and ISR works as follows:
404 * host->mrq points to current request
405 * host->complete_what Indicates when the request is considered done
406 * COMPLETION_CMDSENT when the command was sent
407 * COMPLETION_RSPFIN when a response was received
408 * COMPLETION_XFERFINISH when the data transfer is finished
409 * COMPLETION_XFERFINISH_RSPFIN both of the above.
410 * host->complete_request is the completion-object the driver waits for
411 *
412 * 1) Driver sets up host->mrq and host->complete_what
413 * 2) Driver prepares the transfer
414 * 3) Driver enables interrupts
415 * 4) Driver starts transfer
416 * 5) Driver waits for host->complete_rquest
417 * 6) ISR checks for request status (errors and success)
418 * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
419 * 7) ISR completes host->complete_request
420 * 8) ISR disables interrupts
421 * 9) Driver wakes up and takes care of the request
422 *
423 * Note: "->error"-fields are expected to be set to 0 before the request
424 * was issued by mmc.c - therefore they are only set, when an error
425 * contition comes up
426 */
427
428 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
429 {
430 struct s3cmci_host *host = dev_id;
431 struct mmc_command *cmd;
432 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
433 u32 mci_cclear, mci_dclear;
434 unsigned long iflags;
435
436 spin_lock_irqsave(&host->complete_lock, iflags);
437
438 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
439 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
440 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
441 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
442 mci_imsk = readl(host->base + host->sdiimsk);
443 mci_cclear = 0;
444 mci_dclear = 0;
445
446 if ((host->complete_what == COMPLETION_NONE) ||
447 (host->complete_what == COMPLETION_FINALIZE)) {
448 host->status = "nothing to complete";
449 clear_imask(host);
450 goto irq_out;
451 }
452
453 if (!host->mrq) {
454 host->status = "no active mrq";
455 clear_imask(host);
456 goto irq_out;
457 }
458
459 cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
460
461 if (!cmd) {
462 host->status = "no active cmd";
463 clear_imask(host);
464 goto irq_out;
465 }
466
467 if (!host->dodma) {
468 if ((host->pio_active == XFER_WRITE) &&
469 (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
470
471 disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
472 tasklet_schedule(&host->pio_tasklet);
473 host->status = "pio tx";
474 }
475
476 if ((host->pio_active == XFER_READ) &&
477 (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
478
479 disable_imask(host,
480 S3C2410_SDIIMSK_RXFIFOHALF |
481 S3C2410_SDIIMSK_RXFIFOLAST);
482
483 tasklet_schedule(&host->pio_tasklet);
484 host->status = "pio rx";
485 }
486 }
487
488 if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
489 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
490 cmd->error = -ETIMEDOUT;
491 host->status = "error: command timeout";
492 goto fail_transfer;
493 }
494
495 if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
496 if (host->complete_what == COMPLETION_CMDSENT) {
497 host->status = "ok: command sent";
498 goto close_transfer;
499 }
500
501 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
502 }
503
504 if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
505 if (cmd->flags & MMC_RSP_CRC) {
506 if (host->mrq->cmd->flags & MMC_RSP_136) {
507 dbg(host, dbg_irq,
508 "fixup: ignore CRC fail with long rsp\n");
509 } else {
510 /* note, we used to fail the transfer
511 * here, but it seems that this is just
512 * the hardware getting it wrong.
513 *
514 * cmd->error = -EILSEQ;
515 * host->status = "error: bad command crc";
516 * goto fail_transfer;
517 */
518 }
519 }
520
521 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
522 }
523
524 if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
525 if (host->complete_what == COMPLETION_RSPFIN) {
526 host->status = "ok: command response received";
527 goto close_transfer;
528 }
529
530 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
531 host->complete_what = COMPLETION_XFERFINISH;
532
533 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
534 }
535
536 /* errors handled after this point are only relevant
537 when a data transfer is in progress */
538
539 if (!cmd->data)
540 goto clear_status_bits;
541
542 /* Check for FIFO failure */
543 if (host->is2440) {
544 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
545 dbg(host, dbg_err, "FIFO failure\n");
546 host->mrq->data->error = -EILSEQ;
547 host->status = "error: 2440 fifo failure";
548 goto fail_transfer;
549 }
550 } else {
551 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
552 dbg(host, dbg_err, "FIFO failure\n");
553 cmd->data->error = -EILSEQ;
554 host->status = "error: fifo failure";
555 goto fail_transfer;
556 }
557 }
558
559 if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
560 dbg(host, dbg_err, "bad data crc (outgoing)\n");
561 cmd->data->error = -EILSEQ;
562 host->status = "error: bad data crc (outgoing)";
563 goto fail_transfer;
564 }
565
566 if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
567 dbg(host, dbg_err, "bad data crc (incoming)\n");
568 cmd->data->error = -EILSEQ;
569 host->status = "error: bad data crc (incoming)";
570 goto fail_transfer;
571 }
572
573 if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
574 dbg(host, dbg_err, "data timeout\n");
575 cmd->data->error = -ETIMEDOUT;
576 host->status = "error: data timeout";
577 goto fail_transfer;
578 }
579
580 if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
581 if (host->complete_what == COMPLETION_XFERFINISH) {
582 host->status = "ok: data transfer completed";
583 goto close_transfer;
584 }
585
586 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
587 host->complete_what = COMPLETION_RSPFIN;
588
589 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
590 }
591
592 clear_status_bits:
593 writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
594 writel(mci_dclear, host->base + S3C2410_SDIDSTA);
595
596 goto irq_out;
597
598 fail_transfer:
599 host->pio_active = XFER_NONE;
600
601 close_transfer:
602 host->complete_what = COMPLETION_FINALIZE;
603
604 clear_imask(host);
605 tasklet_schedule(&host->pio_tasklet);
606
607 goto irq_out;
608
609 irq_out:
610 dbg(host, dbg_irq,
611 "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
612 mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
613
614 spin_unlock_irqrestore(&host->complete_lock, iflags);
615 return IRQ_HANDLED;
616
617 }
618
619 /*
620 * ISR for the CardDetect Pin
621 */
622
623 static irqreturn_t s3cmci_irq_cd(int irq, void *dev_id)
624 {
625 struct s3cmci_host *host = (struct s3cmci_host *)dev_id;
626
627 dbg(host, dbg_irq, "card detect\n");
628
629 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
630
631 return IRQ_HANDLED;
632 }
633
634 static void s3cmci_dma_done_callback(struct s3c2410_dma_chan *dma_ch,
635 void *buf_id, int size,
636 enum s3c2410_dma_buffresult result)
637 {
638 struct s3cmci_host *host = buf_id;
639 unsigned long iflags;
640 u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt;
641
642 mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
643 mci_dsta = readl(host->base + S3C2410_SDIDSTA);
644 mci_fsta = readl(host->base + S3C2410_SDIFSTA);
645 mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
646
647 BUG_ON(!host->mrq);
648 BUG_ON(!host->mrq->data);
649 BUG_ON(!host->dmatogo);
650
651 spin_lock_irqsave(&host->complete_lock, iflags);
652
653 if (result != S3C2410_RES_OK) {
654 dbg(host, dbg_fail, "DMA FAILED: csta=0x%08x dsta=0x%08x "
655 "fsta=0x%08x dcnt:0x%08x result:0x%08x toGo:%u\n",
656 mci_csta, mci_dsta, mci_fsta,
657 mci_dcnt, result, host->dmatogo);
658
659 goto fail_request;
660 }
661
662 host->dmatogo--;
663 if (host->dmatogo) {
664 dbg(host, dbg_dma, "DMA DONE Size:%i DSTA:[%08x] "
665 "DCNT:[%08x] toGo:%u\n",
666 size, mci_dsta, mci_dcnt, host->dmatogo);
667
668 goto out;
669 }
670
671 dbg(host, dbg_dma, "DMA FINISHED Size:%i DSTA:%08x DCNT:%08x\n",
672 size, mci_dsta, mci_dcnt);
673
674 host->complete_what = COMPLETION_FINALIZE;
675
676 out:
677 tasklet_schedule(&host->pio_tasklet);
678 spin_unlock_irqrestore(&host->complete_lock, iflags);
679 return;
680
681 fail_request:
682 host->mrq->data->error = -EINVAL;
683 host->complete_what = COMPLETION_FINALIZE;
684 clear_imask(host);
685
686 goto out;
687 }
688
689 static void finalize_request(struct s3cmci_host *host)
690 {
691 struct mmc_request *mrq = host->mrq;
692 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
693 int debug_as_failure = 0;
694
695 if (host->complete_what != COMPLETION_FINALIZE)
696 return;
697
698 if (!mrq)
699 return;
700
701 if (cmd->data && (cmd->error == 0) &&
702 (cmd->data->error == 0)) {
703 if (host->dodma && (!host->dma_complete)) {
704 dbg(host, dbg_dma, "DMA Missing!\n");
705 return;
706 }
707 }
708
709 /* Read response from controller. */
710 cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
711 cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
712 cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
713 cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
714
715 writel(host->prescaler, host->base + S3C2410_SDIPRE);
716
717 if (cmd->error)
718 debug_as_failure = 1;
719
720 if (cmd->data && cmd->data->error)
721 debug_as_failure = 1;
722
723 dbg_dumpcmd(host, cmd, debug_as_failure);
724
725 /* Cleanup controller */
726 writel(0, host->base + S3C2410_SDICMDARG);
727 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
728 writel(0, host->base + S3C2410_SDICMDCON);
729 clear_imask(host);
730
731 if (cmd->data && cmd->error)
732 cmd->data->error = cmd->error;
733
734 if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
735 host->cmd_is_stop = 1;
736 s3cmci_send_request(host->mmc);
737 return;
738 }
739
740 /* If we have no data transfer we are finished here */
741 if (!mrq->data)
742 goto request_done;
743
744 /* Calulate the amout of bytes transfer if there was no error */
745 if (mrq->data->error == 0) {
746 mrq->data->bytes_xfered =
747 (mrq->data->blocks * mrq->data->blksz);
748 } else {
749 mrq->data->bytes_xfered = 0;
750 }
751
752 /* If we had an error while transfering data we flush the
753 * DMA channel and the fifo to clear out any garbage. */
754 if (mrq->data->error != 0) {
755 if (host->dodma)
756 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
757
758 if (host->is2440) {
759 /* Clear failure register and reset fifo. */
760 writel(S3C2440_SDIFSTA_FIFORESET |
761 S3C2440_SDIFSTA_FIFOFAIL,
762 host->base + S3C2410_SDIFSTA);
763 } else {
764 u32 mci_con;
765
766 /* reset fifo */
767 mci_con = readl(host->base + S3C2410_SDICON);
768 mci_con |= S3C2410_SDICON_FIFORESET;
769
770 writel(mci_con, host->base + S3C2410_SDICON);
771 }
772 }
773
774 request_done:
775 host->complete_what = COMPLETION_NONE;
776 host->mrq = NULL;
777 mmc_request_done(host->mmc, mrq);
778 }
779
780 static void s3cmci_dma_setup(struct s3cmci_host *host,
781 enum s3c2410_dmasrc source)
782 {
783 static enum s3c2410_dmasrc last_source = -1;
784 static int setup_ok;
785
786 if (last_source == source)
787 return;
788
789 last_source = source;
790
791 s3c2410_dma_devconfig(host->dma, source,
792 host->mem->start + host->sdidata);
793
794 if (!setup_ok) {
795 s3c2410_dma_config(host->dma, 4);
796 s3c2410_dma_set_buffdone_fn(host->dma,
797 s3cmci_dma_done_callback);
798 s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART);
799 setup_ok = 1;
800 }
801 }
802
803 static void s3cmci_send_command(struct s3cmci_host *host,
804 struct mmc_command *cmd)
805 {
806 u32 ccon, imsk;
807
808 imsk = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
809 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
810 S3C2410_SDIIMSK_RESPONSECRC;
811
812 enable_imask(host, imsk);
813
814 if (cmd->data)
815 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
816 else if (cmd->flags & MMC_RSP_PRESENT)
817 host->complete_what = COMPLETION_RSPFIN;
818 else
819 host->complete_what = COMPLETION_CMDSENT;
820
821 writel(cmd->arg, host->base + S3C2410_SDICMDARG);
822
823 ccon = cmd->opcode & S3C2410_SDICMDCON_INDEX;
824 ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
825
826 if (cmd->flags & MMC_RSP_PRESENT)
827 ccon |= S3C2410_SDICMDCON_WAITRSP;
828
829 if (cmd->flags & MMC_RSP_136)
830 ccon |= S3C2410_SDICMDCON_LONGRSP;
831
832 writel(ccon, host->base + S3C2410_SDICMDCON);
833 }
834
835 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
836 {
837 u32 dcon, imsk, stoptries = 3;
838
839 /* write DCON register */
840
841 if (!data) {
842 writel(0, host->base + S3C2410_SDIDCON);
843 return 0;
844 }
845
846 if ((data->blksz & 3) != 0) {
847 /* We cannot deal with unaligned blocks with more than
848 * one block being transfered. */
849
850 if (data->blocks > 1) {
851 pr_warning("%s: can't do non-word sized block transfers (blksz %d)\n", __func__, data->blksz);
852 return -EINVAL;
853 }
854 }
855
856 while (readl(host->base + S3C2410_SDIDSTA) &
857 (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
858
859 dbg(host, dbg_err,
860 "mci_setup_data() transfer stillin progress.\n");
861
862 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
863 s3cmci_reset(host);
864
865 if ((stoptries--) == 0) {
866 dbg_dumpregs(host, "DRF");
867 return -EINVAL;
868 }
869 }
870
871 dcon = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
872
873 if (host->dodma)
874 dcon |= S3C2410_SDIDCON_DMAEN;
875
876 if (host->bus_width == MMC_BUS_WIDTH_4)
877 dcon |= S3C2410_SDIDCON_WIDEBUS;
878
879 if (!(data->flags & MMC_DATA_STREAM))
880 dcon |= S3C2410_SDIDCON_BLOCKMODE;
881
882 if (data->flags & MMC_DATA_WRITE) {
883 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
884 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
885 }
886
887 if (data->flags & MMC_DATA_READ) {
888 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
889 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
890 }
891
892 if (host->is2440) {
893 dcon |= S3C2440_SDIDCON_DS_WORD;
894 dcon |= S3C2440_SDIDCON_DATSTART;
895 }
896
897 writel(dcon, host->base + S3C2410_SDIDCON);
898
899 /* write BSIZE register */
900
901 writel(data->blksz, host->base + S3C2410_SDIBSIZE);
902
903 /* add to IMASK register */
904 imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
905 S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
906
907 enable_imask(host, imsk);
908
909 /* write TIMER register */
910
911 if (host->is2440) {
912 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
913 } else {
914 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
915
916 /* FIX: set slow clock to prevent timeouts on read */
917 if (data->flags & MMC_DATA_READ)
918 writel(0xFF, host->base + S3C2410_SDIPRE);
919 }
920
921 return 0;
922 }
923
924 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
925
926 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
927 {
928 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
929
930 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
931
932 host->pio_sgptr = 0;
933 host->pio_bytes = 0;
934 host->pio_count = 0;
935 host->pio_active = rw ? XFER_WRITE : XFER_READ;
936
937 if (rw) {
938 do_pio_write(host);
939 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
940 } else {
941 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
942 | S3C2410_SDIIMSK_RXFIFOLAST);
943 }
944
945 return 0;
946 }
947
948 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
949 {
950 int dma_len, i;
951 int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
952
953 BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
954
955 s3cmci_dma_setup(host, rw ? S3C2410_DMASRC_MEM : S3C2410_DMASRC_HW);
956 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
957
958 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
959 (rw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
960
961 if (dma_len == 0)
962 return -ENOMEM;
963
964 host->dma_complete = 0;
965 host->dmatogo = dma_len;
966
967 for (i = 0; i < dma_len; i++) {
968 int res;
969
970 dbg(host, dbg_dma, "enqueue %i:%u@%u\n", i,
971 sg_dma_address(&data->sg[i]),
972 sg_dma_len(&data->sg[i]));
973
974 res = s3c2410_dma_enqueue(host->dma, (void *) host,
975 sg_dma_address(&data->sg[i]),
976 sg_dma_len(&data->sg[i]));
977
978 if (res) {
979 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_FLUSH);
980 return -EBUSY;
981 }
982 }
983
984 s3c2410_dma_ctrl(host->dma, S3C2410_DMAOP_START);
985
986 return 0;
987 }
988
989 static void s3cmci_send_request(struct mmc_host *mmc)
990 {
991 struct s3cmci_host *host = mmc_priv(mmc);
992 struct mmc_request *mrq = host->mrq;
993 struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
994
995 host->ccnt++;
996 prepare_dbgmsg(host, cmd, host->cmd_is_stop);
997
998 /* Clear command, data and fifo status registers
999 Fifo clear only necessary on 2440, but doesn't hurt on 2410
1000 */
1001 writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1002 writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1003 writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1004
1005 if (cmd->data) {
1006 int res = s3cmci_setup_data(host, cmd->data);
1007
1008 host->dcnt++;
1009
1010 if (res) {
1011 dbg(host, dbg_err, "setup data error %d\n", res);
1012 cmd->error = res;
1013 cmd->data->error = res;
1014
1015 mmc_request_done(mmc, mrq);
1016 return;
1017 }
1018
1019 if (host->dodma)
1020 res = s3cmci_prepare_dma(host, cmd->data);
1021 else
1022 res = s3cmci_prepare_pio(host, cmd->data);
1023
1024 if (res) {
1025 dbg(host, dbg_err, "data prepare error %d\n", res);
1026 cmd->error = res;
1027 cmd->data->error = res;
1028
1029 mmc_request_done(mmc, mrq);
1030 return;
1031 }
1032 }
1033
1034 /* Send command */
1035 s3cmci_send_command(host, cmd);
1036
1037 /* Enable Interrupt */
1038 enable_irq(host->irq);
1039 }
1040
1041 static int s3cmci_card_present(struct mmc_host *mmc)
1042 {
1043 struct s3cmci_host *host = mmc_priv(mmc);
1044 struct s3c24xx_mci_pdata *pdata = host->pdata;
1045 int ret;
1046
1047 if (pdata->gpio_detect == 0)
1048 return -ENOSYS;
1049
1050 ret = gpio_get_value(pdata->gpio_detect) ? 0 : 1;
1051 return ret ^ pdata->detect_invert;
1052 }
1053
1054 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1055 {
1056 struct s3cmci_host *host = mmc_priv(mmc);
1057
1058 host->status = "mmc request";
1059 host->cmd_is_stop = 0;
1060 host->mrq = mrq;
1061
1062 if (s3cmci_card_present(mmc) == 0) {
1063 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1064 host->mrq->cmd->error = -ENOMEDIUM;
1065 mmc_request_done(mmc, mrq);
1066 } else
1067 s3cmci_send_request(mmc);
1068 }
1069
1070 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1071 {
1072 u32 mci_psc;
1073
1074 /* Set clock */
1075 for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1076 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1077
1078 if (host->real_rate <= ios->clock)
1079 break;
1080 }
1081
1082 if (mci_psc > 255)
1083 mci_psc = 255;
1084
1085 host->prescaler = mci_psc;
1086 writel(host->prescaler, host->base + S3C2410_SDIPRE);
1087
1088 /* If requested clock is 0, real_rate will be 0, too */
1089 if (ios->clock == 0)
1090 host->real_rate = 0;
1091 }
1092
1093 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1094 {
1095 struct s3cmci_host *host = mmc_priv(mmc);
1096 u32 mci_con;
1097
1098 /* Set the power state */
1099
1100 mci_con = readl(host->base + S3C2410_SDICON);
1101
1102 switch (ios->power_mode) {
1103 case MMC_POWER_ON:
1104 case MMC_POWER_UP:
1105 s3c2410_gpio_cfgpin(S3C2410_GPE(5), S3C2410_GPE5_SDCLK);
1106 s3c2410_gpio_cfgpin(S3C2410_GPE(6), S3C2410_GPE6_SDCMD);
1107 s3c2410_gpio_cfgpin(S3C2410_GPE(7), S3C2410_GPE7_SDDAT0);
1108 s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1);
1109 s3c2410_gpio_cfgpin(S3C2410_GPE(9), S3C2410_GPE9_SDDAT2);
1110 s3c2410_gpio_cfgpin(S3C2410_GPE(10), S3C2410_GPE10_SDDAT3);
1111
1112 if (host->pdata->set_power)
1113 host->pdata->set_power(ios->power_mode, ios->vdd);
1114
1115 if (!host->is2440)
1116 mci_con |= S3C2410_SDICON_FIFORESET;
1117
1118 break;
1119
1120 case MMC_POWER_OFF:
1121 default:
1122 gpio_direction_output(S3C2410_GPE(5), 0);
1123
1124 if (host->is2440)
1125 mci_con |= S3C2440_SDICON_SDRESET;
1126
1127 if (host->pdata->set_power)
1128 host->pdata->set_power(ios->power_mode, ios->vdd);
1129
1130 break;
1131 }
1132
1133 s3cmci_set_clk(host, ios);
1134
1135 /* Set CLOCK_ENABLE */
1136 if (ios->clock)
1137 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1138 else
1139 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1140
1141 writel(mci_con, host->base + S3C2410_SDICON);
1142
1143 if ((ios->power_mode == MMC_POWER_ON) ||
1144 (ios->power_mode == MMC_POWER_UP)) {
1145 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1146 host->real_rate/1000, ios->clock/1000);
1147 } else {
1148 dbg(host, dbg_conf, "powered down.\n");
1149 }
1150
1151 host->bus_width = ios->bus_width;
1152 }
1153
1154 static void s3cmci_reset(struct s3cmci_host *host)
1155 {
1156 u32 con = readl(host->base + S3C2410_SDICON);
1157
1158 con |= S3C2440_SDICON_SDRESET;
1159 writel(con, host->base + S3C2410_SDICON);
1160 }
1161
1162 static int s3cmci_get_ro(struct mmc_host *mmc)
1163 {
1164 struct s3cmci_host *host = mmc_priv(mmc);
1165 struct s3c24xx_mci_pdata *pdata = host->pdata;
1166 int ret;
1167
1168 if (pdata->gpio_wprotect == 0)
1169 return 0;
1170
1171 ret = s3c2410_gpio_getpin(pdata->gpio_wprotect);
1172
1173 if (pdata->wprotect_invert)
1174 ret = !ret;
1175
1176 return ret;
1177 }
1178
1179 static struct mmc_host_ops s3cmci_ops = {
1180 .request = s3cmci_request,
1181 .set_ios = s3cmci_set_ios,
1182 .get_ro = s3cmci_get_ro,
1183 .get_cd = s3cmci_card_present,
1184 };
1185
1186 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1187 /* This is currently here to avoid a number of if (host->pdata)
1188 * checks. Any zero fields to ensure reaonable defaults are picked. */
1189 };
1190
1191 #ifdef CONFIG_CPU_FREQ
1192
1193 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1194 unsigned long val, void *data)
1195 {
1196 struct s3cmci_host *host;
1197 struct mmc_host *mmc;
1198 unsigned long newclk;
1199 unsigned long flags;
1200
1201 host = container_of(nb, struct s3cmci_host, freq_transition);
1202 newclk = clk_get_rate(host->clk);
1203 mmc = host->mmc;
1204
1205 if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1206 (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1207 spin_lock_irqsave(&mmc->lock, flags);
1208
1209 host->clk_rate = newclk;
1210
1211 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1212 mmc->ios.clock != 0)
1213 s3cmci_set_clk(host, &mmc->ios);
1214
1215 spin_unlock_irqrestore(&mmc->lock, flags);
1216 }
1217
1218 return 0;
1219 }
1220
1221 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1222 {
1223 host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1224
1225 return cpufreq_register_notifier(&host->freq_transition,
1226 CPUFREQ_TRANSITION_NOTIFIER);
1227 }
1228
1229 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1230 {
1231 cpufreq_unregister_notifier(&host->freq_transition,
1232 CPUFREQ_TRANSITION_NOTIFIER);
1233 }
1234
1235 #else
1236 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1237 {
1238 return 0;
1239 }
1240
1241 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1242 {
1243 }
1244 #endif
1245
1246
1247 static int __devinit s3cmci_probe(struct platform_device *pdev)
1248 {
1249 struct s3cmci_host *host;
1250 struct mmc_host *mmc;
1251 int ret;
1252 int is2440;
1253 int i;
1254
1255 is2440 = platform_get_device_id(pdev)->driver_data;
1256
1257 mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1258 if (!mmc) {
1259 ret = -ENOMEM;
1260 goto probe_out;
1261 }
1262
1263 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1264 ret = gpio_request(i, dev_name(&pdev->dev));
1265 if (ret) {
1266 dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1267
1268 for (i--; i >= S3C2410_GPE(5); i--)
1269 gpio_free(i);
1270
1271 goto probe_free_host;
1272 }
1273 }
1274
1275 host = mmc_priv(mmc);
1276 host->mmc = mmc;
1277 host->pdev = pdev;
1278 host->is2440 = is2440;
1279
1280 host->pdata = pdev->dev.platform_data;
1281 if (!host->pdata) {
1282 pdev->dev.platform_data = &s3cmci_def_pdata;
1283 host->pdata = &s3cmci_def_pdata;
1284 }
1285
1286 spin_lock_init(&host->complete_lock);
1287 tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1288
1289 if (is2440) {
1290 host->sdiimsk = S3C2440_SDIIMSK;
1291 host->sdidata = S3C2440_SDIDATA;
1292 host->clk_div = 1;
1293 } else {
1294 host->sdiimsk = S3C2410_SDIIMSK;
1295 host->sdidata = S3C2410_SDIDATA;
1296 host->clk_div = 2;
1297 }
1298
1299 host->dodma = 0;
1300 host->complete_what = COMPLETION_NONE;
1301 host->pio_active = XFER_NONE;
1302
1303 host->dma = S3CMCI_DMA;
1304
1305 host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306 if (!host->mem) {
1307 dev_err(&pdev->dev,
1308 "failed to get io memory region resouce.\n");
1309
1310 ret = -ENOENT;
1311 goto probe_free_gpio;
1312 }
1313
1314 host->mem = request_mem_region(host->mem->start,
1315 resource_size(host->mem), pdev->name);
1316
1317 if (!host->mem) {
1318 dev_err(&pdev->dev, "failed to request io memory region.\n");
1319 ret = -ENOENT;
1320 goto probe_free_gpio;
1321 }
1322
1323 host->base = ioremap(host->mem->start, resource_size(host->mem));
1324 if (!host->base) {
1325 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1326 ret = -EINVAL;
1327 goto probe_free_mem_region;
1328 }
1329
1330 host->irq = platform_get_irq(pdev, 0);
1331 if (host->irq == 0) {
1332 dev_err(&pdev->dev, "failed to get interrupt resouce.\n");
1333 ret = -EINVAL;
1334 goto probe_iounmap;
1335 }
1336
1337 if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1338 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1339 ret = -ENOENT;
1340 goto probe_iounmap;
1341 }
1342
1343 /* We get spurious interrupts even when we have set the IMSK
1344 * register to ignore everything, so use disable_irq() to make
1345 * ensure we don't lock the system with un-serviceable requests. */
1346
1347 disable_irq(host->irq);
1348
1349 if (host->pdata->gpio_detect) {
1350 ret = gpio_request(host->pdata->gpio_detect, "s3cmci detect");
1351 if (ret) {
1352 dev_err(&pdev->dev, "failed to get detect gpio\n");
1353 goto probe_free_irq;
1354 }
1355 }
1356
1357 host->irq_cd = s3c2410_gpio_getirq(host->pdata->gpio_detect);
1358
1359 if (host->irq_cd >= 0) {
1360 if (request_irq(host->irq_cd, s3cmci_irq_cd,
1361 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1362 DRIVER_NAME, host)) {
1363 dev_err(&pdev->dev, "can't get card detect irq.\n");
1364 ret = -ENOENT;
1365 goto probe_free_gpio_cd;
1366 }
1367 } else {
1368 dev_warn(&pdev->dev, "host detect has no irq available\n");
1369 gpio_direction_input(host->pdata->gpio_detect);
1370 }
1371
1372 if (host->pdata->gpio_wprotect) {
1373 ret = gpio_request(host->pdata->gpio_wprotect, "s3cmci wp");
1374 if (ret) {
1375 dev_err(&pdev->dev, "failed to get writeprotect\n");
1376 goto probe_free_irq_cd;
1377 }
1378
1379 gpio_direction_input(host->pdata->gpio_wprotect);
1380 }
1381
1382 if (s3c2410_dma_request(S3CMCI_DMA, &s3cmci_dma_client, NULL) < 0) {
1383 dev_err(&pdev->dev, "unable to get DMA channel.\n");
1384 ret = -EBUSY;
1385 goto probe_free_gpio_wp;
1386 }
1387
1388 host->clk = clk_get(&pdev->dev, "sdi");
1389 if (IS_ERR(host->clk)) {
1390 dev_err(&pdev->dev, "failed to find clock source.\n");
1391 ret = PTR_ERR(host->clk);
1392 host->clk = NULL;
1393 goto probe_free_host;
1394 }
1395
1396 ret = clk_enable(host->clk);
1397 if (ret) {
1398 dev_err(&pdev->dev, "failed to enable clock source.\n");
1399 goto clk_free;
1400 }
1401
1402 host->clk_rate = clk_get_rate(host->clk);
1403
1404 mmc->ops = &s3cmci_ops;
1405 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1406 mmc->caps = MMC_CAP_4_BIT_DATA;
1407 mmc->f_min = host->clk_rate / (host->clk_div * 256);
1408 mmc->f_max = host->clk_rate / host->clk_div;
1409
1410 if (host->pdata->ocr_avail)
1411 mmc->ocr_avail = host->pdata->ocr_avail;
1412
1413 mmc->max_blk_count = 4095;
1414 mmc->max_blk_size = 4095;
1415 mmc->max_req_size = 4095 * 512;
1416 mmc->max_seg_size = mmc->max_req_size;
1417
1418 mmc->max_phys_segs = 128;
1419 mmc->max_hw_segs = 128;
1420
1421 dbg(host, dbg_debug,
1422 "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%u.\n",
1423 (host->is2440?"2440":""),
1424 host->base, host->irq, host->irq_cd, host->dma);
1425
1426 ret = s3cmci_cpufreq_register(host);
1427 if (ret) {
1428 dev_err(&pdev->dev, "failed to register cpufreq\n");
1429 goto free_dmabuf;
1430 }
1431
1432 ret = mmc_add_host(mmc);
1433 if (ret) {
1434 dev_err(&pdev->dev, "failed to add mmc host.\n");
1435 goto free_cpufreq;
1436 }
1437
1438 platform_set_drvdata(pdev, mmc);
1439 dev_info(&pdev->dev, "initialisation done.\n");
1440
1441 return 0;
1442
1443 free_cpufreq:
1444 s3cmci_cpufreq_deregister(host);
1445
1446 free_dmabuf:
1447 clk_disable(host->clk);
1448
1449 clk_free:
1450 clk_put(host->clk);
1451
1452 probe_free_gpio_wp:
1453 if (host->pdata->gpio_wprotect)
1454 gpio_free(host->pdata->gpio_wprotect);
1455
1456 probe_free_gpio_cd:
1457 if (host->pdata->gpio_detect)
1458 gpio_free(host->pdata->gpio_detect);
1459
1460 probe_free_irq_cd:
1461 if (host->irq_cd >= 0)
1462 free_irq(host->irq_cd, host);
1463
1464 probe_free_irq:
1465 free_irq(host->irq, host);
1466
1467 probe_iounmap:
1468 iounmap(host->base);
1469
1470 probe_free_mem_region:
1471 release_mem_region(host->mem->start, resource_size(host->mem));
1472
1473 probe_free_gpio:
1474 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1475 gpio_free(i);
1476
1477 probe_free_host:
1478 mmc_free_host(mmc);
1479
1480 probe_out:
1481 return ret;
1482 }
1483
1484 static void s3cmci_shutdown(struct platform_device *pdev)
1485 {
1486 struct mmc_host *mmc = platform_get_drvdata(pdev);
1487 struct s3cmci_host *host = mmc_priv(mmc);
1488
1489 if (host->irq_cd >= 0)
1490 free_irq(host->irq_cd, host);
1491
1492 s3cmci_cpufreq_deregister(host);
1493 mmc_remove_host(mmc);
1494 clk_disable(host->clk);
1495 }
1496
1497 static int __devexit s3cmci_remove(struct platform_device *pdev)
1498 {
1499 struct mmc_host *mmc = platform_get_drvdata(pdev);
1500 struct s3cmci_host *host = mmc_priv(mmc);
1501 struct s3c24xx_mci_pdata *pd = host->pdata;
1502 int i;
1503
1504 s3cmci_shutdown(pdev);
1505
1506 clk_put(host->clk);
1507
1508 tasklet_disable(&host->pio_tasklet);
1509 s3c2410_dma_free(S3CMCI_DMA, &s3cmci_dma_client);
1510
1511 free_irq(host->irq, host);
1512
1513 if (pd->gpio_wprotect)
1514 gpio_free(pd->gpio_wprotect);
1515
1516 if (pd->gpio_detect)
1517 gpio_free(pd->gpio_detect);
1518
1519 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1520 gpio_free(i);
1521
1522
1523 iounmap(host->base);
1524 release_mem_region(host->mem->start, resource_size(host->mem));
1525
1526 mmc_free_host(mmc);
1527 return 0;
1528 }
1529
1530 static struct platform_device_id s3cmci_driver_ids[] = {
1531 {
1532 .name = "s3c2410-sdi",
1533 .driver_data = 0,
1534 }, {
1535 .name = "s3c2412-sdi",
1536 .driver_data = 1,
1537 }, {
1538 .name = "s3c2440-sdi",
1539 .driver_data = 1,
1540 },
1541 { }
1542 };
1543
1544 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1545
1546
1547 #ifdef CONFIG_PM
1548
1549 static int s3cmci_suspend(struct device *dev)
1550 {
1551 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1552 struct pm_message event = { PM_EVENT_SUSPEND };
1553
1554 return mmc_suspend_host(mmc, event);
1555 }
1556
1557 static int s3cmci_resume(struct device *dev)
1558 {
1559 struct mmc_host *mmc = platform_get_drvdata(to_platform_device(dev));
1560
1561 return mmc_resume_host(mmc);
1562 }
1563
1564 static struct dev_pm_ops s3cmci_pm = {
1565 .suspend = s3cmci_suspend,
1566 .resume = s3cmci_resume,
1567 };
1568
1569 #define s3cmci_pm_ops &s3cmci_pm
1570 #else /* CONFIG_PM */
1571 #define s3cmci_pm_ops NULL
1572 #endif /* CONFIG_PM */
1573
1574
1575 static struct platform_driver s3cmci_driver = {
1576 .driver = {
1577 .name = "s3c-sdi",
1578 .owner = THIS_MODULE,
1579 .pm = s3cmci_pm_ops,
1580 },
1581 .id_table = s3cmci_driver_ids,
1582 .probe = s3cmci_probe,
1583 .remove = __devexit_p(s3cmci_remove),
1584 .shutdown = s3cmci_shutdown,
1585 };
1586
1587 static int __init s3cmci_init(void)
1588 {
1589 return platform_driver_register(&s3cmci_driver);
1590 }
1591
1592 static void __exit s3cmci_exit(void)
1593 {
1594 platform_driver_unregister(&s3cmci_driver);
1595 }
1596
1597 module_init(s3cmci_init);
1598 module_exit(s3cmci_exit);
1599
1600 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1601 MODULE_LICENSE("GPL v2");
1602 MODULE_AUTHOR("Thomas Kleffel <tk@maintech.de>, Ben Dooks <ben-linux@fluff.org>");
linux 2.6 git repository for openrd