arch/powerpc/platforms/85xx/mpc85xx_cds.c

   1 /*
   2  * MPC85xx setup and early boot code plus other random bits.
   3  *
   4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
   5  *
   6  * Copyright 2005 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/initrd.h>
  26 #include <linux/module.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/fsl_devices.h>
  29
  30 #include <asm/system.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/page.h>
  33 #include <asm/atomic.h>
  34 #include <asm/time.h>
  35 #include <asm/io.h>
  36 #include <asm/machdep.h>
  37 #include <asm/ipic.h>
  38 #include <asm/pci-bridge.h>
  39 #include <asm/mpc85xx.h>
  40 #include <asm/irq.h>
  41 #include <mm/mmu_decl.h>
  42 #include <asm/prom.h>
  43 #include <asm/udbg.h>
  44 #include <asm/mpic.h>
  45 #include <asm/i8259.h>
  46
  47 #include <sysdev/fsl_soc.h>
  48 #include <sysdev/fsl_pci.h>
  49
  50 static int cds_pci_slot = 2;
  51 static volatile u8 *cadmus;
  52
  53 #ifdef CONFIG_PCI
  54
  55 #define ARCADIA_HOST_BRIDGE_IDSEL       17
  56 #define ARCADIA_2ND_BRIDGE_IDSEL        3
  57
  58 static int mpc85xx_exclude_device(struct pci_controller *hose,
  59                                   u_char bus, u_char devfn)
  60 {
  61         /* We explicitly do not go past the Tundra 320 Bridge */
  62         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  63                 return PCIBIOS_DEVICE_NOT_FOUND;
  64         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
  65                 return PCIBIOS_DEVICE_NOT_FOUND;
  66         else
  67                 return PCIBIOS_SUCCESSFUL;
  68 }
  69
  70 static void mpc85xx_cds_restart(char *cmd)
  71 {
  72         struct pci_dev *dev;
  73         u_char tmp;
  74
  75         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
  76                                         NULL))) {
  77
  78                 /* Use the VIA Super Southbridge to force a PCI reset */
  79                 pci_read_config_byte(dev, 0x47, &tmp);
  80                 pci_write_config_byte(dev, 0x47, tmp | 1);
  81
  82                 /* Flush the outbound PCI write queues */
  83                 pci_read_config_byte(dev, 0x47, &tmp);
  84
  85                 /*
  86                  *  At this point, the harware reset should have triggered.
  87                  *  However, if it doesn't work for some mysterious reason,
  88                  *  just fall through to the default reset below.
  89                  */
  90
  91                 pci_dev_put(dev);
  92         }
  93
  94         /*
  95          *  If we can't find the VIA chip (maybe the P2P bridge is disabled)
  96          *  or the VIA chip reset didn't work, just use the default reset.
  97          */
  98         fsl_rstcr_restart(NULL);
  99 }
 100
 101 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
 102 {
 103         u_char c;
 104         if (dev->vendor == PCI_VENDOR_ID_VIA) {
 105                 switch (dev->device) {
 106                 case PCI_DEVICE_ID_VIA_82C586_1:
 107                         /*
 108                          * U-Boot does not set the enable bits
 109                          * for the IDE device. Force them on here.
 110                          */
 111                         pci_read_config_byte(dev, 0x40, &c);
 112                         c |= 0x03; /* IDE: Chip Enable Bits */
 113                         pci_write_config_byte(dev, 0x40, c);
 114
 115                         /*
 116                          * Since only primary interface works, force the
 117                          * IDE function to standard primary IDE interrupt
 118                          * w/ 8259 offset
 119                          */
 120                         dev->irq = 14;
 121                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 122                         break;
 123                 /*
 124                  * Force legacy USB interrupt routing
 125                  */
 126                 case PCI_DEVICE_ID_VIA_82C586_2:
 127                 /* There are two USB controllers.
 128                  * Identify them by functon number
 129                  */
 130                         if (PCI_FUNC(dev->devfn) == 3)
 131                                 dev->irq = 11;
 132                         else
 133                                 dev->irq = 10;
 134                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 135                 default:
 136                         break;
 137                 }
 138         }
 139 }
 140
 141 static void __devinit skip_fake_bridge(struct pci_dev *dev)
 142 {
 143         /* Make it an error to skip the fake bridge
 144          * in pci_setup_device() in probe.c */
 145         dev->hdr_type = 0x7f;
 146 }
 147 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
 148 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
 149 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
 150
 151 #ifdef CONFIG_PPC_I8259
 152 static void mpc85xx_8259_cascade_handler(unsigned int irq,
 153                                          struct irq_desc *desc)
 154 {
 155         unsigned int cascade_irq = i8259_irq();
 156
 157         if (cascade_irq != NO_IRQ)
 158                 /* handle an interrupt from the 8259 */
 159                 generic_handle_irq(cascade_irq);
 160
 161         /* check for any interrupts from the shared IRQ line */
 162         handle_fasteoi_irq(irq, desc);
 163 }
 164
 165 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
 166 {
 167         return IRQ_HANDLED;
 168 }
 169
 170 static struct irqaction mpc85xxcds_8259_irqaction = {
 171         .handler = mpc85xx_8259_cascade_action,
 172         .flags = IRQF_SHARED,
 173         .mask = CPU_MASK_NONE,
 174         .name = "8259 cascade",
 175 };
 176 #endif /* PPC_I8259 */
 177 #endif /* CONFIG_PCI */
 178
 179 static void __init mpc85xx_cds_pic_init(void)
 180 {
 181         struct mpic *mpic;
 182         struct resource r;
 183         struct device_node *np = NULL;
 184
 185         np = of_find_node_by_type(np, "open-pic");
 186
 187         if (np == NULL) {
 188                 printk(KERN_ERR "Could not find open-pic node\n");
 189                 return;
 190         }
 191
 192         if (of_address_to_resource(np, 0, &r)) {
 193                 printk(KERN_ERR "Failed to map mpic register space\n");
 194                 of_node_put(np);
 195                 return;
 196         }
 197
 198         mpic = mpic_alloc(np, r.start,
 199                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 200                         0, 256, " OpenPIC  ");
 201         BUG_ON(mpic == NULL);
 202
 203         /* Return the mpic node */
 204         of_node_put(np);
 205
 206         mpic_init(mpic);
 207 }
 208
 209 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
 210 static int mpc85xx_cds_8259_attach(void)
 211 {
 212         int ret;
 213         struct device_node *np = NULL;
 214         struct device_node *cascade_node = NULL;
 215         int cascade_irq;
 216
 217         if (!machine_is(mpc85xx_cds))
 218                 return 0;
 219
 220         /* Initialize the i8259 controller */
 221         for_each_node_by_type(np, "interrupt-controller")
 222                 if (of_device_is_compatible(np, "chrp,iic")) {
 223                         cascade_node = np;
 224                         break;
 225                 }
 226
 227         if (cascade_node == NULL) {
 228                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
 229                 return -ENODEV;
 230         }
 231
 232         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 233         if (cascade_irq == NO_IRQ) {
 234                 printk(KERN_ERR "Failed to map cascade interrupt\n");
 235                 return -ENXIO;
 236         }
 237
 238         i8259_init(cascade_node, 0);
 239         of_node_put(cascade_node);
 240
 241         /*
 242          *  Hook the interrupt to make sure desc->action is never NULL.
 243          *  This is required to ensure that the interrupt does not get
 244          *  disabled when the last user of the shared IRQ line frees their
 245          *  interrupt.
 246          */
 247         if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
 248                 printk(KERN_ERR "Failed to setup cascade interrupt\n");
 249                 return ret;
 250         }
 251
 252         /* Success. Connect our low-level cascade handler. */
 253         set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
 254
 255         return 0;
 256 }
 257
 258 device_initcall(mpc85xx_cds_8259_attach);
 259
 260 #endif /* CONFIG_PPC_I8259 */
 261
 262 /*
 263  * Setup the architecture
 264  */
 265 static void __init mpc85xx_cds_setup_arch(void)
 266 {
 267 #ifdef CONFIG_PCI
 268         struct device_node *np;
 269 #endif
 270
 271         if (ppc_md.progress)
 272                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
 273
 274         cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
 275         cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
 276
 277         if (ppc_md.progress) {
 278                 char buf[40];
 279                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
 280                                 cadmus[CM_VER], cds_pci_slot);
 281                 ppc_md.progress(buf, 0);
 282         }
 283
 284 #ifdef CONFIG_PCI
 285         for_each_node_by_type(np, "pci") {
 286                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
 287                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
 288                         struct resource rsrc;
 289                         of_address_to_resource(np, 0, &rsrc);
 290                         if ((rsrc.start & 0xfffff) == 0x8000)
 291                                 fsl_add_bridge(np, 1);
 292                         else
 293                                 fsl_add_bridge(np, 0);
 294                 }
 295         }
 296
 297         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
 298         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 299 #endif
 300 }
 301
 302 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
 303 {
 304         uint pvid, svid, phid1;
 305         uint memsize = total_memory;
 306
 307         pvid = mfspr(SPRN_PVR);
 308         svid = mfspr(SPRN_SVR);
 309
 310         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 311         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]);
 312         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 313         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 314
 315         /* Display cpu Pll setting */
 316         phid1 = mfspr(SPRN_HID1);
 317         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 318
 319         /* Display the amount of memory */
 320         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 321 }
 322
 323
 324 /*
 325  * Called very early, device-tree isn't unflattened
 326  */
 327 static int __init mpc85xx_cds_probe(void)
 328 {
 329         unsigned long root = of_get_flat_dt_root();
 330
 331         return of_flat_dt_is_compatible(root, "MPC85xxCDS");
 332 }
 333
 334 define_machine(mpc85xx_cds) {
 335         .name           = "MPC85xx CDS",
 336         .probe          = mpc85xx_cds_probe,
 337         .setup_arch     = mpc85xx_cds_setup_arch,
 338         .init_IRQ       = mpc85xx_cds_pic_init,
 339         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
 340         .get_irq        = mpic_get_irq,
 341 #ifdef CONFIG_PCI
 342         .restart        = mpc85xx_cds_restart,
 343         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 344 #else
 345         .restart        = fsl_rstcr_restart,
 346 #endif
 347         .calibrate_decr = generic_calibrate_decr,
 348         .progress       = udbg_progress,
 349 };