Merge git://oak/home/sfr/kernels/iseries/work
[linux-2.6/linux-2.6-openrd.git] / include / asm-ppc / cache.h
blob7a157d0f4b5fd646294fff69827f4746ef96e085
1 /*
2 * include/asm-ppc/cache.h
3 */
4 #ifdef __KERNEL__
5 #ifndef __ARCH_PPC_CACHE_H
6 #define __ARCH_PPC_CACHE_H
8 #include <linux/config.h>
10 /* bytes per L1 cache line */
11 #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
12 #define L1_CACHE_SHIFT 4
13 #define MAX_COPY_PREFETCH 1
14 #elif defined(CONFIG_PPC64BRIDGE)
15 #define L1_CACHE_SHIFT 7
16 #define MAX_COPY_PREFETCH 1
17 #else
18 #define L1_CACHE_SHIFT 5
19 #define MAX_COPY_PREFETCH 4
20 #endif
22 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
24 #define SMP_CACHE_BYTES L1_CACHE_BYTES
25 #define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
27 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
28 #define L1_CACHE_PAGES 8
30 #ifndef __ASSEMBLY__
31 extern void clean_dcache_range(unsigned long start, unsigned long stop);
32 extern void flush_dcache_range(unsigned long start, unsigned long stop);
33 extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
34 extern void flush_dcache_all(void);
35 #endif /* __ASSEMBLY__ */
37 /* prep registers for L2 */
38 #define CACHECRBA 0x80000823 /* Cache configuration register address */
39 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
40 #define L2CACHE_512KB 0x00 /* 512KB */
41 #define L2CACHE_256KB 0x01 /* 256KB */
42 #define L2CACHE_1MB 0x02 /* 1MB */
43 #define L2CACHE_NONE 0x03 /* NONE */
44 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
46 #ifdef CONFIG_8xx
47 /* Cache control on the MPC8xx is provided through some additional
48 * special purpose registers.
50 #define SPRN_IC_CST 560 /* Instruction cache control/status */
51 #define SPRN_IC_ADR 561 /* Address needed for some commands */
52 #define SPRN_IC_DAT 562 /* Read-only data register */
53 #define SPRN_DC_CST 568 /* Data cache control/status */
54 #define SPRN_DC_ADR 569 /* Address needed for some commands */
55 #define SPRN_DC_DAT 570 /* Read-only data register */
57 /* Commands. Only the first few are available to the instruction cache.
59 #define IDC_ENABLE 0x02000000 /* Cache enable */
60 #define IDC_DISABLE 0x04000000 /* Cache disable */
61 #define IDC_LDLCK 0x06000000 /* Load and lock */
62 #define IDC_UNLINE 0x08000000 /* Unlock line */
63 #define IDC_UNALL 0x0a000000 /* Unlock all */
64 #define IDC_INVALL 0x0c000000 /* Invalidate all */
66 #define DC_FLINE 0x0e000000 /* Flush data cache line */
67 #define DC_SFWT 0x01000000 /* Set forced writethrough mode */
68 #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
69 #define DC_SLES 0x05000000 /* Set little endian swap mode */
70 #define DC_CLES 0x07000000 /* Clear little endian swap mode */
72 /* Status.
74 #define IDC_ENABLED 0x80000000 /* Cache is enabled */
75 #define IDC_CERR1 0x00200000 /* Cache error 1 */
76 #define IDC_CERR2 0x00100000 /* Cache error 2 */
77 #define IDC_CERR3 0x00080000 /* Cache error 3 */
79 #define DC_DFWT 0x40000000 /* Data cache is forced write through */
80 #define DC_LES 0x20000000 /* Caches are little endian mode */
81 #endif /* CONFIG_8xx */
83 #endif
84 #endif /* __KERNEL__ */