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drm/i915: add GEM GTT mapping support
[linux-2.6/linux-2.6-openrd.git] / drivers / net / wan / farsync.c
blob9557ad078ab802e711496516d950f2d04cff3727
1 /*
2 * FarSync WAN driver for Linux (2.6.x kernel version)
3 *
4 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
5 *
6 * Copyright (C) 2001-2004 FarSite Communications Ltd.
7 * www.farsite.co.uk
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 *
14 * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk>
15 * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/version.h>
21 #include <linux/pci.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/if.h>
25 #include <linux/hdlc.h>
26 #include <asm/io.h>
27 #include <asm/uaccess.h>
28
29 #include "farsync.h"
30
31 /*
32 * Module info
33 */
34 MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>");
35 MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd.");
36 MODULE_LICENSE("GPL");
37
38 /* Driver configuration and global parameters
39 * ==========================================
40 */
41
42 /* Number of ports (per card) and cards supported
43 */
44 #define FST_MAX_PORTS 4
45 #define FST_MAX_CARDS 32
46
47 /* Default parameters for the link
48 */
49 #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is
50 * useful */
51 #define FST_TXQ_DEPTH 16 /* This one is for the buffering
52 * of frames on the way down to the card
53 * so that we can keep the card busy
54 * and maximise throughput
55 */
56 #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control
57 * network layer */
58 #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow
59 * control from network layer */
60 #define FST_MAX_MTU 8000 /* Huge but possible */
61 #define FST_DEF_MTU 1500 /* Common sane value */
62
63 #define FST_TX_TIMEOUT (2*HZ)
64
65 #ifdef ARPHRD_RAWHDLC
66 #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */
67 #else
68 #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */
69 #endif
70
71 /*
72 * Modules parameters and associated varaibles
73 */
74 static int fst_txq_low = FST_LOW_WATER_MARK;
75 static int fst_txq_high = FST_HIGH_WATER_MARK;
76 static int fst_max_reads = 7;
77 static int fst_excluded_cards = 0;
78 static int fst_excluded_list[FST_MAX_CARDS];
79
80 module_param(fst_txq_low, int, 0);
81 module_param(fst_txq_high, int, 0);
82 module_param(fst_max_reads, int, 0);
83 module_param(fst_excluded_cards, int, 0);
84 module_param_array(fst_excluded_list, int, NULL, 0);
85
86 /* Card shared memory layout
87 * =========================
88 */
89 #pragma pack(1)
90
91 /* This information is derived in part from the FarSite FarSync Smc.h
92 * file. Unfortunately various name clashes and the non-portability of the
93 * bit field declarations in that file have meant that I have chosen to
94 * recreate the information here.
95 *
96 * The SMC (Shared Memory Configuration) has a version number that is
97 * incremented every time there is a significant change. This number can
98 * be used to check that we have not got out of step with the firmware
99 * contained in the .CDE files.
100 */
101 #define SMC_VERSION 24
102
103 #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */
104
105 #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main
106 * configuration structure */
107 #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA
108 * buffers */
109
110 #define LEN_TX_BUFFER 8192 /* Size of packet buffers */
111 #define LEN_RX_BUFFER 8192
112
113 #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */
114 #define LEN_SMALL_RX_BUFFER 256
115
116 #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */
117 #define NUM_RX_BUFFER 8
118
119 /* Interrupt retry time in milliseconds */
120 #define INT_RETRY_TIME 2
121
122 /* The Am186CH/CC processors support a SmartDMA mode using circular pools
123 * of buffer descriptors. The structure is almost identical to that used
124 * in the LANCE Ethernet controllers. Details available as PDF from the
125 * AMD web site: http://www.amd.com/products/epd/processors/\
126 * 2.16bitcont/3.am186cxfa/a21914/21914.pdf
127 */
128 struct txdesc { /* Transmit descriptor */
129 volatile u16 ladr; /* Low order address of packet. This is a
130 * linear address in the Am186 memory space
131 */
132 volatile u8 hadr; /* High order address. Low 4 bits only, high 4
133 * bits must be zero
134 */
135 volatile u8 bits; /* Status and config */
136 volatile u16 bcnt; /* 2s complement of packet size in low 15 bits.
137 * Transmit terminal count interrupt enable in
138 * top bit.
139 */
140 u16 unused; /* Not used in Tx */
141 };
142
143 struct rxdesc { /* Receive descriptor */
144 volatile u16 ladr; /* Low order address of packet */
145 volatile u8 hadr; /* High order address */
146 volatile u8 bits; /* Status and config */
147 volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits.
148 * Receive terminal count interrupt enable in
149 * top bit.
150 */
151 volatile u16 mcnt; /* Message byte count (15 bits) */
152 };
153
154 /* Convert a length into the 15 bit 2's complement */
155 /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */
156 /* Since we need to set the high bit to enable the completion interrupt this
157 * can be made a lot simpler
158 */
159 #define cnv_bcnt(len) (-(len))
160
161 /* Status and config bits for the above */
162 #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */
163 #define TX_STP 0x02 /* Tx: start of packet */
164 #define TX_ENP 0x01 /* Tx: end of packet */
165 #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */
166 #define RX_FRAM 0x20 /* Rx: framing error */
167 #define RX_OFLO 0x10 /* Rx: overflow error */
168 #define RX_CRC 0x08 /* Rx: CRC error */
169 #define RX_HBUF 0x04 /* Rx: buffer error */
170 #define RX_STP 0x02 /* Rx: start of packet */
171 #define RX_ENP 0x01 /* Rx: end of packet */
172
173 /* Interrupts from the card are caused by various events which are presented
174 * in a circular buffer as several events may be processed on one physical int
175 */
176 #define MAX_CIRBUFF 32
177
178 struct cirbuff {
179 u8 rdindex; /* read, then increment and wrap */
180 u8 wrindex; /* write, then increment and wrap */
181 u8 evntbuff[MAX_CIRBUFF];
182 };
183
184 /* Interrupt event codes.
185 * Where appropriate the two low order bits indicate the port number
186 */
187 #define CTLA_CHG 0x18 /* Control signal changed */
188 #define CTLB_CHG 0x19
189 #define CTLC_CHG 0x1A
190 #define CTLD_CHG 0x1B
191
192 #define INIT_CPLT 0x20 /* Initialisation complete */
193 #define INIT_FAIL 0x21 /* Initialisation failed */
194
195 #define ABTA_SENT 0x24 /* Abort sent */
196 #define ABTB_SENT 0x25
197 #define ABTC_SENT 0x26
198 #define ABTD_SENT 0x27
199
200 #define TXA_UNDF 0x28 /* Transmission underflow */
201 #define TXB_UNDF 0x29
202 #define TXC_UNDF 0x2A
203 #define TXD_UNDF 0x2B
204
205 #define F56_INT 0x2C
206 #define M32_INT 0x2D
207
208 #define TE1_ALMA 0x30
209
210 /* Port physical configuration. See farsync.h for field values */
211 struct port_cfg {
212 u16 lineInterface; /* Physical interface type */
213 u8 x25op; /* Unused at present */
214 u8 internalClock; /* 1 => internal clock, 0 => external */
215 u8 transparentMode; /* 1 => on, 0 => off */
216 u8 invertClock; /* 0 => normal, 1 => inverted */
217 u8 padBytes[6]; /* Padding */
218 u32 lineSpeed; /* Speed in bps */
219 };
220
221 /* TE1 port physical configuration */
222 struct su_config {
223 u32 dataRate;
224 u8 clocking;
225 u8 framing;
226 u8 structure;
227 u8 interface;
228 u8 coding;
229 u8 lineBuildOut;
230 u8 equalizer;
231 u8 transparentMode;
232 u8 loopMode;
233 u8 range;
234 u8 txBufferMode;
235 u8 rxBufferMode;
236 u8 startingSlot;
237 u8 losThreshold;
238 u8 enableIdleCode;
239 u8 idleCode;
240 u8 spare[44];
241 };
242
243 /* TE1 Status */
244 struct su_status {
245 u32 receiveBufferDelay;
246 u32 framingErrorCount;
247 u32 codeViolationCount;
248 u32 crcErrorCount;
249 u32 lineAttenuation;
250 u8 portStarted;
251 u8 lossOfSignal;
252 u8 receiveRemoteAlarm;
253 u8 alarmIndicationSignal;
254 u8 spare[40];
255 };
256
257 /* Finally sling all the above together into the shared memory structure.
258 * Sorry it's a hodge podge of arrays, structures and unused bits, it's been
259 * evolving under NT for some time so I guess we're stuck with it.
260 * The structure starts at offset SMC_BASE.
261 * See farsync.h for some field values.
262 */
263 struct fst_shared {
264 /* DMA descriptor rings */
265 struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER];
266 struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER];
267
268 /* Obsolete small buffers */
269 u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER];
270 u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER];
271
272 u8 taskStatus; /* 0x00 => initialising, 0x01 => running,
273 * 0xFF => halted
274 */
275
276 u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt,
277 * set to 0xEE by host to acknowledge interrupt
278 */
279
280 u16 smcVersion; /* Must match SMC_VERSION */
281
282 u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major
283 * version, RR = revision and BB = build
284 */
285
286 u16 txa_done; /* Obsolete completion flags */
287 u16 rxa_done;
288 u16 txb_done;
289 u16 rxb_done;
290 u16 txc_done;
291 u16 rxc_done;
292 u16 txd_done;
293 u16 rxd_done;
294
295 u16 mailbox[4]; /* Diagnostics mailbox. Not used */
296
297 struct cirbuff interruptEvent; /* interrupt causes */
298
299 u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */
300 u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */
301
302 struct port_cfg portConfig[FST_MAX_PORTS];
303
304 u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */
305
306 u16 cableStatus; /* lsb: 0=> present, 1=> absent */
307
308 u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */
309 u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */
310
311 u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */
312 u16 cardMailbox[4]; /* Not used */
313
314 /* Number of times the card thinks the host has
315 * missed an interrupt by not acknowledging
316 * within 2mS (I guess NT has problems)
317 */
318 u32 interruptRetryCount;
319
320 /* Driver private data used as an ID. We'll not
321 * use this as I'd rather keep such things
322 * in main memory rather than on the PCI bus
323 */
324 u32 portHandle[FST_MAX_PORTS];
325
326 /* Count of Tx underflows for stats */
327 u32 transmitBufferUnderflow[FST_MAX_PORTS];
328
329 /* Debounced V.24 control input status */
330 u32 v24DebouncedSts[FST_MAX_PORTS];
331
332 /* Adapter debounce timers. Don't touch */
333 u32 ctsTimer[FST_MAX_PORTS];
334 u32 ctsTimerRun[FST_MAX_PORTS];
335 u32 dcdTimer[FST_MAX_PORTS];
336 u32 dcdTimerRun[FST_MAX_PORTS];
337
338 u32 numberOfPorts; /* Number of ports detected at startup */
339
340 u16 _reserved[64];
341
342 u16 cardMode; /* Bit-mask to enable features:
343 * Bit 0: 1 enables LED identify mode
344 */
345
346 u16 portScheduleOffset;
347
348 struct su_config suConfig; /* TE1 Bits */
349 struct su_status suStatus;
350
351 u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of
352 * the structure and marks the end of shared
353 * memory. Adapter code initializes it as
354 * END_SIG.
355 */
356 };
357
358 /* endOfSmcSignature value */
359 #define END_SIG 0x12345678
360
361 /* Mailbox values. (portMailbox) */
362 #define NOP 0 /* No operation */
363 #define ACK 1 /* Positive acknowledgement to PC driver */
364 #define NAK 2 /* Negative acknowledgement to PC driver */
365 #define STARTPORT 3 /* Start an HDLC port */
366 #define STOPPORT 4 /* Stop an HDLC port */
367 #define ABORTTX 5 /* Abort the transmitter for a port */
368 #define SETV24O 6 /* Set V24 outputs */
369
370 /* PLX Chip Register Offsets */
371 #define CNTRL_9052 0x50 /* Control Register */
372 #define CNTRL_9054 0x6c /* Control Register */
373
374 #define INTCSR_9052 0x4c /* Interrupt control/status register */
375 #define INTCSR_9054 0x68 /* Interrupt control/status register */
376
377 /* 9054 DMA Registers */
378 /*
379 * Note that we will be using DMA Channel 0 for copying rx data
380 * and Channel 1 for copying tx data
381 */
382 #define DMAMODE0 0x80
383 #define DMAPADR0 0x84
384 #define DMALADR0 0x88
385 #define DMASIZ0 0x8c
386 #define DMADPR0 0x90
387 #define DMAMODE1 0x94
388 #define DMAPADR1 0x98
389 #define DMALADR1 0x9c
390 #define DMASIZ1 0xa0
391 #define DMADPR1 0xa4
392 #define DMACSR0 0xa8
393 #define DMACSR1 0xa9
394 #define DMAARB 0xac
395 #define DMATHR 0xb0
396 #define DMADAC0 0xb4
397 #define DMADAC1 0xb8
398 #define DMAMARBR 0xac
399
400 #define FST_MIN_DMA_LEN 64
401 #define FST_RX_DMA_INT 0x01
402 #define FST_TX_DMA_INT 0x02
403 #define FST_CARD_INT 0x04
404
405 /* Larger buffers are positioned in memory at offset BFM_BASE */
406 struct buf_window {
407 u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER];
408 u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER];
409 };
410
411 /* Calculate offset of a buffer object within the shared memory window */
412 #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X))
413
414 #pragma pack()
415
416 /* Device driver private information
417 * =================================
418 */
419 /* Per port (line or channel) information
420 */
421 struct fst_port_info {
422 struct net_device *dev; /* Device struct - must be first */
423 struct fst_card_info *card; /* Card we're associated with */
424 int index; /* Port index on the card */
425 int hwif; /* Line hardware (lineInterface copy) */
426 int run; /* Port is running */
427 int mode; /* Normal or FarSync raw */
428 int rxpos; /* Next Rx buffer to use */
429 int txpos; /* Next Tx buffer to use */
430 int txipos; /* Next Tx buffer to check for free */
431 int start; /* Indication of start/stop to network */
432 /*
433 * A sixteen entry transmit queue
434 */
435 int txqs; /* index to get next buffer to tx */
436 int txqe; /* index to queue next packet */
437 struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */
438 int rxqdepth;
439 };
440
441 /* Per card information
442 */
443 struct fst_card_info {
444 char __iomem *mem; /* Card memory mapped to kernel space */
445 char __iomem *ctlmem; /* Control memory for PCI cards */
446 unsigned int phys_mem; /* Physical memory window address */
447 unsigned int phys_ctlmem; /* Physical control memory address */
448 unsigned int irq; /* Interrupt request line number */
449 unsigned int nports; /* Number of serial ports */
450 unsigned int type; /* Type index of card */
451 unsigned int state; /* State of card */
452 spinlock_t card_lock; /* Lock for SMP access */
453 unsigned short pci_conf; /* PCI card config in I/O space */
454 /* Per port info */
455 struct fst_port_info ports[FST_MAX_PORTS];
456 struct pci_dev *device; /* Information about the pci device */
457 int card_no; /* Inst of the card on the system */
458 int family; /* TxP or TxU */
459 int dmarx_in_progress;
460 int dmatx_in_progress;
461 unsigned long int_count;
462 unsigned long int_time_ave;
463 void *rx_dma_handle_host;
464 dma_addr_t rx_dma_handle_card;
465 void *tx_dma_handle_host;
466 dma_addr_t tx_dma_handle_card;
467 struct sk_buff *dma_skb_rx;
468 struct fst_port_info *dma_port_rx;
469 struct fst_port_info *dma_port_tx;
470 int dma_len_rx;
471 int dma_len_tx;
472 int dma_txpos;
473 int dma_rxpos;
474 };
475
476 /* Convert an HDLC device pointer into a port info pointer and similar */
477 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
478 #define port_to_dev(P) ((P)->dev)
479
480
481 /*
482 * Shared memory window access macros
483 *
484 * We have a nice memory based structure above, which could be directly
485 * mapped on i386 but might not work on other architectures unless we use
486 * the readb,w,l and writeb,w,l macros. Unfortunately these macros take
487 * physical offsets so we have to convert. The only saving grace is that
488 * this should all collapse back to a simple indirection eventually.
489 */
490 #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X))
491
492 #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E))
493 #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E))
494 #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E))
495
496 #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E))
497 #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E))
498 #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E))
499
500 /*
501 * Debug support
502 */
503 #if FST_DEBUG
504
505 static int fst_debug_mask = { FST_DEBUG };
506
507 /* Most common debug activity is to print something if the corresponding bit
508 * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to
509 * support variable numbers of macro parameters. The inverted if prevents us
510 * eating someone else's else clause.
511 */
512 #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \
513 ; \
514 else \
515 printk ( KERN_DEBUG FST_NAME ": " fmt, ## A )
516
517 #else
518 #define dbg(X...) /* NOP */
519 #endif
520
521 /* Printing short cuts
522 */
523 #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A )
524 #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A )
525 #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A )
526
527 /*
528 * PCI ID lookup table
529 */
530 static struct pci_device_id fst_pci_dev_id[] __devinitdata = {
531 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID,
532 PCI_ANY_ID, 0, 0, FST_TYPE_T2P},
533
534 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID,
535 PCI_ANY_ID, 0, 0, FST_TYPE_T4P},
536
537 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID,
538 PCI_ANY_ID, 0, 0, FST_TYPE_T1U},
539
540 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID,
541 PCI_ANY_ID, 0, 0, FST_TYPE_T2U},
542
543 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID,
544 PCI_ANY_ID, 0, 0, FST_TYPE_T4U},
545
546 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID,
547 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
548
549 {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID,
550 PCI_ANY_ID, 0, 0, FST_TYPE_TE1},
551 {0,} /* End */
552 };
553
554 MODULE_DEVICE_TABLE(pci, fst_pci_dev_id);
555
556 /*
557 * Device Driver Work Queues
558 *
559 * So that we don't spend too much time processing events in the
560 * Interrupt Service routine, we will declare a work queue per Card
561 * and make the ISR schedule a task in the queue for later execution.
562 * In the 2.4 Kernel we used to use the immediate queue for BH's
563 * Now that they are gone, tasklets seem to be much better than work
564 * queues.
565 */
566
567 static void do_bottom_half_tx(struct fst_card_info *card);
568 static void do_bottom_half_rx(struct fst_card_info *card);
569 static void fst_process_tx_work_q(unsigned long work_q);
570 static void fst_process_int_work_q(unsigned long work_q);
571
572 static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0);
573 static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0);
574
575 static struct fst_card_info *fst_card_array[FST_MAX_CARDS];
576 static spinlock_t fst_work_q_lock;
577 static u64 fst_work_txq;
578 static u64 fst_work_intq;
579
580 static void
581 fst_q_work_item(u64 * queue, int card_index)
582 {
583 unsigned long flags;
584 u64 mask;
585
586 /*
587 * Grab the queue exclusively
588 */
589 spin_lock_irqsave(&fst_work_q_lock, flags);
590
591 /*
592 * Making an entry in the queue is simply a matter of setting
593 * a bit for the card indicating that there is work to do in the
594 * bottom half for the card. Note the limitation of 64 cards.
595 * That ought to be enough
596 */
597 mask = 1 << card_index;
598 *queue |= mask;
599 spin_unlock_irqrestore(&fst_work_q_lock, flags);
600 }
601
602 static void
603 fst_process_tx_work_q(unsigned long /*void **/work_q)
604 {
605 unsigned long flags;
606 u64 work_txq;
607 int i;
608
609 /*
610 * Grab the queue exclusively
611 */
612 dbg(DBG_TX, "fst_process_tx_work_q\n");
613 spin_lock_irqsave(&fst_work_q_lock, flags);
614 work_txq = fst_work_txq;
615 fst_work_txq = 0;
616 spin_unlock_irqrestore(&fst_work_q_lock, flags);
617
618 /*
619 * Call the bottom half for each card with work waiting
620 */
621 for (i = 0; i < FST_MAX_CARDS; i++) {
622 if (work_txq & 0x01) {
623 if (fst_card_array[i] != NULL) {
624 dbg(DBG_TX, "Calling tx bh for card %d\n", i);
625 do_bottom_half_tx(fst_card_array[i]);
626 }
627 }
628 work_txq = work_txq >> 1;
629 }
630 }
631
632 static void
633 fst_process_int_work_q(unsigned long /*void **/work_q)
634 {
635 unsigned long flags;
636 u64 work_intq;
637 int i;
638
639 /*
640 * Grab the queue exclusively
641 */
642 dbg(DBG_INTR, "fst_process_int_work_q\n");
643 spin_lock_irqsave(&fst_work_q_lock, flags);
644 work_intq = fst_work_intq;
645 fst_work_intq = 0;
646 spin_unlock_irqrestore(&fst_work_q_lock, flags);
647
648 /*
649 * Call the bottom half for each card with work waiting
650 */
651 for (i = 0; i < FST_MAX_CARDS; i++) {
652 if (work_intq & 0x01) {
653 if (fst_card_array[i] != NULL) {
654 dbg(DBG_INTR,
655 "Calling rx & tx bh for card %d\n", i);
656 do_bottom_half_rx(fst_card_array[i]);
657 do_bottom_half_tx(fst_card_array[i]);
658 }
659 }
660 work_intq = work_intq >> 1;
661 }
662 }
663
664 /* Card control functions
665 * ======================
666 */
667 /* Place the processor in reset state
668 *
669 * Used to be a simple write to card control space but a glitch in the latest
670 * AMD Am186CH processor means that we now have to do it by asserting and de-
671 * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register
672 * at offset 9052_CNTRL. Note the updates for the TXU.
673 */
674 static inline void
675 fst_cpureset(struct fst_card_info *card)
676 {
677 unsigned char interrupt_line_register;
678 unsigned long j = jiffies + 1;
679 unsigned int regval;
680
681 if (card->family == FST_FAMILY_TXU) {
682 if (pci_read_config_byte
683 (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) {
684 dbg(DBG_ASS,
685 "Error in reading interrupt line register\n");
686 }
687 /*
688 * Assert PLX software reset and Am186 hardware reset
689 * and then deassert the PLX software reset but 186 still in reset
690 */
691 outw(0x440f, card->pci_conf + CNTRL_9054 + 2);
692 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
693 /*
694 * We are delaying here to allow the 9054 to reset itself
695 */
696 j = jiffies + 1;
697 while (jiffies < j)
698 /* Do nothing */ ;
699 outw(0x240f, card->pci_conf + CNTRL_9054 + 2);
700 /*
701 * We are delaying here to allow the 9054 to reload its eeprom
702 */
703 j = jiffies + 1;
704 while (jiffies < j)
705 /* Do nothing */ ;
706 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
707
708 if (pci_write_config_byte
709 (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) {
710 dbg(DBG_ASS,
711 "Error in writing interrupt line register\n");
712 }
713
714 } else {
715 regval = inl(card->pci_conf + CNTRL_9052);
716
717 outl(regval | 0x40000000, card->pci_conf + CNTRL_9052);
718 outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052);
719 }
720 }
721
722 /* Release the processor from reset
723 */
724 static inline void
725 fst_cpurelease(struct fst_card_info *card)
726 {
727 if (card->family == FST_FAMILY_TXU) {
728 /*
729 * Force posted writes to complete
730 */
731 (void) readb(card->mem);
732
733 /*
734 * Release LRESET DO = 1
735 * Then release Local Hold, DO = 1
736 */
737 outw(0x040e, card->pci_conf + CNTRL_9054 + 2);
738 outw(0x040f, card->pci_conf + CNTRL_9054 + 2);
739 } else {
740 (void) readb(card->ctlmem);
741 }
742 }
743
744 /* Clear the cards interrupt flag
745 */
746 static inline void
747 fst_clear_intr(struct fst_card_info *card)
748 {
749 if (card->family == FST_FAMILY_TXU) {
750 (void) readb(card->ctlmem);
751 } else {
752 /* Poke the appropriate PLX chip register (same as enabling interrupts)
753 */
754 outw(0x0543, card->pci_conf + INTCSR_9052);
755 }
756 }
757
758 /* Enable card interrupts
759 */
760 static inline void
761 fst_enable_intr(struct fst_card_info *card)
762 {
763 if (card->family == FST_FAMILY_TXU) {
764 outl(0x0f0c0900, card->pci_conf + INTCSR_9054);
765 } else {
766 outw(0x0543, card->pci_conf + INTCSR_9052);
767 }
768 }
769
770 /* Disable card interrupts
771 */
772 static inline void
773 fst_disable_intr(struct fst_card_info *card)
774 {
775 if (card->family == FST_FAMILY_TXU) {
776 outl(0x00000000, card->pci_conf + INTCSR_9054);
777 } else {
778 outw(0x0000, card->pci_conf + INTCSR_9052);
779 }
780 }
781
782 /* Process the result of trying to pass a received frame up the stack
783 */
784 static void
785 fst_process_rx_status(int rx_status, char *name)
786 {
787 switch (rx_status) {
788 case NET_RX_SUCCESS:
789 {
790 /*
791 * Nothing to do here
792 */
793 break;
794 }
795
796 case NET_RX_CN_LOW:
797 {
798 dbg(DBG_ASS, "%s: Receive Low Congestion\n", name);
799 break;
800 }
801
802 case NET_RX_CN_MOD:
803 {
804 dbg(DBG_ASS, "%s: Receive Moderate Congestion\n", name);
805 break;
806 }
807
808 case NET_RX_CN_HIGH:
809 {
810 dbg(DBG_ASS, "%s: Receive High Congestion\n", name);
811 break;
812 }
813
814 case NET_RX_DROP:
815 {
816 dbg(DBG_ASS, "%s: Received packet dropped\n", name);
817 break;
818 }
819 }
820 }
821
822 /* Initilaise DMA for PLX 9054
823 */
824 static inline void
825 fst_init_dma(struct fst_card_info *card)
826 {
827 /*
828 * This is only required for the PLX 9054
829 */
830 if (card->family == FST_FAMILY_TXU) {
831 pci_set_master(card->device);
832 outl(0x00020441, card->pci_conf + DMAMODE0);
833 outl(0x00020441, card->pci_conf + DMAMODE1);
834 outl(0x0, card->pci_conf + DMATHR);
835 }
836 }
837
838 /* Tx dma complete interrupt
839 */
840 static void
841 fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
842 int len, int txpos)
843 {
844 struct net_device *dev = port_to_dev(port);
845
846 /*
847 * Everything is now set, just tell the card to go
848 */
849 dbg(DBG_TX, "fst_tx_dma_complete\n");
850 FST_WRB(card, txDescrRing[port->index][txpos].bits,
851 DMA_OWN | TX_STP | TX_ENP);
852 dev->stats.tx_packets++;
853 dev->stats.tx_bytes += len;
854 dev->trans_start = jiffies;
855 }
856
857 /*
858 * Mark it for our own raw sockets interface
859 */
860 static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev)
861 {
862 skb->dev = dev;
863 skb_reset_mac_header(skb);
864 skb->pkt_type = PACKET_HOST;
865 return htons(ETH_P_CUST);
866 }
867
868 /* Rx dma complete interrupt
869 */
870 static void
871 fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port,
872 int len, struct sk_buff *skb, int rxp)
873 {
874 struct net_device *dev = port_to_dev(port);
875 int pi;
876 int rx_status;
877
878 dbg(DBG_TX, "fst_rx_dma_complete\n");
879 pi = port->index;
880 memcpy(skb_put(skb, len), card->rx_dma_handle_host, len);
881
882 /* Reset buffer descriptor */
883 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
884
885 /* Update stats */
886 dev->stats.rx_packets++;
887 dev->stats.rx_bytes += len;
888
889 /* Push upstream */
890 dbg(DBG_RX, "Pushing the frame up the stack\n");
891 if (port->mode == FST_RAW)
892 skb->protocol = farsync_type_trans(skb, dev);
893 else
894 skb->protocol = hdlc_type_trans(skb, dev);
895 rx_status = netif_rx(skb);
896 fst_process_rx_status(rx_status, port_to_dev(port)->name);
897 if (rx_status == NET_RX_DROP)
898 dev->stats.rx_dropped++;
899 dev->last_rx = jiffies;
900 }
901
902 /*
903 * Receive a frame through the DMA
904 */
905 static inline void
906 fst_rx_dma(struct fst_card_info *card, unsigned char *skb,
907 unsigned char *mem, int len)
908 {
909 /*
910 * This routine will setup the DMA and start it
911 */
912
913 dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len);
914 if (card->dmarx_in_progress) {
915 dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n");
916 }
917
918 outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */
919 outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */
920 outl(len, card->pci_conf + DMASIZ0); /* for this length */
921 outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */
922
923 /*
924 * We use the dmarx_in_progress flag to flag the channel as busy
925 */
926 card->dmarx_in_progress = 1;
927 outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */
928 }
929
930 /*
931 * Send a frame through the DMA
932 */
933 static inline void
934 fst_tx_dma(struct fst_card_info *card, unsigned char *skb,
935 unsigned char *mem, int len)
936 {
937 /*
938 * This routine will setup the DMA and start it.
939 */
940
941 dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len);
942 if (card->dmatx_in_progress) {
943 dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n");
944 }
945
946 outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */
947 outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */
948 outl(len, card->pci_conf + DMASIZ1); /* for this length */
949 outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */
950
951 /*
952 * We use the dmatx_in_progress to flag the channel as busy
953 */
954 card->dmatx_in_progress = 1;
955 outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */
956 }
957
958 /* Issue a Mailbox command for a port.
959 * Note we issue them on a fire and forget basis, not expecting to see an
960 * error and not waiting for completion.
961 */
962 static void
963 fst_issue_cmd(struct fst_port_info *port, unsigned short cmd)
964 {
965 struct fst_card_info *card;
966 unsigned short mbval;
967 unsigned long flags;
968 int safety;
969
970 card = port->card;
971 spin_lock_irqsave(&card->card_lock, flags);
972 mbval = FST_RDW(card, portMailbox[port->index][0]);
973
974 safety = 0;
975 /* Wait for any previous command to complete */
976 while (mbval > NAK) {
977 spin_unlock_irqrestore(&card->card_lock, flags);
978 schedule_timeout_uninterruptible(1);
979 spin_lock_irqsave(&card->card_lock, flags);
980
981 if (++safety > 2000) {
982 printk_err("Mailbox safety timeout\n");
983 break;
984 }
985
986 mbval = FST_RDW(card, portMailbox[port->index][0]);
987 }
988 if (safety > 0) {
989 dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety);
990 }
991 if (mbval == NAK) {
992 dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n");
993 }
994
995 FST_WRW(card, portMailbox[port->index][0], cmd);
996
997 if (cmd == ABORTTX || cmd == STARTPORT) {
998 port->txpos = 0;
999 port->txipos = 0;
1000 port->start = 0;
1001 }
1002
1003 spin_unlock_irqrestore(&card->card_lock, flags);
1004 }
1005
1006 /* Port output signals control
1007 */
1008 static inline void
1009 fst_op_raise(struct fst_port_info *port, unsigned int outputs)
1010 {
1011 outputs |= FST_RDL(port->card, v24OpSts[port->index]);
1012 FST_WRL(port->card, v24OpSts[port->index], outputs);
1013
1014 if (port->run)
1015 fst_issue_cmd(port, SETV24O);
1016 }
1017
1018 static inline void
1019 fst_op_lower(struct fst_port_info *port, unsigned int outputs)
1020 {
1021 outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]);
1022 FST_WRL(port->card, v24OpSts[port->index], outputs);
1023
1024 if (port->run)
1025 fst_issue_cmd(port, SETV24O);
1026 }
1027
1028 /*
1029 * Setup port Rx buffers
1030 */
1031 static void
1032 fst_rx_config(struct fst_port_info *port)
1033 {
1034 int i;
1035 int pi;
1036 unsigned int offset;
1037 unsigned long flags;
1038 struct fst_card_info *card;
1039
1040 pi = port->index;
1041 card = port->card;
1042 spin_lock_irqsave(&card->card_lock, flags);
1043 for (i = 0; i < NUM_RX_BUFFER; i++) {
1044 offset = BUF_OFFSET(rxBuffer[pi][i][0]);
1045
1046 FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset);
1047 FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16));
1048 FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER));
1049 FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER);
1050 FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN);
1051 }
1052 port->rxpos = 0;
1053 spin_unlock_irqrestore(&card->card_lock, flags);
1054 }
1055
1056 /*
1057 * Setup port Tx buffers
1058 */
1059 static void
1060 fst_tx_config(struct fst_port_info *port)
1061 {
1062 int i;
1063 int pi;
1064 unsigned int offset;
1065 unsigned long flags;
1066 struct fst_card_info *card;
1067
1068 pi = port->index;
1069 card = port->card;
1070 spin_lock_irqsave(&card->card_lock, flags);
1071 for (i = 0; i < NUM_TX_BUFFER; i++) {
1072 offset = BUF_OFFSET(txBuffer[pi][i][0]);
1073
1074 FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset);
1075 FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16));
1076 FST_WRW(card, txDescrRing[pi][i].bcnt, 0);
1077 FST_WRB(card, txDescrRing[pi][i].bits, 0);
1078 }
1079 port->txpos = 0;
1080 port->txipos = 0;
1081 port->start = 0;
1082 spin_unlock_irqrestore(&card->card_lock, flags);
1083 }
1084
1085 /* TE1 Alarm change interrupt event
1086 */
1087 static void
1088 fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port)
1089 {
1090 u8 los;
1091 u8 rra;
1092 u8 ais;
1093
1094 los = FST_RDB(card, suStatus.lossOfSignal);
1095 rra = FST_RDB(card, suStatus.receiveRemoteAlarm);
1096 ais = FST_RDB(card, suStatus.alarmIndicationSignal);
1097
1098 if (los) {
1099 /*
1100 * Lost the link
1101 */
1102 if (netif_carrier_ok(port_to_dev(port))) {
1103 dbg(DBG_INTR, "Net carrier off\n");
1104 netif_carrier_off(port_to_dev(port));
1105 }
1106 } else {
1107 /*
1108 * Link available
1109 */
1110 if (!netif_carrier_ok(port_to_dev(port))) {
1111 dbg(DBG_INTR, "Net carrier on\n");
1112 netif_carrier_on(port_to_dev(port));
1113 }
1114 }
1115
1116 if (los)
1117 dbg(DBG_INTR, "Assert LOS Alarm\n");
1118 else
1119 dbg(DBG_INTR, "De-assert LOS Alarm\n");
1120 if (rra)
1121 dbg(DBG_INTR, "Assert RRA Alarm\n");
1122 else
1123 dbg(DBG_INTR, "De-assert RRA Alarm\n");
1124
1125 if (ais)
1126 dbg(DBG_INTR, "Assert AIS Alarm\n");
1127 else
1128 dbg(DBG_INTR, "De-assert AIS Alarm\n");
1129 }
1130
1131 /* Control signal change interrupt event
1132 */
1133 static void
1134 fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port)
1135 {
1136 int signals;
1137
1138 signals = FST_RDL(card, v24DebouncedSts[port->index]);
1139
1140 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
1141 ? IPSTS_INDICATE : IPSTS_DCD)) {
1142 if (!netif_carrier_ok(port_to_dev(port))) {
1143 dbg(DBG_INTR, "DCD active\n");
1144 netif_carrier_on(port_to_dev(port));
1145 }
1146 } else {
1147 if (netif_carrier_ok(port_to_dev(port))) {
1148 dbg(DBG_INTR, "DCD lost\n");
1149 netif_carrier_off(port_to_dev(port));
1150 }
1151 }
1152 }
1153
1154 /* Log Rx Errors
1155 */
1156 static void
1157 fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1158 unsigned char dmabits, int rxp, unsigned short len)
1159 {
1160 struct net_device *dev = port_to_dev(port);
1161
1162 /*
1163 * Increment the appropriate error counter
1164 */
1165 dev->stats.rx_errors++;
1166 if (dmabits & RX_OFLO) {
1167 dev->stats.rx_fifo_errors++;
1168 dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n",
1169 card->card_no, port->index, rxp);
1170 }
1171 if (dmabits & RX_CRC) {
1172 dev->stats.rx_crc_errors++;
1173 dbg(DBG_ASS, "Rx crc error on card %d port %d\n",
1174 card->card_no, port->index);
1175 }
1176 if (dmabits & RX_FRAM) {
1177 dev->stats.rx_frame_errors++;
1178 dbg(DBG_ASS, "Rx frame error on card %d port %d\n",
1179 card->card_no, port->index);
1180 }
1181 if (dmabits == (RX_STP | RX_ENP)) {
1182 dev->stats.rx_length_errors++;
1183 dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n",
1184 len, card->card_no, port->index);
1185 }
1186 }
1187
1188 /* Rx Error Recovery
1189 */
1190 static void
1191 fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port,
1192 unsigned char dmabits, int rxp, unsigned short len)
1193 {
1194 int i;
1195 int pi;
1196
1197 pi = port->index;
1198 /*
1199 * Discard buffer descriptors until we see the start of the
1200 * next frame. Note that for long frames this could be in
1201 * a subsequent interrupt.
1202 */
1203 i = 0;
1204 while ((dmabits & (DMA_OWN | RX_STP)) == 0) {
1205 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1206 rxp = (rxp+1) % NUM_RX_BUFFER;
1207 if (++i > NUM_RX_BUFFER) {
1208 dbg(DBG_ASS, "intr_rx: Discarding more bufs"
1209 " than we have\n");
1210 break;
1211 }
1212 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1213 dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits);
1214 }
1215 dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i);
1216
1217 /* Discard the terminal buffer */
1218 if (!(dmabits & DMA_OWN)) {
1219 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1220 rxp = (rxp+1) % NUM_RX_BUFFER;
1221 }
1222 port->rxpos = rxp;
1223 return;
1224
1225 }
1226
1227 /* Rx complete interrupt
1228 */
1229 static void
1230 fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port)
1231 {
1232 unsigned char dmabits;
1233 int pi;
1234 int rxp;
1235 int rx_status;
1236 unsigned short len;
1237 struct sk_buff *skb;
1238 struct net_device *dev = port_to_dev(port);
1239
1240 /* Check we have a buffer to process */
1241 pi = port->index;
1242 rxp = port->rxpos;
1243 dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits);
1244 if (dmabits & DMA_OWN) {
1245 dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n",
1246 pi, rxp);
1247 return;
1248 }
1249 if (card->dmarx_in_progress) {
1250 return;
1251 }
1252
1253 /* Get buffer length */
1254 len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt);
1255 /* Discard the CRC */
1256 len -= 2;
1257 if (len == 0) {
1258 /*
1259 * This seems to happen on the TE1 interface sometimes
1260 * so throw the frame away and log the event.
1261 */
1262 printk_err("Frame received with 0 length. Card %d Port %d\n",
1263 card->card_no, port->index);
1264 /* Return descriptor to card */
1265 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1266
1267 rxp = (rxp+1) % NUM_RX_BUFFER;
1268 port->rxpos = rxp;
1269 return;
1270 }
1271
1272 /* Check buffer length and for other errors. We insist on one packet
1273 * in one buffer. This simplifies things greatly and since we've
1274 * allocated 8K it shouldn't be a real world limitation
1275 */
1276 dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len);
1277 if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) {
1278 fst_log_rx_error(card, port, dmabits, rxp, len);
1279 fst_recover_rx_error(card, port, dmabits, rxp, len);
1280 return;
1281 }
1282
1283 /* Allocate SKB */
1284 if ((skb = dev_alloc_skb(len)) == NULL) {
1285 dbg(DBG_RX, "intr_rx: can't allocate buffer\n");
1286
1287 dev->stats.rx_dropped++;
1288
1289 /* Return descriptor to card */
1290 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1291
1292 rxp = (rxp+1) % NUM_RX_BUFFER;
1293 port->rxpos = rxp;
1294 return;
1295 }
1296
1297 /*
1298 * We know the length we need to receive, len.
1299 * It's not worth using the DMA for reads of less than
1300 * FST_MIN_DMA_LEN
1301 */
1302
1303 if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) {
1304 memcpy_fromio(skb_put(skb, len),
1305 card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]),
1306 len);
1307
1308 /* Reset buffer descriptor */
1309 FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN);
1310
1311 /* Update stats */
1312 dev->stats.rx_packets++;
1313 dev->stats.rx_bytes += len;
1314
1315 /* Push upstream */
1316 dbg(DBG_RX, "Pushing frame up the stack\n");
1317 if (port->mode == FST_RAW)
1318 skb->protocol = farsync_type_trans(skb, dev);
1319 else
1320 skb->protocol = hdlc_type_trans(skb, dev);
1321 rx_status = netif_rx(skb);
1322 fst_process_rx_status(rx_status, port_to_dev(port)->name);
1323 if (rx_status == NET_RX_DROP)
1324 dev->stats.rx_dropped++;
1325 dev->last_rx = jiffies;
1326 } else {
1327 card->dma_skb_rx = skb;
1328 card->dma_port_rx = port;
1329 card->dma_len_rx = len;
1330 card->dma_rxpos = rxp;
1331 fst_rx_dma(card, (char *) card->rx_dma_handle_card,
1332 (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len);
1333 }
1334 if (rxp != port->rxpos) {
1335 dbg(DBG_ASS, "About to increment rxpos by more than 1\n");
1336 dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos);
1337 }
1338 rxp = (rxp+1) % NUM_RX_BUFFER;
1339 port->rxpos = rxp;
1340 }
1341
1342 /*
1343 * The bottom halfs to the ISR
1344 *
1345 */
1346
1347 static void
1348 do_bottom_half_tx(struct fst_card_info *card)
1349 {
1350 struct fst_port_info *port;
1351 int pi;
1352 int txq_length;
1353 struct sk_buff *skb;
1354 unsigned long flags;
1355 struct net_device *dev;
1356
1357 /*
1358 * Find a free buffer for the transmit
1359 * Step through each port on this card
1360 */
1361
1362 dbg(DBG_TX, "do_bottom_half_tx\n");
1363 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1364 if (!port->run)
1365 continue;
1366
1367 dev = port_to_dev(port);
1368 while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) &
1369 DMA_OWN)
1370 && !(card->dmatx_in_progress)) {
1371 /*
1372 * There doesn't seem to be a txdone event per-se
1373 * We seem to have to deduce it, by checking the DMA_OWN
1374 * bit on the next buffer we think we can use
1375 */
1376 spin_lock_irqsave(&card->card_lock, flags);
1377 if ((txq_length = port->txqe - port->txqs) < 0) {
1378 /*
1379 * This is the case where one has wrapped and the
1380 * maths gives us a negative number
1381 */
1382 txq_length = txq_length + FST_TXQ_DEPTH;
1383 }
1384 spin_unlock_irqrestore(&card->card_lock, flags);
1385 if (txq_length > 0) {
1386 /*
1387 * There is something to send
1388 */
1389 spin_lock_irqsave(&card->card_lock, flags);
1390 skb = port->txq[port->txqs];
1391 port->txqs++;
1392 if (port->txqs == FST_TXQ_DEPTH) {
1393 port->txqs = 0;
1394 }
1395 spin_unlock_irqrestore(&card->card_lock, flags);
1396 /*
1397 * copy the data and set the required indicators on the
1398 * card.
1399 */
1400 FST_WRW(card, txDescrRing[pi][port->txpos].bcnt,
1401 cnv_bcnt(skb->len));
1402 if ((skb->len < FST_MIN_DMA_LEN)
1403 || (card->family == FST_FAMILY_TXP)) {
1404 /* Enqueue the packet with normal io */
1405 memcpy_toio(card->mem +
1406 BUF_OFFSET(txBuffer[pi]
1407 [port->
1408 txpos][0]),
1409 skb->data, skb->len);
1410 FST_WRB(card,
1411 txDescrRing[pi][port->txpos].
1412 bits,
1413 DMA_OWN | TX_STP | TX_ENP);
1414 dev->stats.tx_packets++;
1415 dev->stats.tx_bytes += skb->len;
1416 dev->trans_start = jiffies;
1417 } else {
1418 /* Or do it through dma */
1419 memcpy(card->tx_dma_handle_host,
1420 skb->data, skb->len);
1421 card->dma_port_tx = port;
1422 card->dma_len_tx = skb->len;
1423 card->dma_txpos = port->txpos;
1424 fst_tx_dma(card,
1425 (char *) card->
1426 tx_dma_handle_card,
1427 (char *)
1428 BUF_OFFSET(txBuffer[pi]
1429 [port->txpos][0]),
1430 skb->len);
1431 }
1432 if (++port->txpos >= NUM_TX_BUFFER)
1433 port->txpos = 0;
1434 /*
1435 * If we have flow control on, can we now release it?
1436 */
1437 if (port->start) {
1438 if (txq_length < fst_txq_low) {
1439 netif_wake_queue(port_to_dev
1440 (port));
1441 port->start = 0;
1442 }
1443 }
1444 dev_kfree_skb(skb);
1445 } else {
1446 /*
1447 * Nothing to send so break out of the while loop
1448 */
1449 break;
1450 }
1451 }
1452 }
1453 }
1454
1455 static void
1456 do_bottom_half_rx(struct fst_card_info *card)
1457 {
1458 struct fst_port_info *port;
1459 int pi;
1460 int rx_count = 0;
1461
1462 /* Check for rx completions on all ports on this card */
1463 dbg(DBG_RX, "do_bottom_half_rx\n");
1464 for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) {
1465 if (!port->run)
1466 continue;
1467
1468 while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits)
1469 & DMA_OWN) && !(card->dmarx_in_progress)) {
1470 if (rx_count > fst_max_reads) {
1471 /*
1472 * Don't spend forever in receive processing
1473 * Schedule another event
1474 */
1475 fst_q_work_item(&fst_work_intq, card->card_no);
1476 tasklet_schedule(&fst_int_task);
1477 break; /* Leave the loop */
1478 }
1479 fst_intr_rx(card, port);
1480 rx_count++;
1481 }
1482 }
1483 }
1484
1485 /*
1486 * The interrupt service routine
1487 * Dev_id is our fst_card_info pointer
1488 */
1489 static irqreturn_t
1490 fst_intr(int dummy, void *dev_id)
1491 {
1492 struct fst_card_info *card = dev_id;
1493 struct fst_port_info *port;
1494 int rdidx; /* Event buffer indices */
1495 int wridx;
1496 int event; /* Actual event for processing */
1497 unsigned int dma_intcsr = 0;
1498 unsigned int do_card_interrupt;
1499 unsigned int int_retry_count;
1500
1501 /*
1502 * Check to see if the interrupt was for this card
1503 * return if not
1504 * Note that the call to clear the interrupt is important
1505 */
1506 dbg(DBG_INTR, "intr: %d %p\n", card->irq, card);
1507 if (card->state != FST_RUNNING) {
1508 printk_err
1509 ("Interrupt received for card %d in a non running state (%d)\n",
1510 card->card_no, card->state);
1511
1512 /*
1513 * It is possible to really be running, i.e. we have re-loaded
1514 * a running card
1515 * Clear and reprime the interrupt source
1516 */
1517 fst_clear_intr(card);
1518 return IRQ_HANDLED;
1519 }
1520
1521 /* Clear and reprime the interrupt source */
1522 fst_clear_intr(card);
1523
1524 /*
1525 * Is the interrupt for this card (handshake == 1)
1526 */
1527 do_card_interrupt = 0;
1528 if (FST_RDB(card, interruptHandshake) == 1) {
1529 do_card_interrupt += FST_CARD_INT;
1530 /* Set the software acknowledge */
1531 FST_WRB(card, interruptHandshake, 0xEE);
1532 }
1533 if (card->family == FST_FAMILY_TXU) {
1534 /*
1535 * Is it a DMA Interrupt
1536 */
1537 dma_intcsr = inl(card->pci_conf + INTCSR_9054);
1538 if (dma_intcsr & 0x00200000) {
1539 /*
1540 * DMA Channel 0 (Rx transfer complete)
1541 */
1542 dbg(DBG_RX, "DMA Rx xfer complete\n");
1543 outb(0x8, card->pci_conf + DMACSR0);
1544 fst_rx_dma_complete(card, card->dma_port_rx,
1545 card->dma_len_rx, card->dma_skb_rx,
1546 card->dma_rxpos);
1547 card->dmarx_in_progress = 0;
1548 do_card_interrupt += FST_RX_DMA_INT;
1549 }
1550 if (dma_intcsr & 0x00400000) {
1551 /*
1552 * DMA Channel 1 (Tx transfer complete)
1553 */
1554 dbg(DBG_TX, "DMA Tx xfer complete\n");
1555 outb(0x8, card->pci_conf + DMACSR1);
1556 fst_tx_dma_complete(card, card->dma_port_tx,
1557 card->dma_len_tx, card->dma_txpos);
1558 card->dmatx_in_progress = 0;
1559 do_card_interrupt += FST_TX_DMA_INT;
1560 }
1561 }
1562
1563 /*
1564 * Have we been missing Interrupts
1565 */
1566 int_retry_count = FST_RDL(card, interruptRetryCount);
1567 if (int_retry_count) {
1568 dbg(DBG_ASS, "Card %d int_retry_count is %d\n",
1569 card->card_no, int_retry_count);
1570 FST_WRL(card, interruptRetryCount, 0);
1571 }
1572
1573 if (!do_card_interrupt) {
1574 return IRQ_HANDLED;
1575 }
1576
1577 /* Scehdule the bottom half of the ISR */
1578 fst_q_work_item(&fst_work_intq, card->card_no);
1579 tasklet_schedule(&fst_int_task);
1580
1581 /* Drain the event queue */
1582 rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f;
1583 wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f;
1584 while (rdidx != wridx) {
1585 event = FST_RDB(card, interruptEvent.evntbuff[rdidx]);
1586 port = &card->ports[event & 0x03];
1587
1588 dbg(DBG_INTR, "Processing Interrupt event: %x\n", event);
1589
1590 switch (event) {
1591 case TE1_ALMA:
1592 dbg(DBG_INTR, "TE1 Alarm intr\n");
1593 if (port->run)
1594 fst_intr_te1_alarm(card, port);
1595 break;
1596
1597 case CTLA_CHG:
1598 case CTLB_CHG:
1599 case CTLC_CHG:
1600 case CTLD_CHG:
1601 if (port->run)
1602 fst_intr_ctlchg(card, port);
1603 break;
1604
1605 case ABTA_SENT:
1606 case ABTB_SENT:
1607 case ABTC_SENT:
1608 case ABTD_SENT:
1609 dbg(DBG_TX, "Abort complete port %d\n", port->index);
1610 break;
1611
1612 case TXA_UNDF:
1613 case TXB_UNDF:
1614 case TXC_UNDF:
1615 case TXD_UNDF:
1616 /* Difficult to see how we'd get this given that we
1617 * always load up the entire packet for DMA.
1618 */
1619 dbg(DBG_TX, "Tx underflow port %d\n", port->index);
1620 port_to_dev(port)->stats.tx_errors++;
1621 port_to_dev(port)->stats.tx_fifo_errors++;
1622 dbg(DBG_ASS, "Tx underflow on card %d port %d\n",
1623 card->card_no, port->index);
1624 break;
1625
1626 case INIT_CPLT:
1627 dbg(DBG_INIT, "Card init OK intr\n");
1628 break;
1629
1630 case INIT_FAIL:
1631 dbg(DBG_INIT, "Card init FAILED intr\n");
1632 card->state = FST_IFAILED;
1633 break;
1634
1635 default:
1636 printk_err("intr: unknown card event %d. ignored\n",
1637 event);
1638 break;
1639 }
1640
1641 /* Bump and wrap the index */
1642 if (++rdidx >= MAX_CIRBUFF)
1643 rdidx = 0;
1644 }
1645 FST_WRB(card, interruptEvent.rdindex, rdidx);
1646 return IRQ_HANDLED;
1647 }
1648
1649 /* Check that the shared memory configuration is one that we can handle
1650 * and that some basic parameters are correct
1651 */
1652 static void
1653 check_started_ok(struct fst_card_info *card)
1654 {
1655 int i;
1656
1657 /* Check structure version and end marker */
1658 if (FST_RDW(card, smcVersion) != SMC_VERSION) {
1659 printk_err("Bad shared memory version %d expected %d\n",
1660 FST_RDW(card, smcVersion), SMC_VERSION);
1661 card->state = FST_BADVERSION;
1662 return;
1663 }
1664 if (FST_RDL(card, endOfSmcSignature) != END_SIG) {
1665 printk_err("Missing shared memory signature\n");
1666 card->state = FST_BADVERSION;
1667 return;
1668 }
1669 /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */
1670 if ((i = FST_RDB(card, taskStatus)) == 0x01) {
1671 card->state = FST_RUNNING;
1672 } else if (i == 0xFF) {
1673 printk_err("Firmware initialisation failed. Card halted\n");
1674 card->state = FST_HALTED;
1675 return;
1676 } else if (i != 0x00) {
1677 printk_err("Unknown firmware status 0x%x\n", i);
1678 card->state = FST_HALTED;
1679 return;
1680 }
1681
1682 /* Finally check the number of ports reported by firmware against the
1683 * number we assumed at card detection. Should never happen with
1684 * existing firmware etc so we just report it for the moment.
1685 */
1686 if (FST_RDL(card, numberOfPorts) != card->nports) {
1687 printk_warn("Port count mismatch on card %d."
1688 " Firmware thinks %d we say %d\n", card->card_no,
1689 FST_RDL(card, numberOfPorts), card->nports);
1690 }
1691 }
1692
1693 static int
1694 set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port,
1695 struct fstioc_info *info)
1696 {
1697 int err;
1698 unsigned char my_framing;
1699
1700 /* Set things according to the user set valid flags
1701 * Several of the old options have been invalidated/replaced by the
1702 * generic hdlc package.
1703 */
1704 err = 0;
1705 if (info->valid & FSTVAL_PROTO) {
1706 if (info->proto == FST_RAW)
1707 port->mode = FST_RAW;
1708 else
1709 port->mode = FST_GEN_HDLC;
1710 }
1711
1712 if (info->valid & FSTVAL_CABLE)
1713 err = -EINVAL;
1714
1715 if (info->valid & FSTVAL_SPEED)
1716 err = -EINVAL;
1717
1718 if (info->valid & FSTVAL_PHASE)
1719 FST_WRB(card, portConfig[port->index].invertClock,
1720 info->invertClock);
1721 if (info->valid & FSTVAL_MODE)
1722 FST_WRW(card, cardMode, info->cardMode);
1723 if (info->valid & FSTVAL_TE1) {
1724 FST_WRL(card, suConfig.dataRate, info->lineSpeed);
1725 FST_WRB(card, suConfig.clocking, info->clockSource);
1726 my_framing = FRAMING_E1;
1727 if (info->framing == E1)
1728 my_framing = FRAMING_E1;
1729 if (info->framing == T1)
1730 my_framing = FRAMING_T1;
1731 if (info->framing == J1)
1732 my_framing = FRAMING_J1;
1733 FST_WRB(card, suConfig.framing, my_framing);
1734 FST_WRB(card, suConfig.structure, info->structure);
1735 FST_WRB(card, suConfig.interface, info->interface);
1736 FST_WRB(card, suConfig.coding, info->coding);
1737 FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut);
1738 FST_WRB(card, suConfig.equalizer, info->equalizer);
1739 FST_WRB(card, suConfig.transparentMode, info->transparentMode);
1740 FST_WRB(card, suConfig.loopMode, info->loopMode);
1741 FST_WRB(card, suConfig.range, info->range);
1742 FST_WRB(card, suConfig.txBufferMode, info->txBufferMode);
1743 FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode);
1744 FST_WRB(card, suConfig.startingSlot, info->startingSlot);
1745 FST_WRB(card, suConfig.losThreshold, info->losThreshold);
1746 if (info->idleCode)
1747 FST_WRB(card, suConfig.enableIdleCode, 1);
1748 else
1749 FST_WRB(card, suConfig.enableIdleCode, 0);
1750 FST_WRB(card, suConfig.idleCode, info->idleCode);
1751 #if FST_DEBUG
1752 if (info->valid & FSTVAL_TE1) {
1753 printk("Setting TE1 data\n");
1754 printk("Line Speed = %d\n", info->lineSpeed);
1755 printk("Start slot = %d\n", info->startingSlot);
1756 printk("Clock source = %d\n", info->clockSource);
1757 printk("Framing = %d\n", my_framing);
1758 printk("Structure = %d\n", info->structure);
1759 printk("interface = %d\n", info->interface);
1760 printk("Coding = %d\n", info->coding);
1761 printk("Line build out = %d\n", info->lineBuildOut);
1762 printk("Equaliser = %d\n", info->equalizer);
1763 printk("Transparent mode = %d\n",
1764 info->transparentMode);
1765 printk("Loop mode = %d\n", info->loopMode);
1766 printk("Range = %d\n", info->range);
1767 printk("Tx Buffer mode = %d\n", info->txBufferMode);
1768 printk("Rx Buffer mode = %d\n", info->rxBufferMode);
1769 printk("LOS Threshold = %d\n", info->losThreshold);
1770 printk("Idle Code = %d\n", info->idleCode);
1771 }
1772 #endif
1773 }
1774 #if FST_DEBUG
1775 if (info->valid & FSTVAL_DEBUG) {
1776 fst_debug_mask = info->debug;
1777 }
1778 #endif
1779
1780 return err;
1781 }
1782
1783 static void
1784 gather_conf_info(struct fst_card_info *card, struct fst_port_info *port,
1785 struct fstioc_info *info)
1786 {
1787 int i;
1788
1789 memset(info, 0, sizeof (struct fstioc_info));
1790
1791 i = port->index;
1792 info->kernelVersion = LINUX_VERSION_CODE;
1793 info->nports = card->nports;
1794 info->type = card->type;
1795 info->state = card->state;
1796 info->proto = FST_GEN_HDLC;
1797 info->index = i;
1798 #if FST_DEBUG
1799 info->debug = fst_debug_mask;
1800 #endif
1801
1802 /* Only mark information as valid if card is running.
1803 * Copy the data anyway in case it is useful for diagnostics
1804 */
1805 info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD)
1806 #if FST_DEBUG
1807 | FSTVAL_DEBUG
1808 #endif
1809 ;
1810
1811 info->lineInterface = FST_RDW(card, portConfig[i].lineInterface);
1812 info->internalClock = FST_RDB(card, portConfig[i].internalClock);
1813 info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed);
1814 info->invertClock = FST_RDB(card, portConfig[i].invertClock);
1815 info->v24IpSts = FST_RDL(card, v24IpSts[i]);
1816 info->v24OpSts = FST_RDL(card, v24OpSts[i]);
1817 info->clockStatus = FST_RDW(card, clockStatus[i]);
1818 info->cableStatus = FST_RDW(card, cableStatus);
1819 info->cardMode = FST_RDW(card, cardMode);
1820 info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion);
1821
1822 /*
1823 * The T2U can report cable presence for both A or B
1824 * in bits 0 and 1 of cableStatus. See which port we are and
1825 * do the mapping.
1826 */
1827 if (card->family == FST_FAMILY_TXU) {
1828 if (port->index == 0) {
1829 /*
1830 * Port A
1831 */
1832 info->cableStatus = info->cableStatus & 1;
1833 } else {
1834 /*
1835 * Port B
1836 */
1837 info->cableStatus = info->cableStatus >> 1;
1838 info->cableStatus = info->cableStatus & 1;
1839 }
1840 }
1841 /*
1842 * Some additional bits if we are TE1
1843 */
1844 if (card->type == FST_TYPE_TE1) {
1845 info->lineSpeed = FST_RDL(card, suConfig.dataRate);
1846 info->clockSource = FST_RDB(card, suConfig.clocking);
1847 info->framing = FST_RDB(card, suConfig.framing);
1848 info->structure = FST_RDB(card, suConfig.structure);
1849 info->interface = FST_RDB(card, suConfig.interface);
1850 info->coding = FST_RDB(card, suConfig.coding);
1851 info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut);
1852 info->equalizer = FST_RDB(card, suConfig.equalizer);
1853 info->loopMode = FST_RDB(card, suConfig.loopMode);
1854 info->range = FST_RDB(card, suConfig.range);
1855 info->txBufferMode = FST_RDB(card, suConfig.txBufferMode);
1856 info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode);
1857 info->startingSlot = FST_RDB(card, suConfig.startingSlot);
1858 info->losThreshold = FST_RDB(card, suConfig.losThreshold);
1859 if (FST_RDB(card, suConfig.enableIdleCode))
1860 info->idleCode = FST_RDB(card, suConfig.idleCode);
1861 else
1862 info->idleCode = 0;
1863 info->receiveBufferDelay =
1864 FST_RDL(card, suStatus.receiveBufferDelay);
1865 info->framingErrorCount =
1866 FST_RDL(card, suStatus.framingErrorCount);
1867 info->codeViolationCount =
1868 FST_RDL(card, suStatus.codeViolationCount);
1869 info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount);
1870 info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation);
1871 info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal);
1872 info->receiveRemoteAlarm =
1873 FST_RDB(card, suStatus.receiveRemoteAlarm);
1874 info->alarmIndicationSignal =
1875 FST_RDB(card, suStatus.alarmIndicationSignal);
1876 }
1877 }
1878
1879 static int
1880 fst_set_iface(struct fst_card_info *card, struct fst_port_info *port,
1881 struct ifreq *ifr)
1882 {
1883 sync_serial_settings sync;
1884 int i;
1885
1886 if (ifr->ifr_settings.size != sizeof (sync)) {
1887 return -ENOMEM;
1888 }
1889
1890 if (copy_from_user
1891 (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) {
1892 return -EFAULT;
1893 }
1894
1895 if (sync.loopback)
1896 return -EINVAL;
1897
1898 i = port->index;
1899
1900 switch (ifr->ifr_settings.type) {
1901 case IF_IFACE_V35:
1902 FST_WRW(card, portConfig[i].lineInterface, V35);
1903 port->hwif = V35;
1904 break;
1905
1906 case IF_IFACE_V24:
1907 FST_WRW(card, portConfig[i].lineInterface, V24);
1908 port->hwif = V24;
1909 break;
1910
1911 case IF_IFACE_X21:
1912 FST_WRW(card, portConfig[i].lineInterface, X21);
1913 port->hwif = X21;
1914 break;
1915
1916 case IF_IFACE_X21D:
1917 FST_WRW(card, portConfig[i].lineInterface, X21D);
1918 port->hwif = X21D;
1919 break;
1920
1921 case IF_IFACE_T1:
1922 FST_WRW(card, portConfig[i].lineInterface, T1);
1923 port->hwif = T1;
1924 break;
1925
1926 case IF_IFACE_E1:
1927 FST_WRW(card, portConfig[i].lineInterface, E1);
1928 port->hwif = E1;
1929 break;
1930
1931 case IF_IFACE_SYNC_SERIAL:
1932 break;
1933
1934 default:
1935 return -EINVAL;
1936 }
1937
1938 switch (sync.clock_type) {
1939 case CLOCK_EXT:
1940 FST_WRB(card, portConfig[i].internalClock, EXTCLK);
1941 break;
1942
1943 case CLOCK_INT:
1944 FST_WRB(card, portConfig[i].internalClock, INTCLK);
1945 break;
1946
1947 default:
1948 return -EINVAL;
1949 }
1950 FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate);
1951 return 0;
1952 }
1953
1954 static int
1955 fst_get_iface(struct fst_card_info *card, struct fst_port_info *port,
1956 struct ifreq *ifr)
1957 {
1958 sync_serial_settings sync;
1959 int i;
1960
1961 /* First check what line type is set, we'll default to reporting X.21
1962 * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be
1963 * changed
1964 */
1965 switch (port->hwif) {
1966 case E1:
1967 ifr->ifr_settings.type = IF_IFACE_E1;
1968 break;
1969 case T1:
1970 ifr->ifr_settings.type = IF_IFACE_T1;
1971 break;
1972 case V35:
1973 ifr->ifr_settings.type = IF_IFACE_V35;
1974 break;
1975 case V24:
1976 ifr->ifr_settings.type = IF_IFACE_V24;
1977 break;
1978 case X21D:
1979 ifr->ifr_settings.type = IF_IFACE_X21D;
1980 break;
1981 case X21:
1982 default:
1983 ifr->ifr_settings.type = IF_IFACE_X21;
1984 break;
1985 }
1986 if (ifr->ifr_settings.size == 0) {
1987 return 0; /* only type requested */
1988 }
1989 if (ifr->ifr_settings.size < sizeof (sync)) {
1990 return -ENOMEM;
1991 }
1992
1993 i = port->index;
1994 sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed);
1995 /* Lucky card and linux use same encoding here */
1996 sync.clock_type = FST_RDB(card, portConfig[i].internalClock) ==
1997 INTCLK ? CLOCK_INT : CLOCK_EXT;
1998 sync.loopback = 0;
1999
2000 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) {
2001 return -EFAULT;
2002 }
2003
2004 ifr->ifr_settings.size = sizeof (sync);
2005 return 0;
2006 }
2007
2008 static int
2009 fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2010 {
2011 struct fst_card_info *card;
2012 struct fst_port_info *port;
2013 struct fstioc_write wrthdr;
2014 struct fstioc_info info;
2015 unsigned long flags;
2016 void *buf;
2017
2018 dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data);
2019
2020 port = dev_to_port(dev);
2021 card = port->card;
2022
2023 if (!capable(CAP_NET_ADMIN))
2024 return -EPERM;
2025
2026 switch (cmd) {
2027 case FSTCPURESET:
2028 fst_cpureset(card);
2029 card->state = FST_RESET;
2030 return 0;
2031
2032 case FSTCPURELEASE:
2033 fst_cpurelease(card);
2034 card->state = FST_STARTING;
2035 return 0;
2036
2037 case FSTWRITE: /* Code write (download) */
2038
2039 /* First copy in the header with the length and offset of data
2040 * to write
2041 */
2042 if (ifr->ifr_data == NULL) {
2043 return -EINVAL;
2044 }
2045 if (copy_from_user(&wrthdr, ifr->ifr_data,
2046 sizeof (struct fstioc_write))) {
2047 return -EFAULT;
2048 }
2049
2050 /* Sanity check the parameters. We don't support partial writes
2051 * when going over the top
2052 */
2053 if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE
2054 || wrthdr.size + wrthdr.offset > FST_MEMSIZE) {
2055 return -ENXIO;
2056 }
2057
2058 /* Now copy the data to the card. */
2059
2060 buf = kmalloc(wrthdr.size, GFP_KERNEL);
2061 if (!buf)
2062 return -ENOMEM;
2063
2064 if (copy_from_user(buf,
2065 ifr->ifr_data + sizeof (struct fstioc_write),
2066 wrthdr.size)) {
2067 kfree(buf);
2068 return -EFAULT;
2069 }
2070
2071 memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size);
2072 kfree(buf);
2073
2074 /* Writes to the memory of a card in the reset state constitute
2075 * a download
2076 */
2077 if (card->state == FST_RESET) {
2078 card->state = FST_DOWNLOAD;
2079 }
2080 return 0;
2081
2082 case FSTGETCONF:
2083
2084 /* If card has just been started check the shared memory config
2085 * version and marker
2086 */
2087 if (card->state == FST_STARTING) {
2088 check_started_ok(card);
2089
2090 /* If everything checked out enable card interrupts */
2091 if (card->state == FST_RUNNING) {
2092 spin_lock_irqsave(&card->card_lock, flags);
2093 fst_enable_intr(card);
2094 FST_WRB(card, interruptHandshake, 0xEE);
2095 spin_unlock_irqrestore(&card->card_lock, flags);
2096 }
2097 }
2098
2099 if (ifr->ifr_data == NULL) {
2100 return -EINVAL;
2101 }
2102
2103 gather_conf_info(card, port, &info);
2104
2105 if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) {
2106 return -EFAULT;
2107 }
2108 return 0;
2109
2110 case FSTSETCONF:
2111
2112 /*
2113 * Most of the settings have been moved to the generic ioctls
2114 * this just covers debug and board ident now
2115 */
2116
2117 if (card->state != FST_RUNNING) {
2118 printk_err
2119 ("Attempt to configure card %d in non-running state (%d)\n",
2120 card->card_no, card->state);
2121 return -EIO;
2122 }
2123 if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) {
2124 return -EFAULT;
2125 }
2126
2127 return set_conf_from_info(card, port, &info);
2128
2129 case SIOCWANDEV:
2130 switch (ifr->ifr_settings.type) {
2131 case IF_GET_IFACE:
2132 return fst_get_iface(card, port, ifr);
2133
2134 case IF_IFACE_SYNC_SERIAL:
2135 case IF_IFACE_V35:
2136 case IF_IFACE_V24:
2137 case IF_IFACE_X21:
2138 case IF_IFACE_X21D:
2139 case IF_IFACE_T1:
2140 case IF_IFACE_E1:
2141 return fst_set_iface(card, port, ifr);
2142
2143 case IF_PROTO_RAW:
2144 port->mode = FST_RAW;
2145 return 0;
2146
2147 case IF_GET_PROTO:
2148 if (port->mode == FST_RAW) {
2149 ifr->ifr_settings.type = IF_PROTO_RAW;
2150 return 0;
2151 }
2152 return hdlc_ioctl(dev, ifr, cmd);
2153
2154 default:
2155 port->mode = FST_GEN_HDLC;
2156 dbg(DBG_IOCTL, "Passing this type to hdlc %x\n",
2157 ifr->ifr_settings.type);
2158 return hdlc_ioctl(dev, ifr, cmd);
2159 }
2160
2161 default:
2162 /* Not one of ours. Pass through to HDLC package */
2163 return hdlc_ioctl(dev, ifr, cmd);
2164 }
2165 }
2166
2167 static void
2168 fst_openport(struct fst_port_info *port)
2169 {
2170 int signals;
2171 int txq_length;
2172
2173 /* Only init things if card is actually running. This allows open to
2174 * succeed for downloads etc.
2175 */
2176 if (port->card->state == FST_RUNNING) {
2177 if (port->run) {
2178 dbg(DBG_OPEN, "open: found port already running\n");
2179
2180 fst_issue_cmd(port, STOPPORT);
2181 port->run = 0;
2182 }
2183
2184 fst_rx_config(port);
2185 fst_tx_config(port);
2186 fst_op_raise(port, OPSTS_RTS | OPSTS_DTR);
2187
2188 fst_issue_cmd(port, STARTPORT);
2189 port->run = 1;
2190
2191 signals = FST_RDL(port->card, v24DebouncedSts[port->index]);
2192 if (signals & (((port->hwif == X21) || (port->hwif == X21D))
2193 ? IPSTS_INDICATE : IPSTS_DCD))
2194 netif_carrier_on(port_to_dev(port));
2195 else
2196 netif_carrier_off(port_to_dev(port));
2197
2198 txq_length = port->txqe - port->txqs;
2199 port->txqe = 0;
2200 port->txqs = 0;
2201 }
2202
2203 }
2204
2205 static void
2206 fst_closeport(struct fst_port_info *port)
2207 {
2208 if (port->card->state == FST_RUNNING) {
2209 if (port->run) {
2210 port->run = 0;
2211 fst_op_lower(port, OPSTS_RTS | OPSTS_DTR);
2212
2213 fst_issue_cmd(port, STOPPORT);
2214 } else {
2215 dbg(DBG_OPEN, "close: port not running\n");
2216 }
2217 }
2218 }
2219
2220 static int
2221 fst_open(struct net_device *dev)
2222 {
2223 int err;
2224 struct fst_port_info *port;
2225
2226 port = dev_to_port(dev);
2227 if (!try_module_get(THIS_MODULE))
2228 return -EBUSY;
2229
2230 if (port->mode != FST_RAW) {
2231 err = hdlc_open(dev);
2232 if (err)
2233 return err;
2234 }
2235
2236 fst_openport(port);
2237 netif_wake_queue(dev);
2238 return 0;
2239 }
2240
2241 static int
2242 fst_close(struct net_device *dev)
2243 {
2244 struct fst_port_info *port;
2245 struct fst_card_info *card;
2246 unsigned char tx_dma_done;
2247 unsigned char rx_dma_done;
2248
2249 port = dev_to_port(dev);
2250 card = port->card;
2251
2252 tx_dma_done = inb(card->pci_conf + DMACSR1);
2253 rx_dma_done = inb(card->pci_conf + DMACSR0);
2254 dbg(DBG_OPEN,
2255 "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n",
2256 card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress,
2257 rx_dma_done);
2258
2259 netif_stop_queue(dev);
2260 fst_closeport(dev_to_port(dev));
2261 if (port->mode != FST_RAW) {
2262 hdlc_close(dev);
2263 }
2264 module_put(THIS_MODULE);
2265 return 0;
2266 }
2267
2268 static int
2269 fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity)
2270 {
2271 /*
2272 * Setting currently fixed in FarSync card so we check and forget
2273 */
2274 if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT)
2275 return -EINVAL;
2276 return 0;
2277 }
2278
2279 static void
2280 fst_tx_timeout(struct net_device *dev)
2281 {
2282 struct fst_port_info *port;
2283 struct fst_card_info *card;
2284
2285 port = dev_to_port(dev);
2286 card = port->card;
2287 dev->stats.tx_errors++;
2288 dev->stats.tx_aborted_errors++;
2289 dbg(DBG_ASS, "Tx timeout card %d port %d\n",
2290 card->card_no, port->index);
2291 fst_issue_cmd(port, ABORTTX);
2292
2293 dev->trans_start = jiffies;
2294 netif_wake_queue(dev);
2295 port->start = 0;
2296 }
2297
2298 static int
2299 fst_start_xmit(struct sk_buff *skb, struct net_device *dev)
2300 {
2301 struct fst_card_info *card;
2302 struct fst_port_info *port;
2303 unsigned long flags;
2304 int txq_length;
2305
2306 port = dev_to_port(dev);
2307 card = port->card;
2308 dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len);
2309
2310 /* Drop packet with error if we don't have carrier */
2311 if (!netif_carrier_ok(dev)) {
2312 dev_kfree_skb(skb);
2313 dev->stats.tx_errors++;
2314 dev->stats.tx_carrier_errors++;
2315 dbg(DBG_ASS,
2316 "Tried to transmit but no carrier on card %d port %d\n",
2317 card->card_no, port->index);
2318 return 0;
2319 }
2320
2321 /* Drop it if it's too big! MTU failure ? */
2322 if (skb->len > LEN_TX_BUFFER) {
2323 dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len,
2324 LEN_TX_BUFFER);
2325 dev_kfree_skb(skb);
2326 dev->stats.tx_errors++;
2327 return 0;
2328 }
2329
2330 /*
2331 * We are always going to queue the packet
2332 * so that the bottom half is the only place we tx from
2333 * Check there is room in the port txq
2334 */
2335 spin_lock_irqsave(&card->card_lock, flags);
2336 if ((txq_length = port->txqe - port->txqs) < 0) {
2337 /*
2338 * This is the case where the next free has wrapped but the
2339 * last used hasn't
2340 */
2341 txq_length = txq_length + FST_TXQ_DEPTH;
2342 }
2343 spin_unlock_irqrestore(&card->card_lock, flags);
2344 if (txq_length > fst_txq_high) {
2345 /*
2346 * We have got enough buffers in the pipeline. Ask the network
2347 * layer to stop sending frames down
2348 */
2349 netif_stop_queue(dev);
2350 port->start = 1; /* I'm using this to signal stop sent up */
2351 }
2352
2353 if (txq_length == FST_TXQ_DEPTH - 1) {
2354 /*
2355 * This shouldn't have happened but such is life
2356 */
2357 dev_kfree_skb(skb);
2358 dev->stats.tx_errors++;
2359 dbg(DBG_ASS, "Tx queue overflow card %d port %d\n",
2360 card->card_no, port->index);
2361 return 0;
2362 }
2363
2364 /*
2365 * queue the buffer
2366 */
2367 spin_lock_irqsave(&card->card_lock, flags);
2368 port->txq[port->txqe] = skb;
2369 port->txqe++;
2370 if (port->txqe == FST_TXQ_DEPTH)
2371 port->txqe = 0;
2372 spin_unlock_irqrestore(&card->card_lock, flags);
2373
2374 /* Scehdule the bottom half which now does transmit processing */
2375 fst_q_work_item(&fst_work_txq, card->card_no);
2376 tasklet_schedule(&fst_tx_task);
2377
2378 return 0;
2379 }
2380
2381 /*
2382 * Card setup having checked hardware resources.
2383 * Should be pretty bizarre if we get an error here (kernel memory
2384 * exhaustion is one possibility). If we do see a problem we report it
2385 * via a printk and leave the corresponding interface and all that follow
2386 * disabled.
2387 */
2388 static char *type_strings[] __devinitdata = {
2389 "no hardware", /* Should never be seen */
2390 "FarSync T2P",
2391 "FarSync T4P",
2392 "FarSync T1U",
2393 "FarSync T2U",
2394 "FarSync T4U",
2395 "FarSync TE1"
2396 };
2397
2398 static void __devinit
2399 fst_init_card(struct fst_card_info *card)
2400 {
2401 int i;
2402 int err;
2403
2404 /* We're working on a number of ports based on the card ID. If the
2405 * firmware detects something different later (should never happen)
2406 * we'll have to revise it in some way then.
2407 */
2408 for (i = 0; i < card->nports; i++) {
2409 err = register_hdlc_device(card->ports[i].dev);
2410 if (err < 0) {
2411 int j;
2412 printk_err ("Cannot register HDLC device for port %d"
2413 " (errno %d)\n", i, -err );
2414 for (j = i; j < card->nports; j++) {
2415 free_netdev(card->ports[j].dev);
2416 card->ports[j].dev = NULL;
2417 }
2418 card->nports = i;
2419 break;
2420 }
2421 }
2422
2423 printk_info("%s-%s: %s IRQ%d, %d ports\n",
2424 port_to_dev(&card->ports[0])->name,
2425 port_to_dev(&card->ports[card->nports - 1])->name,
2426 type_strings[card->type], card->irq, card->nports);
2427 }
2428
2429 /*
2430 * Initialise card when detected.
2431 * Returns 0 to indicate success, or errno otherwise.
2432 */
2433 static int __devinit
2434 fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2435 {
2436 static int firsttime_done = 0;
2437 static int no_of_cards_added = 0;
2438 struct fst_card_info *card;
2439 int err = 0;
2440 int i;
2441
2442 if (!firsttime_done) {
2443 printk_info("FarSync WAN driver " FST_USER_VERSION
2444 " (c) 2001-2004 FarSite Communications Ltd.\n");
2445 firsttime_done = 1;
2446 dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask);
2447 }
2448
2449 /*
2450 * We are going to be clever and allow certain cards not to be
2451 * configured. An exclude list can be provided in /etc/modules.conf
2452 */
2453 if (fst_excluded_cards != 0) {
2454 /*
2455 * There are cards to exclude
2456 *
2457 */
2458 for (i = 0; i < fst_excluded_cards; i++) {
2459 if ((pdev->devfn) >> 3 == fst_excluded_list[i]) {
2460 printk_info("FarSync PCI device %d not assigned\n",
2461 (pdev->devfn) >> 3);
2462 return -EBUSY;
2463 }
2464 }
2465 }
2466
2467 /* Allocate driver private data */
2468 card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL);
2469 if (card == NULL) {
2470 printk_err("FarSync card found but insufficient memory for"
2471 " driver storage\n");
2472 return -ENOMEM;
2473 }
2474
2475 /* Try to enable the device */
2476 if ((err = pci_enable_device(pdev)) != 0) {
2477 printk_err("Failed to enable card. Err %d\n", -err);
2478 kfree(card);
2479 return err;
2480 }
2481
2482 if ((err = pci_request_regions(pdev, "FarSync")) !=0) {
2483 printk_err("Failed to allocate regions. Err %d\n", -err);
2484 pci_disable_device(pdev);
2485 kfree(card);
2486 return err;
2487 }
2488
2489 /* Get virtual addresses of memory regions */
2490 card->pci_conf = pci_resource_start(pdev, 1);
2491 card->phys_mem = pci_resource_start(pdev, 2);
2492 card->phys_ctlmem = pci_resource_start(pdev, 3);
2493 if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) {
2494 printk_err("Physical memory remap failed\n");
2495 pci_release_regions(pdev);
2496 pci_disable_device(pdev);
2497 kfree(card);
2498 return -ENODEV;
2499 }
2500 if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) {
2501 printk_err("Control memory remap failed\n");
2502 pci_release_regions(pdev);
2503 pci_disable_device(pdev);
2504 kfree(card);
2505 return -ENODEV;
2506 }
2507 dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem);
2508
2509 /* Register the interrupt handler */
2510 if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) {
2511 printk_err("Unable to register interrupt %d\n", card->irq);
2512 pci_release_regions(pdev);
2513 pci_disable_device(pdev);
2514 iounmap(card->ctlmem);
2515 iounmap(card->mem);
2516 kfree(card);
2517 return -ENODEV;
2518 }
2519
2520 /* Record info we need */
2521 card->irq = pdev->irq;
2522 card->type = ent->driver_data;
2523 card->family = ((ent->driver_data == FST_TYPE_T2P) ||
2524 (ent->driver_data == FST_TYPE_T4P))
2525 ? FST_FAMILY_TXP : FST_FAMILY_TXU;
2526 if ((ent->driver_data == FST_TYPE_T1U) ||
2527 (ent->driver_data == FST_TYPE_TE1))
2528 card->nports = 1;
2529 else
2530 card->nports = ((ent->driver_data == FST_TYPE_T2P) ||
2531 (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4;
2532
2533 card->state = FST_UNINIT;
2534 spin_lock_init ( &card->card_lock );
2535
2536 for ( i = 0 ; i < card->nports ; i++ ) {
2537 struct net_device *dev = alloc_hdlcdev(&card->ports[i]);
2538 hdlc_device *hdlc;
2539 if (!dev) {
2540 while (i--)
2541 free_netdev(card->ports[i].dev);
2542 printk_err ("FarSync: out of memory\n");
2543 free_irq(card->irq, card);
2544 pci_release_regions(pdev);
2545 pci_disable_device(pdev);
2546 iounmap(card->ctlmem);
2547 iounmap(card->mem);
2548 kfree(card);
2549 return -ENODEV;
2550 }
2551 card->ports[i].dev = dev;
2552 card->ports[i].card = card;
2553 card->ports[i].index = i;
2554 card->ports[i].run = 0;
2555
2556 hdlc = dev_to_hdlc(dev);
2557
2558 /* Fill in the net device info */
2559 /* Since this is a PCI setup this is purely
2560 * informational. Give them the buffer addresses
2561 * and basic card I/O.
2562 */
2563 dev->mem_start = card->phys_mem
2564 + BUF_OFFSET ( txBuffer[i][0][0]);
2565 dev->mem_end = card->phys_mem
2566 + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]);
2567 dev->base_addr = card->pci_conf;
2568 dev->irq = card->irq;
2569
2570 dev->tx_queue_len = FST_TX_QUEUE_LEN;
2571 dev->open = fst_open;
2572 dev->stop = fst_close;
2573 dev->do_ioctl = fst_ioctl;
2574 dev->watchdog_timeo = FST_TX_TIMEOUT;
2575 dev->tx_timeout = fst_tx_timeout;
2576 hdlc->attach = fst_attach;
2577 hdlc->xmit = fst_start_xmit;
2578 }
2579
2580 card->device = pdev;
2581
2582 dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type,
2583 card->nports, card->irq);
2584 dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n",
2585 card->pci_conf, card->phys_mem, card->phys_ctlmem);
2586
2587 /* Reset the card's processor */
2588 fst_cpureset(card);
2589 card->state = FST_RESET;
2590
2591 /* Initialise DMA (if required) */
2592 fst_init_dma(card);
2593
2594 /* Record driver data for later use */
2595 pci_set_drvdata(pdev, card);
2596
2597 /* Remainder of card setup */
2598 fst_card_array[no_of_cards_added] = card;
2599 card->card_no = no_of_cards_added++; /* Record instance and bump it */
2600 fst_init_card(card);
2601 if (card->family == FST_FAMILY_TXU) {
2602 /*
2603 * Allocate a dma buffer for transmit and receives
2604 */
2605 card->rx_dma_handle_host =
2606 pci_alloc_consistent(card->device, FST_MAX_MTU,
2607 &card->rx_dma_handle_card);
2608 if (card->rx_dma_handle_host == NULL) {
2609 printk_err("Could not allocate rx dma buffer\n");
2610 fst_disable_intr(card);
2611 pci_release_regions(pdev);
2612 pci_disable_device(pdev);
2613 iounmap(card->ctlmem);
2614 iounmap(card->mem);
2615 kfree(card);
2616 return -ENOMEM;
2617 }
2618 card->tx_dma_handle_host =
2619 pci_alloc_consistent(card->device, FST_MAX_MTU,
2620 &card->tx_dma_handle_card);
2621 if (card->tx_dma_handle_host == NULL) {
2622 printk_err("Could not allocate tx dma buffer\n");
2623 fst_disable_intr(card);
2624 pci_release_regions(pdev);
2625 pci_disable_device(pdev);
2626 iounmap(card->ctlmem);
2627 iounmap(card->mem);
2628 kfree(card);
2629 return -ENOMEM;
2630 }
2631 }
2632 return 0; /* Success */
2633 }
2634
2635 /*
2636 * Cleanup and close down a card
2637 */
2638 static void __devexit
2639 fst_remove_one(struct pci_dev *pdev)
2640 {
2641 struct fst_card_info *card;
2642 int i;
2643
2644 card = pci_get_drvdata(pdev);
2645
2646 for (i = 0; i < card->nports; i++) {
2647 struct net_device *dev = port_to_dev(&card->ports[i]);
2648 unregister_hdlc_device(dev);
2649 }
2650
2651 fst_disable_intr(card);
2652 free_irq(card->irq, card);
2653
2654 iounmap(card->ctlmem);
2655 iounmap(card->mem);
2656 pci_release_regions(pdev);
2657 if (card->family == FST_FAMILY_TXU) {
2658 /*
2659 * Free dma buffers
2660 */
2661 pci_free_consistent(card->device, FST_MAX_MTU,
2662 card->rx_dma_handle_host,
2663 card->rx_dma_handle_card);
2664 pci_free_consistent(card->device, FST_MAX_MTU,
2665 card->tx_dma_handle_host,
2666 card->tx_dma_handle_card);
2667 }
2668 fst_card_array[card->card_no] = NULL;
2669 }
2670
2671 static struct pci_driver fst_driver = {
2672 .name = FST_NAME,
2673 .id_table = fst_pci_dev_id,
2674 .probe = fst_add_one,
2675 .remove = __devexit_p(fst_remove_one),
2676 .suspend = NULL,
2677 .resume = NULL,
2678 };
2679
2680 static int __init
2681 fst_init(void)
2682 {
2683 int i;
2684
2685 for (i = 0; i < FST_MAX_CARDS; i++)
2686 fst_card_array[i] = NULL;
2687 spin_lock_init(&fst_work_q_lock);
2688 return pci_register_driver(&fst_driver);
2689 }
2690
2691 static void __exit
2692 fst_cleanup_module(void)
2693 {
2694 printk_info("FarSync WAN driver unloading\n");
2695 pci_unregister_driver(&fst_driver);
2696 }
2697
2698 module_init(fst_init);
2699 module_exit(fst_cleanup_module);
linux 2.6 git repository for openrd