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drm/i915: add GEM GTT mapping support
[linux-2.6/linux-2.6-openrd.git] / drivers / net / irda / smsc-ircc2.c
blobb5360fe99d3a5669b89180f96462dc8340d065f5
1 /*********************************************************************
2 *
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Status: Experimental.
5 * Author: Daniele Peri (peri@csai.unipa.it)
6 * Created at:
7 * Modified at:
8 * Modified by:
9 *
10 * Copyright (c) 2002 Daniele Peri
11 * All Rights Reserved.
12 * Copyright (c) 2002 Jean Tourrilhes
13 * Copyright (c) 2006 Linus Walleij
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44 #include <linux/module.h>
45 #include <linux/kernel.h>
46 #include <linux/types.h>
47 #include <linux/skbuff.h>
48 #include <linux/netdevice.h>
49 #include <linux/ioport.h>
50 #include <linux/delay.h>
51 #include <linux/slab.h>
52 #include <linux/init.h>
53 #include <linux/rtnetlink.h>
54 #include <linux/serial_reg.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/pnp.h>
57 #include <linux/platform_device.h>
58
59 #include <asm/io.h>
60 #include <asm/dma.h>
61 #include <asm/byteorder.h>
62
63 #include <linux/spinlock.h>
64 #include <linux/pm.h>
65 #ifdef CONFIG_PCI
66 #include <linux/pci.h>
67 #endif
68
69 #include <net/irda/wrapper.h>
70 #include <net/irda/irda.h>
71 #include <net/irda/irda_device.h>
72
73 #include "smsc-ircc2.h"
74 #include "smsc-sio.h"
75
76
77 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
78 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
79 MODULE_LICENSE("GPL");
80
81 static int smsc_nopnp = 1;
82 module_param_named(nopnp, smsc_nopnp, bool, 0);
83 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
84
85 #define DMA_INVAL 255
86 static int ircc_dma = DMA_INVAL;
87 module_param(ircc_dma, int, 0);
88 MODULE_PARM_DESC(ircc_dma, "DMA channel");
89
90 #define IRQ_INVAL 255
91 static int ircc_irq = IRQ_INVAL;
92 module_param(ircc_irq, int, 0);
93 MODULE_PARM_DESC(ircc_irq, "IRQ line");
94
95 static int ircc_fir;
96 module_param(ircc_fir, int, 0);
97 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
98
99 static int ircc_sir;
100 module_param(ircc_sir, int, 0);
101 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
102
103 static int ircc_cfg;
104 module_param(ircc_cfg, int, 0);
105 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
106
107 static int ircc_transceiver;
108 module_param(ircc_transceiver, int, 0);
109 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
110
111 /* Types */
112
113 #ifdef CONFIG_PCI
114 struct smsc_ircc_subsystem_configuration {
115 unsigned short vendor; /* PCI vendor ID */
116 unsigned short device; /* PCI vendor ID */
117 unsigned short subvendor; /* PCI subsystem vendor ID */
118 unsigned short subdevice; /* PCI sybsystem device ID */
119 unsigned short sir_io; /* I/O port for SIR */
120 unsigned short fir_io; /* I/O port for FIR */
121 unsigned char fir_irq; /* FIR IRQ */
122 unsigned char fir_dma; /* FIR DMA */
123 unsigned short cfg_base; /* I/O port for chip configuration */
124 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
125 const char *name; /* name shown as info */
126 };
127 #endif
128
129 struct smsc_transceiver {
130 char *name;
131 void (*set_for_speed)(int fir_base, u32 speed);
132 int (*probe)(int fir_base);
133 };
134
135 struct smsc_chip {
136 char *name;
137 #if 0
138 u8 type;
139 #endif
140 u16 flags;
141 u8 devid;
142 u8 rev;
143 };
144
145 struct smsc_chip_address {
146 unsigned int cfg_base;
147 unsigned int type;
148 };
149
150 /* Private data for each instance */
151 struct smsc_ircc_cb {
152 struct net_device *netdev; /* Yes! we are some kind of netdevice */
153 struct net_device_stats stats;
154 struct irlap_cb *irlap; /* The link layer we are binded to */
155
156 chipio_t io; /* IrDA controller information */
157 iobuff_t tx_buff; /* Transmit buffer */
158 iobuff_t rx_buff; /* Receive buffer */
159 dma_addr_t tx_buff_dma;
160 dma_addr_t rx_buff_dma;
161
162 struct qos_info qos; /* QoS capabilities for this device */
163
164 spinlock_t lock; /* For serializing operations */
165
166 __u32 new_speed;
167 __u32 flags; /* Interface flags */
168
169 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
170 int tx_len; /* Number of frames in tx_buff */
171
172 int transceiver;
173 struct platform_device *pldev;
174 };
175
176 /* Constants */
177
178 #define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
179
180 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
181 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
182 #define SMSC_IRCC2_C_NET_TIMEOUT 0
183 #define SMSC_IRCC2_C_SIR_STOP 0
184
185 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
186
187 /* Prototypes */
188
189 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
190 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
191 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
192 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
193 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
194 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
195 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
196 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
197 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
198 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
199 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
200 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
201 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
202 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
203 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
204 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
205 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
206 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
207 #if SMSC_IRCC2_C_SIR_STOP
208 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
209 #endif
210 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
211 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
212 static int smsc_ircc_net_open(struct net_device *dev);
213 static int smsc_ircc_net_close(struct net_device *dev);
214 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
215 #if SMSC_IRCC2_C_NET_TIMEOUT
216 static void smsc_ircc_timeout(struct net_device *dev);
217 #endif
218 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
219 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
220 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
221 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
222 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
223
224 /* Probing */
225 static int __init smsc_ircc_look_for_chips(void);
226 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
227 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
228 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229 static int __init smsc_superio_fdc(unsigned short cfg_base);
230 static int __init smsc_superio_lpc(unsigned short cfg_base);
231 #ifdef CONFIG_PCI
232 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
233 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
234 static void __init preconfigure_ali_port(struct pci_dev *dev,
235 unsigned short port);
236 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
237 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
238 unsigned short ircc_fir,
239 unsigned short ircc_sir,
240 unsigned char ircc_dma,
241 unsigned char ircc_irq);
242 #endif
243
244 /* Transceivers specific functions */
245
246 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
247 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
248 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
249 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
250 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
251 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
252
253 /* Power Management */
254
255 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
256 static int smsc_ircc_resume(struct platform_device *dev);
257
258 static struct platform_driver smsc_ircc_driver = {
259 .suspend = smsc_ircc_suspend,
260 .resume = smsc_ircc_resume,
261 .driver = {
262 .name = SMSC_IRCC2_DRIVER_NAME,
263 },
264 };
265
266 /* Transceivers for SMSC-ircc */
267
268 static struct smsc_transceiver smsc_transceivers[] =
269 {
270 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
271 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
272 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
273 { NULL, NULL }
274 };
275 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
276
277 /* SMC SuperIO chipsets definitions */
278
279 #define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
280 #define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
281 #define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
282 #define SIR 0 /* SuperIO Chip has only slow IRDA */
283 #define FIR 4 /* SuperIO Chip has fast IRDA */
284 #define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
285
286 static struct smsc_chip __initdata fdc_chips_flat[] =
287 {
288 /* Base address 0x3f0 or 0x370 */
289 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
290 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
291 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
292 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
294 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
295 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
296 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
297 { NULL }
298 };
299
300 static struct smsc_chip __initdata fdc_chips_paged[] =
301 {
302 /* Base address 0x3f0 or 0x370 */
303 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
304 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
305 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
306 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
307 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
308 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
309 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
310 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
311 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
312 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
313 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
314 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
315 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
316 { NULL }
317 };
318
319 static struct smsc_chip __initdata lpc_chips_flat[] =
320 {
321 /* Base address 0x2E or 0x4E */
322 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
323 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
324 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
325 { NULL }
326 };
327
328 static struct smsc_chip __initdata lpc_chips_paged[] =
329 {
330 /* Base address 0x2E or 0x4E */
331 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
332 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
333 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
335 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
336 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
337 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
338 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
339 { NULL }
340 };
341
342 #define SMSCSIO_TYPE_FDC 1
343 #define SMSCSIO_TYPE_LPC 2
344 #define SMSCSIO_TYPE_FLAT 4
345 #define SMSCSIO_TYPE_PAGED 8
346
347 static struct smsc_chip_address __initdata possible_addresses[] =
348 {
349 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0, 0 }
355 };
356
357 /* Globals */
358
359 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
360 static unsigned short dev_count;
361
362 static inline void register_bank(int iobase, int bank)
363 {
364 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
365 iobase + IRCC_MASTER);
366 }
367
368 /* PNP hotplug support */
369 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
370 { .id = "SMCf010", .driver_data = 0 },
371 /* and presumably others */
372 { }
373 };
374 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
375
376 static int pnp_driver_registered;
377
378 #ifdef CONFIG_PNP
379 static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
380 const struct pnp_device_id *dev_id)
381 {
382 unsigned int firbase, sirbase;
383 u8 dma, irq;
384
385 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
386 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
387 return -EINVAL;
388
389 sirbase = pnp_port_start(dev, 0);
390 firbase = pnp_port_start(dev, 1);
391 dma = pnp_dma(dev, 0);
392 irq = pnp_irq(dev, 0);
393
394 if (smsc_ircc_open(firbase, sirbase, dma, irq))
395 return -ENODEV;
396
397 return 0;
398 }
399
400 static struct pnp_driver smsc_ircc_pnp_driver = {
401 .name = "smsc-ircc2",
402 .id_table = smsc_ircc_pnp_table,
403 .probe = smsc_ircc_pnp_probe,
404 };
405 #else /* CONFIG_PNP */
406 static struct pnp_driver smsc_ircc_pnp_driver;
407 #endif
408
409 /*******************************************************************************
410 *
411 *
412 * SMSC-ircc stuff
413 *
414 *
415 *******************************************************************************/
416
417 static int __init smsc_ircc_legacy_probe(void)
418 {
419 int ret = 0;
420
421 #ifdef CONFIG_PCI
422 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
423 /* Ignore errors from preconfiguration */
424 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
425 }
426 #endif
427
428 if (ircc_fir > 0 && ircc_sir > 0) {
429 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
430 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
431
432 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
433 ret = -ENODEV;
434 } else {
435 ret = -ENODEV;
436
437 /* try user provided configuration register base address */
438 if (ircc_cfg > 0) {
439 IRDA_MESSAGE(" Overriding configuration address "
440 "0x%04x\n", ircc_cfg);
441 if (!smsc_superio_fdc(ircc_cfg))
442 ret = 0;
443 if (!smsc_superio_lpc(ircc_cfg))
444 ret = 0;
445 }
446
447 if (smsc_ircc_look_for_chips() > 0)
448 ret = 0;
449 }
450 return ret;
451 }
452
453 /*
454 * Function smsc_ircc_init ()
455 *
456 * Initialize chip. Just try to find out how many chips we are dealing with
457 * and where they are
458 */
459 static int __init smsc_ircc_init(void)
460 {
461 int ret;
462
463 IRDA_DEBUG(1, "%s\n", __func__);
464
465 ret = platform_driver_register(&smsc_ircc_driver);
466 if (ret) {
467 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
468 return ret;
469 }
470
471 dev_count = 0;
472
473 if (smsc_nopnp || !pnp_platform_devices ||
474 ircc_cfg || ircc_fir || ircc_sir ||
475 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
476 ret = smsc_ircc_legacy_probe();
477 } else {
478 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
479 pnp_driver_registered = 1;
480 }
481
482 if (ret) {
483 if (pnp_driver_registered)
484 pnp_unregister_driver(&smsc_ircc_pnp_driver);
485 platform_driver_unregister(&smsc_ircc_driver);
486 }
487
488 return ret;
489 }
490
491 /*
492 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
493 *
494 * Try to open driver instance
495 *
496 */
497 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
498 {
499 struct smsc_ircc_cb *self;
500 struct net_device *dev;
501 int err;
502
503 IRDA_DEBUG(1, "%s\n", __func__);
504
505 err = smsc_ircc_present(fir_base, sir_base);
506 if (err)
507 goto err_out;
508
509 err = -ENOMEM;
510 if (dev_count >= ARRAY_SIZE(dev_self)) {
511 IRDA_WARNING("%s(), too many devices!\n", __func__);
512 goto err_out1;
513 }
514
515 /*
516 * Allocate new instance of the driver
517 */
518 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
519 if (!dev) {
520 IRDA_WARNING("%s() can't allocate net device\n", __func__);
521 goto err_out1;
522 }
523
524 dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
525 #if SMSC_IRCC2_C_NET_TIMEOUT
526 dev->tx_timeout = smsc_ircc_timeout;
527 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
528 #endif
529 dev->open = smsc_ircc_net_open;
530 dev->stop = smsc_ircc_net_close;
531 dev->do_ioctl = smsc_ircc_net_ioctl;
532 dev->get_stats = smsc_ircc_net_get_stats;
533
534 self = netdev_priv(dev);
535 self->netdev = dev;
536
537 /* Make ifconfig display some details */
538 dev->base_addr = self->io.fir_base = fir_base;
539 dev->irq = self->io.irq = irq;
540
541 /* Need to store self somewhere */
542 dev_self[dev_count] = self;
543 spin_lock_init(&self->lock);
544
545 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
546 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
547
548 self->rx_buff.head =
549 dma_alloc_coherent(NULL, self->rx_buff.truesize,
550 &self->rx_buff_dma, GFP_KERNEL);
551 if (self->rx_buff.head == NULL) {
552 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
553 driver_name);
554 goto err_out2;
555 }
556
557 self->tx_buff.head =
558 dma_alloc_coherent(NULL, self->tx_buff.truesize,
559 &self->tx_buff_dma, GFP_KERNEL);
560 if (self->tx_buff.head == NULL) {
561 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
562 driver_name);
563 goto err_out3;
564 }
565
566 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
567 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
568
569 self->rx_buff.in_frame = FALSE;
570 self->rx_buff.state = OUTSIDE_FRAME;
571 self->tx_buff.data = self->tx_buff.head;
572 self->rx_buff.data = self->rx_buff.head;
573
574 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
575 smsc_ircc_setup_qos(self);
576 smsc_ircc_init_chip(self);
577
578 if (ircc_transceiver > 0 &&
579 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
580 self->transceiver = ircc_transceiver;
581 else
582 smsc_ircc_probe_transceiver(self);
583
584 err = register_netdev(self->netdev);
585 if (err) {
586 IRDA_ERROR("%s, Network device registration failed!\n",
587 driver_name);
588 goto err_out4;
589 }
590
591 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
592 dev_count, NULL, 0);
593 if (IS_ERR(self->pldev)) {
594 err = PTR_ERR(self->pldev);
595 goto err_out5;
596 }
597 platform_set_drvdata(self->pldev, self);
598
599 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
600 dev_count++;
601
602 return 0;
603
604 err_out5:
605 unregister_netdev(self->netdev);
606
607 err_out4:
608 dma_free_coherent(NULL, self->tx_buff.truesize,
609 self->tx_buff.head, self->tx_buff_dma);
610 err_out3:
611 dma_free_coherent(NULL, self->rx_buff.truesize,
612 self->rx_buff.head, self->rx_buff_dma);
613 err_out2:
614 free_netdev(self->netdev);
615 dev_self[dev_count] = NULL;
616 err_out1:
617 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
618 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
619 err_out:
620 return err;
621 }
622
623 /*
624 * Function smsc_ircc_present(fir_base, sir_base)
625 *
626 * Check the smsc-ircc chip presence
627 *
628 */
629 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
630 {
631 unsigned char low, high, chip, config, dma, irq, version;
632
633 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
634 driver_name)) {
635 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
636 __func__, fir_base);
637 goto out1;
638 }
639
640 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
641 driver_name)) {
642 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
643 __func__, sir_base);
644 goto out2;
645 }
646
647 register_bank(fir_base, 3);
648
649 high = inb(fir_base + IRCC_ID_HIGH);
650 low = inb(fir_base + IRCC_ID_LOW);
651 chip = inb(fir_base + IRCC_CHIP_ID);
652 version = inb(fir_base + IRCC_VERSION);
653 config = inb(fir_base + IRCC_INTERFACE);
654 dma = config & IRCC_INTERFACE_DMA_MASK;
655 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
656
657 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
658 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
659 __func__, fir_base);
660 goto out3;
661 }
662 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
663 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
664 chip & 0x0f, version, fir_base, sir_base, dma, irq);
665
666 return 0;
667
668 out3:
669 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
670 out2:
671 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
672 out1:
673 return -ENODEV;
674 }
675
676 /*
677 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
678 *
679 * Setup I/O
680 *
681 */
682 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
683 unsigned int fir_base, unsigned int sir_base,
684 u8 dma, u8 irq)
685 {
686 unsigned char config, chip_dma, chip_irq;
687
688 register_bank(fir_base, 3);
689 config = inb(fir_base + IRCC_INTERFACE);
690 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
691 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
692
693 self->io.fir_base = fir_base;
694 self->io.sir_base = sir_base;
695 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
696 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
697 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
698 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
699
700 if (irq != IRQ_INVAL) {
701 if (irq != chip_irq)
702 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
703 driver_name, chip_irq, irq);
704 self->io.irq = irq;
705 } else
706 self->io.irq = chip_irq;
707
708 if (dma != DMA_INVAL) {
709 if (dma != chip_dma)
710 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
711 driver_name, chip_dma, dma);
712 self->io.dma = dma;
713 } else
714 self->io.dma = chip_dma;
715
716 }
717
718 /*
719 * Function smsc_ircc_setup_qos(self)
720 *
721 * Setup qos
722 *
723 */
724 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
725 {
726 /* Initialize QoS for this device */
727 irda_init_max_qos_capabilies(&self->qos);
728
729 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
730 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
731
732 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
733 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
734 irda_qos_bits_to_value(&self->qos);
735 }
736
737 /*
738 * Function smsc_ircc_init_chip(self)
739 *
740 * Init chip
741 *
742 */
743 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
744 {
745 int iobase = self->io.fir_base;
746
747 register_bank(iobase, 0);
748 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
749 outb(0x00, iobase + IRCC_MASTER);
750
751 register_bank(iobase, 1);
752 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
753 iobase + IRCC_SCE_CFGA);
754
755 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
756 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
757 iobase + IRCC_SCE_CFGB);
758 #else
759 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
760 iobase + IRCC_SCE_CFGB);
761 #endif
762 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
763 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
764
765 register_bank(iobase, 4);
766 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
767
768 register_bank(iobase, 0);
769 outb(0, iobase + IRCC_LCR_A);
770
771 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
772
773 /* Power on device */
774 outb(0x00, iobase + IRCC_MASTER);
775 }
776
777 /*
778 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
779 *
780 * Process IOCTL commands for this device
781 *
782 */
783 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
784 {
785 struct if_irda_req *irq = (struct if_irda_req *) rq;
786 struct smsc_ircc_cb *self;
787 unsigned long flags;
788 int ret = 0;
789
790 IRDA_ASSERT(dev != NULL, return -1;);
791
792 self = netdev_priv(dev);
793
794 IRDA_ASSERT(self != NULL, return -1;);
795
796 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
797
798 switch (cmd) {
799 case SIOCSBANDWIDTH: /* Set bandwidth */
800 if (!capable(CAP_NET_ADMIN))
801 ret = -EPERM;
802 else {
803 /* Make sure we are the only one touching
804 * self->io.speed and the hardware - Jean II */
805 spin_lock_irqsave(&self->lock, flags);
806 smsc_ircc_change_speed(self, irq->ifr_baudrate);
807 spin_unlock_irqrestore(&self->lock, flags);
808 }
809 break;
810 case SIOCSMEDIABUSY: /* Set media busy */
811 if (!capable(CAP_NET_ADMIN)) {
812 ret = -EPERM;
813 break;
814 }
815
816 irda_device_set_media_busy(self->netdev, TRUE);
817 break;
818 case SIOCGRECEIVING: /* Check if we are receiving right now */
819 irq->ifr_receiving = smsc_ircc_is_receiving(self);
820 break;
821 #if 0
822 case SIOCSDTRRTS:
823 if (!capable(CAP_NET_ADMIN)) {
824 ret = -EPERM;
825 break;
826 }
827 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
828 break;
829 #endif
830 default:
831 ret = -EOPNOTSUPP;
832 }
833
834 return ret;
835 }
836
837 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
838 {
839 struct smsc_ircc_cb *self = netdev_priv(dev);
840
841 return &self->stats;
842 }
843
844 #if SMSC_IRCC2_C_NET_TIMEOUT
845 /*
846 * Function smsc_ircc_timeout (struct net_device *dev)
847 *
848 * The networking timeout management.
849 *
850 */
851
852 static void smsc_ircc_timeout(struct net_device *dev)
853 {
854 struct smsc_ircc_cb *self = netdev_priv(dev);
855 unsigned long flags;
856
857 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
858 dev->name, self->io.speed);
859 spin_lock_irqsave(&self->lock, flags);
860 smsc_ircc_sir_start(self);
861 smsc_ircc_change_speed(self, self->io.speed);
862 dev->trans_start = jiffies;
863 netif_wake_queue(dev);
864 spin_unlock_irqrestore(&self->lock, flags);
865 }
866 #endif
867
868 /*
869 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
870 *
871 * Transmits the current frame until FIFO is full, then
872 * waits until the next transmit interrupt, and continues until the
873 * frame is transmitted.
874 */
875 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
876 {
877 struct smsc_ircc_cb *self;
878 unsigned long flags;
879 s32 speed;
880
881 IRDA_DEBUG(1, "%s\n", __func__);
882
883 IRDA_ASSERT(dev != NULL, return 0;);
884
885 self = netdev_priv(dev);
886 IRDA_ASSERT(self != NULL, return 0;);
887
888 netif_stop_queue(dev);
889
890 /* Make sure test of self->io.speed & speed change are atomic */
891 spin_lock_irqsave(&self->lock, flags);
892
893 /* Check if we need to change the speed */
894 speed = irda_get_next_speed(skb);
895 if (speed != self->io.speed && speed != -1) {
896 /* Check for empty frame */
897 if (!skb->len) {
898 /*
899 * We send frames one by one in SIR mode (no
900 * pipelining), so at this point, if we were sending
901 * a previous frame, we just received the interrupt
902 * telling us it is finished (UART_IIR_THRI).
903 * Therefore, waiting for the transmitter to really
904 * finish draining the fifo won't take too long.
905 * And the interrupt handler is not expected to run.
906 * - Jean II */
907 smsc_ircc_sir_wait_hw_transmitter_finish(self);
908 smsc_ircc_change_speed(self, speed);
909 spin_unlock_irqrestore(&self->lock, flags);
910 dev_kfree_skb(skb);
911 return 0;
912 }
913 self->new_speed = speed;
914 }
915
916 /* Init tx buffer */
917 self->tx_buff.data = self->tx_buff.head;
918
919 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
920 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
921 self->tx_buff.truesize);
922
923 self->stats.tx_bytes += self->tx_buff.len;
924
925 /* Turn on transmit finished interrupt. Will fire immediately! */
926 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
927
928 spin_unlock_irqrestore(&self->lock, flags);
929
930 dev_kfree_skb(skb);
931
932 return 0;
933 }
934
935 /*
936 * Function smsc_ircc_set_fir_speed (self, baud)
937 *
938 * Change the speed of the device
939 *
940 */
941 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
942 {
943 int fir_base, ir_mode, ctrl, fast;
944
945 IRDA_ASSERT(self != NULL, return;);
946 fir_base = self->io.fir_base;
947
948 self->io.speed = speed;
949
950 switch (speed) {
951 default:
952 case 576000:
953 ir_mode = IRCC_CFGA_IRDA_HDLC;
954 ctrl = IRCC_CRC;
955 fast = 0;
956 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
957 break;
958 case 1152000:
959 ir_mode = IRCC_CFGA_IRDA_HDLC;
960 ctrl = IRCC_1152 | IRCC_CRC;
961 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
962 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
963 __func__);
964 break;
965 case 4000000:
966 ir_mode = IRCC_CFGA_IRDA_4PPM;
967 ctrl = IRCC_CRC;
968 fast = IRCC_LCR_A_FAST;
969 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
970 __func__);
971 break;
972 }
973 #if 0
974 Now in tranceiver!
975 /* This causes an interrupt */
976 register_bank(fir_base, 0);
977 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
978 #endif
979
980 register_bank(fir_base, 1);
981 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
982
983 register_bank(fir_base, 4);
984 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
985 }
986
987 /*
988 * Function smsc_ircc_fir_start(self)
989 *
990 * Change the speed of the device
991 *
992 */
993 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
994 {
995 struct net_device *dev;
996 int fir_base;
997
998 IRDA_DEBUG(1, "%s\n", __func__);
999
1000 IRDA_ASSERT(self != NULL, return;);
1001 dev = self->netdev;
1002 IRDA_ASSERT(dev != NULL, return;);
1003
1004 fir_base = self->io.fir_base;
1005
1006 /* Reset everything */
1007
1008 /* Install FIR transmit handler */
1009 dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
1010
1011 /* Clear FIFO */
1012 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1013
1014 /* Enable interrupt */
1015 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1016
1017 register_bank(fir_base, 1);
1018
1019 /* Select the TX/RX interface */
1020 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1021 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1022 fir_base + IRCC_SCE_CFGB);
1023 #else
1024 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1025 fir_base + IRCC_SCE_CFGB);
1026 #endif
1027 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1028
1029 /* Enable SCE interrupts */
1030 outb(0, fir_base + IRCC_MASTER);
1031 register_bank(fir_base, 0);
1032 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1033 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1034 }
1035
1036 /*
1037 * Function smsc_ircc_fir_stop(self, baud)
1038 *
1039 * Change the speed of the device
1040 *
1041 */
1042 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1043 {
1044 int fir_base;
1045
1046 IRDA_DEBUG(1, "%s\n", __func__);
1047
1048 IRDA_ASSERT(self != NULL, return;);
1049
1050 fir_base = self->io.fir_base;
1051 register_bank(fir_base, 0);
1052 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1053 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1054 }
1055
1056
1057 /*
1058 * Function smsc_ircc_change_speed(self, baud)
1059 *
1060 * Change the speed of the device
1061 *
1062 * This function *must* be called with spinlock held, because it may
1063 * be called from the irq handler. - Jean II
1064 */
1065 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1066 {
1067 struct net_device *dev;
1068 int last_speed_was_sir;
1069
1070 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1071
1072 IRDA_ASSERT(self != NULL, return;);
1073 dev = self->netdev;
1074
1075 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1076
1077 #if 0
1078 /* Temp Hack */
1079 speed= 1152000;
1080 self->io.speed = speed;
1081 last_speed_was_sir = 0;
1082 smsc_ircc_fir_start(self);
1083 #endif
1084
1085 if (self->io.speed == 0)
1086 smsc_ircc_sir_start(self);
1087
1088 #if 0
1089 if (!last_speed_was_sir) speed = self->io.speed;
1090 #endif
1091
1092 if (self->io.speed != speed)
1093 smsc_ircc_set_transceiver_for_speed(self, speed);
1094
1095 self->io.speed = speed;
1096
1097 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1098 if (!last_speed_was_sir) {
1099 smsc_ircc_fir_stop(self);
1100 smsc_ircc_sir_start(self);
1101 }
1102 smsc_ircc_set_sir_speed(self, speed);
1103 } else {
1104 if (last_speed_was_sir) {
1105 #if SMSC_IRCC2_C_SIR_STOP
1106 smsc_ircc_sir_stop(self);
1107 #endif
1108 smsc_ircc_fir_start(self);
1109 }
1110 smsc_ircc_set_fir_speed(self, speed);
1111
1112 #if 0
1113 self->tx_buff.len = 10;
1114 self->tx_buff.data = self->tx_buff.head;
1115
1116 smsc_ircc_dma_xmit(self, 4000);
1117 #endif
1118 /* Be ready for incoming frames */
1119 smsc_ircc_dma_receive(self);
1120 }
1121
1122 netif_wake_queue(dev);
1123 }
1124
1125 /*
1126 * Function smsc_ircc_set_sir_speed (self, speed)
1127 *
1128 * Set speed of IrDA port to specified baudrate
1129 *
1130 */
1131 void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1132 {
1133 int iobase;
1134 int fcr; /* FIFO control reg */
1135 int lcr; /* Line control reg */
1136 int divisor;
1137
1138 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1139
1140 IRDA_ASSERT(self != NULL, return;);
1141 iobase = self->io.sir_base;
1142
1143 /* Update accounting for new speed */
1144 self->io.speed = speed;
1145
1146 /* Turn off interrupts */
1147 outb(0, iobase + UART_IER);
1148
1149 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1150
1151 fcr = UART_FCR_ENABLE_FIFO;
1152
1153 /*
1154 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1155 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1156 * about this timeout since it will always be fast enough.
1157 */
1158 fcr |= self->io.speed < 38400 ?
1159 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1160
1161 /* IrDA ports use 8N1 */
1162 lcr = UART_LCR_WLEN8;
1163
1164 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1165 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1166 outb(divisor >> 8, iobase + UART_DLM);
1167 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1168 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1169
1170 /* Turn on interrups */
1171 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1172
1173 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1174 }
1175
1176
1177 /*
1178 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1179 *
1180 * Transmit the frame!
1181 *
1182 */
1183 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1184 {
1185 struct smsc_ircc_cb *self;
1186 unsigned long flags;
1187 s32 speed;
1188 int mtt;
1189
1190 IRDA_ASSERT(dev != NULL, return 0;);
1191 self = netdev_priv(dev);
1192 IRDA_ASSERT(self != NULL, return 0;);
1193
1194 netif_stop_queue(dev);
1195
1196 /* Make sure test of self->io.speed & speed change are atomic */
1197 spin_lock_irqsave(&self->lock, flags);
1198
1199 /* Check if we need to change the speed after this frame */
1200 speed = irda_get_next_speed(skb);
1201 if (speed != self->io.speed && speed != -1) {
1202 /* Check for empty frame */
1203 if (!skb->len) {
1204 /* Note : you should make sure that speed changes
1205 * are not going to corrupt any outgoing frame.
1206 * Look at nsc-ircc for the gory details - Jean II */
1207 smsc_ircc_change_speed(self, speed);
1208 spin_unlock_irqrestore(&self->lock, flags);
1209 dev_kfree_skb(skb);
1210 return 0;
1211 }
1212
1213 self->new_speed = speed;
1214 }
1215
1216 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1217
1218 self->tx_buff.len = skb->len;
1219 self->tx_buff.data = self->tx_buff.head;
1220
1221 mtt = irda_get_mtt(skb);
1222 if (mtt) {
1223 int bofs;
1224
1225 /*
1226 * Compute how many BOFs (STA or PA's) we need to waste the
1227 * min turn time given the speed of the link.
1228 */
1229 bofs = mtt * (self->io.speed / 1000) / 8000;
1230 if (bofs > 4095)
1231 bofs = 4095;
1232
1233 smsc_ircc_dma_xmit(self, bofs);
1234 } else {
1235 /* Transmit frame */
1236 smsc_ircc_dma_xmit(self, 0);
1237 }
1238
1239 spin_unlock_irqrestore(&self->lock, flags);
1240 dev_kfree_skb(skb);
1241
1242 return 0;
1243 }
1244
1245 /*
1246 * Function smsc_ircc_dma_xmit (self, bofs)
1247 *
1248 * Transmit data using DMA
1249 *
1250 */
1251 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1252 {
1253 int iobase = self->io.fir_base;
1254 u8 ctrl;
1255
1256 IRDA_DEBUG(3, "%s\n", __func__);
1257 #if 1
1258 /* Disable Rx */
1259 register_bank(iobase, 0);
1260 outb(0x00, iobase + IRCC_LCR_B);
1261 #endif
1262 register_bank(iobase, 1);
1263 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1264 iobase + IRCC_SCE_CFGB);
1265
1266 self->io.direction = IO_XMIT;
1267
1268 /* Set BOF additional count for generating the min turn time */
1269 register_bank(iobase, 4);
1270 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1271 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1272 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1273
1274 /* Set max Tx frame size */
1275 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1276 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1277
1278 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1279
1280 /* Enable burst mode chip Tx DMA */
1281 register_bank(iobase, 1);
1282 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1283 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1284
1285 /* Setup DMA controller (must be done after enabling chip DMA) */
1286 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1287 DMA_TX_MODE);
1288
1289 /* Enable interrupt */
1290
1291 register_bank(iobase, 0);
1292 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1293 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1294
1295 /* Enable transmit */
1296 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1297 }
1298
1299 /*
1300 * Function smsc_ircc_dma_xmit_complete (self)
1301 *
1302 * The transfer of a frame in finished. This function will only be called
1303 * by the interrupt handler
1304 *
1305 */
1306 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1307 {
1308 int iobase = self->io.fir_base;
1309
1310 IRDA_DEBUG(3, "%s\n", __func__);
1311 #if 0
1312 /* Disable Tx */
1313 register_bank(iobase, 0);
1314 outb(0x00, iobase + IRCC_LCR_B);
1315 #endif
1316 register_bank(iobase, 1);
1317 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1318 iobase + IRCC_SCE_CFGB);
1319
1320 /* Check for underrun! */
1321 register_bank(iobase, 0);
1322 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1323 self->stats.tx_errors++;
1324 self->stats.tx_fifo_errors++;
1325
1326 /* Reset error condition */
1327 register_bank(iobase, 0);
1328 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1329 outb(0x00, iobase + IRCC_MASTER);
1330 } else {
1331 self->stats.tx_packets++;
1332 self->stats.tx_bytes += self->tx_buff.len;
1333 }
1334
1335 /* Check if it's time to change the speed */
1336 if (self->new_speed) {
1337 smsc_ircc_change_speed(self, self->new_speed);
1338 self->new_speed = 0;
1339 }
1340
1341 netif_wake_queue(self->netdev);
1342 }
1343
1344 /*
1345 * Function smsc_ircc_dma_receive(self)
1346 *
1347 * Get ready for receiving a frame. The device will initiate a DMA
1348 * if it starts to receive a frame.
1349 *
1350 */
1351 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1352 {
1353 int iobase = self->io.fir_base;
1354 #if 0
1355 /* Turn off chip DMA */
1356 register_bank(iobase, 1);
1357 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1358 iobase + IRCC_SCE_CFGB);
1359 #endif
1360
1361 /* Disable Tx */
1362 register_bank(iobase, 0);
1363 outb(0x00, iobase + IRCC_LCR_B);
1364
1365 /* Turn off chip DMA */
1366 register_bank(iobase, 1);
1367 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1368 iobase + IRCC_SCE_CFGB);
1369
1370 self->io.direction = IO_RECV;
1371 self->rx_buff.data = self->rx_buff.head;
1372
1373 /* Set max Rx frame size */
1374 register_bank(iobase, 4);
1375 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1376 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1377
1378 /* Setup DMA controller */
1379 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1380 DMA_RX_MODE);
1381
1382 /* Enable burst mode chip Rx DMA */
1383 register_bank(iobase, 1);
1384 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1385 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1386
1387 /* Enable interrupt */
1388 register_bank(iobase, 0);
1389 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1390 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1391
1392 /* Enable receiver */
1393 register_bank(iobase, 0);
1394 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1395 iobase + IRCC_LCR_B);
1396
1397 return 0;
1398 }
1399
1400 /*
1401 * Function smsc_ircc_dma_receive_complete(self)
1402 *
1403 * Finished with receiving frames
1404 *
1405 */
1406 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1407 {
1408 struct sk_buff *skb;
1409 int len, msgcnt, lsr;
1410 int iobase = self->io.fir_base;
1411
1412 register_bank(iobase, 0);
1413
1414 IRDA_DEBUG(3, "%s\n", __func__);
1415 #if 0
1416 /* Disable Rx */
1417 register_bank(iobase, 0);
1418 outb(0x00, iobase + IRCC_LCR_B);
1419 #endif
1420 register_bank(iobase, 0);
1421 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1422 lsr= inb(iobase + IRCC_LSR);
1423 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1424
1425 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1426 get_dma_residue(self->io.dma));
1427
1428 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1429
1430 /* Look for errors */
1431 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1432 self->stats.rx_errors++;
1433 if (lsr & IRCC_LSR_FRAME_ERROR)
1434 self->stats.rx_frame_errors++;
1435 if (lsr & IRCC_LSR_CRC_ERROR)
1436 self->stats.rx_crc_errors++;
1437 if (lsr & IRCC_LSR_SIZE_ERROR)
1438 self->stats.rx_length_errors++;
1439 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1440 self->stats.rx_length_errors++;
1441 return;
1442 }
1443
1444 /* Remove CRC */
1445 len -= self->io.speed < 4000000 ? 2 : 4;
1446
1447 if (len < 2 || len > 2050) {
1448 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1449 return;
1450 }
1451 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1452
1453 skb = dev_alloc_skb(len + 1);
1454 if (!skb) {
1455 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1456 __func__);
1457 return;
1458 }
1459 /* Make sure IP header gets aligned */
1460 skb_reserve(skb, 1);
1461
1462 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1463 self->stats.rx_packets++;
1464 self->stats.rx_bytes += len;
1465
1466 skb->dev = self->netdev;
1467 skb_reset_mac_header(skb);
1468 skb->protocol = htons(ETH_P_IRDA);
1469 netif_rx(skb);
1470 }
1471
1472 /*
1473 * Function smsc_ircc_sir_receive (self)
1474 *
1475 * Receive one frame from the infrared port
1476 *
1477 */
1478 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1479 {
1480 int boguscount = 0;
1481 int iobase;
1482
1483 IRDA_ASSERT(self != NULL, return;);
1484
1485 iobase = self->io.sir_base;
1486
1487 /*
1488 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1489 * async_unwrap_char will deliver all found frames
1490 */
1491 do {
1492 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1493 inb(iobase + UART_RX));
1494
1495 /* Make sure we don't stay here to long */
1496 if (boguscount++ > 32) {
1497 IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1498 break;
1499 }
1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1501 }
1502
1503
1504 /*
1505 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1506 *
1507 * An interrupt from the chip has arrived. Time to do some work
1508 *
1509 */
1510 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1511 {
1512 struct net_device *dev = dev_id;
1513 struct smsc_ircc_cb *self = netdev_priv(dev);
1514 int iobase, iir, lcra, lsr;
1515 irqreturn_t ret = IRQ_NONE;
1516
1517 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1518 spin_lock(&self->lock);
1519
1520 /* Check if we should use the SIR interrupt handler */
1521 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1522 ret = smsc_ircc_interrupt_sir(dev);
1523 goto irq_ret_unlock;
1524 }
1525
1526 iobase = self->io.fir_base;
1527
1528 register_bank(iobase, 0);
1529 iir = inb(iobase + IRCC_IIR);
1530 if (iir == 0)
1531 goto irq_ret_unlock;
1532 ret = IRQ_HANDLED;
1533
1534 /* Disable interrupts */
1535 outb(0, iobase + IRCC_IER);
1536 lcra = inb(iobase + IRCC_LCR_A);
1537 lsr = inb(iobase + IRCC_LSR);
1538
1539 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1540
1541 if (iir & IRCC_IIR_EOM) {
1542 if (self->io.direction == IO_RECV)
1543 smsc_ircc_dma_receive_complete(self);
1544 else
1545 smsc_ircc_dma_xmit_complete(self);
1546
1547 smsc_ircc_dma_receive(self);
1548 }
1549
1550 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1551 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1552 }
1553
1554 /* Enable interrupts again */
1555
1556 register_bank(iobase, 0);
1557 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1558
1559 irq_ret_unlock:
1560 spin_unlock(&self->lock);
1561
1562 return ret;
1563 }
1564
1565 /*
1566 * Function irport_interrupt_sir (irq, dev_id)
1567 *
1568 * Interrupt handler for SIR modes
1569 */
1570 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1571 {
1572 struct smsc_ircc_cb *self = netdev_priv(dev);
1573 int boguscount = 0;
1574 int iobase;
1575 int iir, lsr;
1576
1577 /* Already locked comming here in smsc_ircc_interrupt() */
1578 /*spin_lock(&self->lock);*/
1579
1580 iobase = self->io.sir_base;
1581
1582 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1583 if (iir == 0)
1584 return IRQ_NONE;
1585 while (iir) {
1586 /* Clear interrupt */
1587 lsr = inb(iobase + UART_LSR);
1588
1589 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1590 __func__, iir, lsr, iobase);
1591
1592 switch (iir) {
1593 case UART_IIR_RLSI:
1594 IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1595 break;
1596 case UART_IIR_RDI:
1597 /* Receive interrupt */
1598 smsc_ircc_sir_receive(self);
1599 break;
1600 case UART_IIR_THRI:
1601 if (lsr & UART_LSR_THRE)
1602 /* Transmitter ready for data */
1603 smsc_ircc_sir_write_wakeup(self);
1604 break;
1605 default:
1606 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1607 __func__, iir);
1608 break;
1609 }
1610
1611 /* Make sure we don't stay here to long */
1612 if (boguscount++ > 100)
1613 break;
1614
1615 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1616 }
1617 /*spin_unlock(&self->lock);*/
1618 return IRQ_HANDLED;
1619 }
1620
1621
1622 #if 0 /* unused */
1623 /*
1624 * Function ircc_is_receiving (self)
1625 *
1626 * Return TRUE is we are currently receiving a frame
1627 *
1628 */
1629 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1630 {
1631 int status = FALSE;
1632 /* int iobase; */
1633
1634 IRDA_DEBUG(1, "%s\n", __func__);
1635
1636 IRDA_ASSERT(self != NULL, return FALSE;);
1637
1638 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1639 get_dma_residue(self->io.dma));
1640
1641 status = (self->rx_buff.state != OUTSIDE_FRAME);
1642
1643 return status;
1644 }
1645 #endif /* unused */
1646
1647 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1648 {
1649 int error;
1650
1651 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1652 self->netdev->name, self->netdev);
1653 if (error)
1654 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1655 __func__, self->io.irq, error);
1656
1657 return error;
1658 }
1659
1660 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1661 {
1662 unsigned long flags;
1663
1664 spin_lock_irqsave(&self->lock, flags);
1665
1666 self->io.speed = 0;
1667 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1668
1669 spin_unlock_irqrestore(&self->lock, flags);
1670 }
1671
1672 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1673 {
1674 int iobase = self->io.fir_base;
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(&self->lock, flags);
1678
1679 register_bank(iobase, 0);
1680 outb(0, iobase + IRCC_IER);
1681 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1682 outb(0x00, iobase + IRCC_MASTER);
1683
1684 spin_unlock_irqrestore(&self->lock, flags);
1685 }
1686
1687
1688 /*
1689 * Function smsc_ircc_net_open (dev)
1690 *
1691 * Start the device
1692 *
1693 */
1694 static int smsc_ircc_net_open(struct net_device *dev)
1695 {
1696 struct smsc_ircc_cb *self;
1697 char hwname[16];
1698
1699 IRDA_DEBUG(1, "%s\n", __func__);
1700
1701 IRDA_ASSERT(dev != NULL, return -1;);
1702 self = netdev_priv(dev);
1703 IRDA_ASSERT(self != NULL, return 0;);
1704
1705 if (self->io.suspended) {
1706 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1707 return -EAGAIN;
1708 }
1709
1710 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1711 (void *) dev)) {
1712 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1713 __func__, self->io.irq);
1714 return -EAGAIN;
1715 }
1716
1717 smsc_ircc_start_interrupts(self);
1718
1719 /* Give self a hardware name */
1720 /* It would be cool to offer the chip revision here - Jean II */
1721 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1722
1723 /*
1724 * Open new IrLAP layer instance, now that everything should be
1725 * initialized properly
1726 */
1727 self->irlap = irlap_open(dev, &self->qos, hwname);
1728
1729 /*
1730 * Always allocate the DMA channel after the IRQ,
1731 * and clean up on failure.
1732 */
1733 if (request_dma(self->io.dma, dev->name)) {
1734 smsc_ircc_net_close(dev);
1735
1736 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1737 __func__, self->io.dma);
1738 return -EAGAIN;
1739 }
1740
1741 netif_start_queue(dev);
1742
1743 return 0;
1744 }
1745
1746 /*
1747 * Function smsc_ircc_net_close (dev)
1748 *
1749 * Stop the device
1750 *
1751 */
1752 static int smsc_ircc_net_close(struct net_device *dev)
1753 {
1754 struct smsc_ircc_cb *self;
1755
1756 IRDA_DEBUG(1, "%s\n", __func__);
1757
1758 IRDA_ASSERT(dev != NULL, return -1;);
1759 self = netdev_priv(dev);
1760 IRDA_ASSERT(self != NULL, return 0;);
1761
1762 /* Stop device */
1763 netif_stop_queue(dev);
1764
1765 /* Stop and remove instance of IrLAP */
1766 if (self->irlap)
1767 irlap_close(self->irlap);
1768 self->irlap = NULL;
1769
1770 smsc_ircc_stop_interrupts(self);
1771
1772 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1773 if (!self->io.suspended)
1774 free_irq(self->io.irq, dev);
1775
1776 disable_dma(self->io.dma);
1777 free_dma(self->io.dma);
1778
1779 return 0;
1780 }
1781
1782 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1783 {
1784 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1785
1786 if (!self->io.suspended) {
1787 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1788
1789 rtnl_lock();
1790 if (netif_running(self->netdev)) {
1791 netif_device_detach(self->netdev);
1792 smsc_ircc_stop_interrupts(self);
1793 free_irq(self->io.irq, self->netdev);
1794 disable_dma(self->io.dma);
1795 }
1796 self->io.suspended = 1;
1797 rtnl_unlock();
1798 }
1799
1800 return 0;
1801 }
1802
1803 static int smsc_ircc_resume(struct platform_device *dev)
1804 {
1805 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1806
1807 if (self->io.suspended) {
1808 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1809
1810 rtnl_lock();
1811 smsc_ircc_init_chip(self);
1812 if (netif_running(self->netdev)) {
1813 if (smsc_ircc_request_irq(self)) {
1814 /*
1815 * Don't fail resume process, just kill this
1816 * network interface
1817 */
1818 unregister_netdevice(self->netdev);
1819 } else {
1820 enable_dma(self->io.dma);
1821 smsc_ircc_start_interrupts(self);
1822 netif_device_attach(self->netdev);
1823 }
1824 }
1825 self->io.suspended = 0;
1826 rtnl_unlock();
1827 }
1828 return 0;
1829 }
1830
1831 /*
1832 * Function smsc_ircc_close (self)
1833 *
1834 * Close driver instance
1835 *
1836 */
1837 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1838 {
1839 IRDA_DEBUG(1, "%s\n", __func__);
1840
1841 IRDA_ASSERT(self != NULL, return -1;);
1842
1843 platform_device_unregister(self->pldev);
1844
1845 /* Remove netdevice */
1846 unregister_netdev(self->netdev);
1847
1848 smsc_ircc_stop_interrupts(self);
1849
1850 /* Release the PORTS that this driver is using */
1851 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1852 self->io.fir_base);
1853
1854 release_region(self->io.fir_base, self->io.fir_ext);
1855
1856 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1857 self->io.sir_base);
1858
1859 release_region(self->io.sir_base, self->io.sir_ext);
1860
1861 if (self->tx_buff.head)
1862 dma_free_coherent(NULL, self->tx_buff.truesize,
1863 self->tx_buff.head, self->tx_buff_dma);
1864
1865 if (self->rx_buff.head)
1866 dma_free_coherent(NULL, self->rx_buff.truesize,
1867 self->rx_buff.head, self->rx_buff_dma);
1868
1869 free_netdev(self->netdev);
1870
1871 return 0;
1872 }
1873
1874 static void __exit smsc_ircc_cleanup(void)
1875 {
1876 int i;
1877
1878 IRDA_DEBUG(1, "%s\n", __func__);
1879
1880 for (i = 0; i < 2; i++) {
1881 if (dev_self[i])
1882 smsc_ircc_close(dev_self[i]);
1883 }
1884
1885 if (pnp_driver_registered)
1886 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1887
1888 platform_driver_unregister(&smsc_ircc_driver);
1889 }
1890
1891 /*
1892 * Start SIR operations
1893 *
1894 * This function *must* be called with spinlock held, because it may
1895 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1896 */
1897 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1898 {
1899 struct net_device *dev;
1900 int fir_base, sir_base;
1901
1902 IRDA_DEBUG(3, "%s\n", __func__);
1903
1904 IRDA_ASSERT(self != NULL, return;);
1905 dev = self->netdev;
1906 IRDA_ASSERT(dev != NULL, return;);
1907 dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1908
1909 fir_base = self->io.fir_base;
1910 sir_base = self->io.sir_base;
1911
1912 /* Reset everything */
1913 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1914
1915 #if SMSC_IRCC2_C_SIR_STOP
1916 /*smsc_ircc_sir_stop(self);*/
1917 #endif
1918
1919 register_bank(fir_base, 1);
1920 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1921
1922 /* Initialize UART */
1923 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1924 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1925
1926 /* Turn on interrups */
1927 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1928
1929 IRDA_DEBUG(3, "%s() - exit\n", __func__);
1930
1931 outb(0x00, fir_base + IRCC_MASTER);
1932 }
1933
1934 #if SMSC_IRCC2_C_SIR_STOP
1935 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1936 {
1937 int iobase;
1938
1939 IRDA_DEBUG(3, "%s\n", __func__);
1940 iobase = self->io.sir_base;
1941
1942 /* Reset UART */
1943 outb(0, iobase + UART_MCR);
1944
1945 /* Turn off interrupts */
1946 outb(0, iobase + UART_IER);
1947 }
1948 #endif
1949
1950 /*
1951 * Function smsc_sir_write_wakeup (self)
1952 *
1953 * Called by the SIR interrupt handler when there's room for more data.
1954 * If we have more packets to send, we send them here.
1955 *
1956 */
1957 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1958 {
1959 int actual = 0;
1960 int iobase;
1961 int fcr;
1962
1963 IRDA_ASSERT(self != NULL, return;);
1964
1965 IRDA_DEBUG(4, "%s\n", __func__);
1966
1967 iobase = self->io.sir_base;
1968
1969 /* Finished with frame? */
1970 if (self->tx_buff.len > 0) {
1971 /* Write data left in transmit buffer */
1972 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1973 self->tx_buff.data, self->tx_buff.len);
1974 self->tx_buff.data += actual;
1975 self->tx_buff.len -= actual;
1976 } else {
1977
1978 /*if (self->tx_buff.len ==0) {*/
1979
1980 /*
1981 * Now serial buffer is almost free & we can start
1982 * transmission of another packet. But first we must check
1983 * if we need to change the speed of the hardware
1984 */
1985 if (self->new_speed) {
1986 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1987 __func__, self->new_speed);
1988 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1989 smsc_ircc_change_speed(self, self->new_speed);
1990 self->new_speed = 0;
1991 } else {
1992 /* Tell network layer that we want more frames */
1993 netif_wake_queue(self->netdev);
1994 }
1995 self->stats.tx_packets++;
1996
1997 if (self->io.speed <= 115200) {
1998 /*
1999 * Reset Rx FIFO to make sure that all reflected transmit data
2000 * is discarded. This is needed for half duplex operation
2001 */
2002 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2003 fcr |= self->io.speed < 38400 ?
2004 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2005
2006 outb(fcr, iobase + UART_FCR);
2007
2008 /* Turn on receive interrupts */
2009 outb(UART_IER_RDI, iobase + UART_IER);
2010 }
2011 }
2012 }
2013
2014 /*
2015 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2016 *
2017 * Fill Tx FIFO with transmit data
2018 *
2019 */
2020 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2021 {
2022 int actual = 0;
2023
2024 /* Tx FIFO should be empty! */
2025 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2026 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
2027 return 0;
2028 }
2029
2030 /* Fill FIFO with current frame */
2031 while (fifo_size-- > 0 && actual < len) {
2032 /* Transmit next byte */
2033 outb(buf[actual], iobase + UART_TX);
2034 actual++;
2035 }
2036 return actual;
2037 }
2038
2039 /*
2040 * Function smsc_ircc_is_receiving (self)
2041 *
2042 * Returns true is we are currently receiving data
2043 *
2044 */
2045 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2046 {
2047 return (self->rx_buff.state != OUTSIDE_FRAME);
2048 }
2049
2050
2051 /*
2052 * Function smsc_ircc_probe_transceiver(self)
2053 *
2054 * Tries to find the used Transceiver
2055 *
2056 */
2057 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2058 {
2059 unsigned int i;
2060
2061 IRDA_ASSERT(self != NULL, return;);
2062
2063 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2064 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2065 IRDA_MESSAGE(" %s transceiver found\n",
2066 smsc_transceivers[i].name);
2067 self->transceiver= i + 1;
2068 return;
2069 }
2070
2071 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2072 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2073
2074 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2075 }
2076
2077
2078 /*
2079 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2080 *
2081 * Set the transceiver according to the speed
2082 *
2083 */
2084 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2085 {
2086 unsigned int trx;
2087
2088 trx = self->transceiver;
2089 if (trx > 0)
2090 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2091 }
2092
2093 /*
2094 * Function smsc_ircc_wait_hw_transmitter_finish ()
2095 *
2096 * Wait for the real end of HW transmission
2097 *
2098 * The UART is a strict FIFO, and we get called only when we have finished
2099 * pushing data to the FIFO, so the maximum amount of time we must wait
2100 * is only for the FIFO to drain out.
2101 *
2102 * We use a simple calibrated loop. We may need to adjust the loop
2103 * delay (udelay) to balance I/O traffic and latency. And we also need to
2104 * adjust the maximum timeout.
2105 * It would probably be better to wait for the proper interrupt,
2106 * but it doesn't seem to be available.
2107 *
2108 * We can't use jiffies or kernel timers because :
2109 * 1) We are called from the interrupt handler, which disable softirqs,
2110 * so jiffies won't be increased
2111 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2112 * want to wait that long to detect stuck hardware.
2113 * Jean II
2114 */
2115
2116 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2117 {
2118 int iobase = self->io.sir_base;
2119 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2120
2121 /* Calibrated busy loop */
2122 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2123 udelay(1);
2124
2125 if (count == 0)
2126 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
2127 }
2128
2129
2130 /* PROBING
2131 *
2132 * REVISIT we can be told about the device by PNP, and should use that info
2133 * instead of probing hardware and creating a platform_device ...
2134 */
2135
2136 static int __init smsc_ircc_look_for_chips(void)
2137 {
2138 struct smsc_chip_address *address;
2139 char *type;
2140 unsigned int cfg_base, found;
2141
2142 found = 0;
2143 address = possible_addresses;
2144
2145 while (address->cfg_base) {
2146 cfg_base = address->cfg_base;
2147
2148 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2149
2150 if (address->type & SMSCSIO_TYPE_FDC) {
2151 type = "FDC";
2152 if (address->type & SMSCSIO_TYPE_FLAT)
2153 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2154 found++;
2155
2156 if (address->type & SMSCSIO_TYPE_PAGED)
2157 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2158 found++;
2159 }
2160 if (address->type & SMSCSIO_TYPE_LPC) {
2161 type = "LPC";
2162 if (address->type & SMSCSIO_TYPE_FLAT)
2163 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2164 found++;
2165
2166 if (address->type & SMSCSIO_TYPE_PAGED)
2167 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2168 found++;
2169 }
2170 address++;
2171 }
2172 return found;
2173 }
2174
2175 /*
2176 * Function smsc_superio_flat (chip, base, type)
2177 *
2178 * Try to get configuration of a smc SuperIO chip with flat register model
2179 *
2180 */
2181 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2182 {
2183 unsigned short firbase, sirbase;
2184 u8 mode, dma, irq;
2185 int ret = -ENODEV;
2186
2187 IRDA_DEBUG(1, "%s\n", __func__);
2188
2189 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2190 return ret;
2191
2192 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2193 mode = inb(cfgbase + 1);
2194
2195 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2196
2197 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2198 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
2199
2200 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2201 sirbase = inb(cfgbase + 1) << 2;
2202
2203 /* FIR iobase */
2204 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2205 firbase = inb(cfgbase + 1) << 3;
2206
2207 /* DMA */
2208 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2209 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2210
2211 /* IRQ */
2212 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2213 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2214
2215 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
2216
2217 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2218 ret = 0;
2219
2220 /* Exit configuration */
2221 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2222
2223 return ret;
2224 }
2225
2226 /*
2227 * Function smsc_superio_paged (chip, base, type)
2228 *
2229 * Try to get configuration of a smc SuperIO chip with paged register model
2230 *
2231 */
2232 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2233 {
2234 unsigned short fir_io, sir_io;
2235 int ret = -ENODEV;
2236
2237 IRDA_DEBUG(1, "%s\n", __func__);
2238
2239 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2240 return ret;
2241
2242 /* Select logical device (UART2) */
2243 outb(0x07, cfg_base);
2244 outb(0x05, cfg_base + 1);
2245
2246 /* SIR iobase */
2247 outb(0x60, cfg_base);
2248 sir_io = inb(cfg_base + 1) << 8;
2249 outb(0x61, cfg_base);
2250 sir_io |= inb(cfg_base + 1);
2251
2252 /* Read FIR base */
2253 outb(0x62, cfg_base);
2254 fir_io = inb(cfg_base + 1) << 8;
2255 outb(0x63, cfg_base);
2256 fir_io |= inb(cfg_base + 1);
2257 outb(0x2b, cfg_base); /* ??? */
2258
2259 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2260 ret = 0;
2261
2262 /* Exit configuration */
2263 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2264
2265 return ret;
2266 }
2267
2268
2269 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2270 {
2271 IRDA_DEBUG(1, "%s\n", __func__);
2272
2273 outb(reg, cfg_base);
2274 return inb(cfg_base) != reg ? -1 : 0;
2275 }
2276
2277 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2278 {
2279 u8 devid, xdevid, rev;
2280
2281 IRDA_DEBUG(1, "%s\n", __func__);
2282
2283 /* Leave configuration */
2284
2285 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2286
2287 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2288 return NULL;
2289
2290 outb(reg, cfg_base);
2291
2292 xdevid = inb(cfg_base + 1);
2293
2294 /* Enter configuration */
2295
2296 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2297
2298 #if 0
2299 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2300 return NULL;
2301 #endif
2302
2303 /* probe device ID */
2304
2305 if (smsc_access(cfg_base, reg))
2306 return NULL;
2307
2308 devid = inb(cfg_base + 1);
2309
2310 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2311 return NULL;
2312
2313 /* probe revision ID */
2314
2315 if (smsc_access(cfg_base, reg + 1))
2316 return NULL;
2317
2318 rev = inb(cfg_base + 1);
2319
2320 if (rev >= 128) /* i think this will make no sense */
2321 return NULL;
2322
2323 if (devid == xdevid) /* protection against false positives */
2324 return NULL;
2325
2326 /* Check for expected device ID; are there others? */
2327
2328 while (chip->devid != devid) {
2329
2330 chip++;
2331
2332 if (chip->name == NULL)
2333 return NULL;
2334 }
2335
2336 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2337 devid, rev, cfg_base, type, chip->name);
2338
2339 if (chip->rev > rev) {
2340 IRDA_MESSAGE("Revision higher than expected\n");
2341 return NULL;
2342 }
2343
2344 if (chip->flags & NoIRDA)
2345 IRDA_MESSAGE("chipset does not support IRDA\n");
2346
2347 return chip;
2348 }
2349
2350 static int __init smsc_superio_fdc(unsigned short cfg_base)
2351 {
2352 int ret = -1;
2353
2354 if (!request_region(cfg_base, 2, driver_name)) {
2355 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2356 __func__, cfg_base);
2357 } else {
2358 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2359 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2360 ret = 0;
2361
2362 release_region(cfg_base, 2);
2363 }
2364
2365 return ret;
2366 }
2367
2368 static int __init smsc_superio_lpc(unsigned short cfg_base)
2369 {
2370 int ret = -1;
2371
2372 if (!request_region(cfg_base, 2, driver_name)) {
2373 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2374 __func__, cfg_base);
2375 } else {
2376 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2377 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2378 ret = 0;
2379
2380 release_region(cfg_base, 2);
2381 }
2382 return ret;
2383 }
2384
2385 /*
2386 * Look for some specific subsystem setups that need
2387 * pre-configuration not properly done by the BIOS (especially laptops)
2388 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2389 * and tosh2450-smcinit.c. The table lists the device entries
2390 * for ISA bridges with an LPC (Low Pin Count) controller which
2391 * handles the communication with the SMSC device. After the LPC
2392 * controller is initialized through PCI, the SMSC device is initialized
2393 * through a dedicated port in the ISA port-mapped I/O area, this latter
2394 * area is used to configure the SMSC device with default
2395 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2396 * used different sets of parameters and different control port
2397 * addresses making a subsystem device table necessary.
2398 */
2399 #ifdef CONFIG_PCI
2400 #define PCIID_VENDOR_INTEL 0x8086
2401 #define PCIID_VENDOR_ALI 0x10b9
2402 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2403 /*
2404 * Subsystems needing entries:
2405 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2406 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2407 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2408 */
2409 {
2410 /* Guessed entry */
2411 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2412 .device = 0x24cc,
2413 .subvendor = 0x103c,
2414 .subdevice = 0x08bc,
2415 .sir_io = 0x02f8,
2416 .fir_io = 0x0130,
2417 .fir_irq = 0x05,
2418 .fir_dma = 0x03,
2419 .cfg_base = 0x004e,
2420 .preconfigure = preconfigure_through_82801,
2421 .name = "HP nx5000 family",
2422 },
2423 {
2424 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2425 .device = 0x24cc,
2426 .subvendor = 0x103c,
2427 .subdevice = 0x088c,
2428 /* Quite certain these are the same for nc8000 as for nc6000 */
2429 .sir_io = 0x02f8,
2430 .fir_io = 0x0130,
2431 .fir_irq = 0x05,
2432 .fir_dma = 0x03,
2433 .cfg_base = 0x004e,
2434 .preconfigure = preconfigure_through_82801,
2435 .name = "HP nc8000 family",
2436 },
2437 {
2438 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2439 .device = 0x24cc,
2440 .subvendor = 0x103c,
2441 .subdevice = 0x0890,
2442 .sir_io = 0x02f8,
2443 .fir_io = 0x0130,
2444 .fir_irq = 0x05,
2445 .fir_dma = 0x03,
2446 .cfg_base = 0x004e,
2447 .preconfigure = preconfigure_through_82801,
2448 .name = "HP nc6000 family",
2449 },
2450 {
2451 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2452 .device = 0x24cc,
2453 .subvendor = 0x0e11,
2454 .subdevice = 0x0860,
2455 /* I assume these are the same for x1000 as for the others */
2456 .sir_io = 0x02e8,
2457 .fir_io = 0x02f8,
2458 .fir_irq = 0x07,
2459 .fir_dma = 0x03,
2460 .cfg_base = 0x002e,
2461 .preconfigure = preconfigure_through_82801,
2462 .name = "Compaq x1000 family",
2463 },
2464 {
2465 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2466 .vendor = PCIID_VENDOR_INTEL,
2467 .device = 0x24c0,
2468 .subvendor = 0x1179,
2469 .subdevice = 0xffff, /* 0xffff is "any" */
2470 .sir_io = 0x03f8,
2471 .fir_io = 0x0130,
2472 .fir_irq = 0x07,
2473 .fir_dma = 0x01,
2474 .cfg_base = 0x002e,
2475 .preconfigure = preconfigure_through_82801,
2476 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2477 },
2478 {
2479 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2480 .device = 0x248c,
2481 .subvendor = 0x1179,
2482 .subdevice = 0xffff, /* 0xffff is "any" */
2483 .sir_io = 0x03f8,
2484 .fir_io = 0x0130,
2485 .fir_irq = 0x03,
2486 .fir_dma = 0x03,
2487 .cfg_base = 0x002e,
2488 .preconfigure = preconfigure_through_82801,
2489 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2490 },
2491 {
2492 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2493 .vendor = PCIID_VENDOR_INTEL,
2494 .device = 0x24cc,
2495 .subvendor = 0x1179,
2496 .subdevice = 0xffff, /* 0xffff is "any" */
2497 .sir_io = 0x03f8,
2498 .fir_io = 0x0130,
2499 .fir_irq = 0x03,
2500 .fir_dma = 0x03,
2501 .cfg_base = 0x002e,
2502 .preconfigure = preconfigure_through_82801,
2503 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2504 },
2505 {
2506 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2507 .vendor = PCIID_VENDOR_ALI,
2508 .device = 0x1533,
2509 .subvendor = 0x1179,
2510 .subdevice = 0xffff, /* 0xffff is "any" */
2511 .sir_io = 0x02e8,
2512 .fir_io = 0x02f8,
2513 .fir_irq = 0x07,
2514 .fir_dma = 0x03,
2515 .cfg_base = 0x002e,
2516 .preconfigure = preconfigure_through_ali,
2517 .name = "Toshiba laptop with ALi ISA bridge",
2518 },
2519 { } // Terminator
2520 };
2521
2522
2523 /*
2524 * This sets up the basic SMSC parameters
2525 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2526 * through the chip configuration port.
2527 */
2528 static int __init preconfigure_smsc_chip(struct
2529 smsc_ircc_subsystem_configuration
2530 *conf)
2531 {
2532 unsigned short iobase = conf->cfg_base;
2533 unsigned char tmpbyte;
2534
2535 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2536 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2537 tmpbyte = inb(iobase +1); // Read device ID
2538 IRDA_DEBUG(0,
2539 "Detected Chip id: 0x%02x, setting up registers...\n",
2540 tmpbyte);
2541
2542 /* Disable UART1 and set up SIR I/O port */
2543 outb(0x24, iobase); // select CR24 - UART1 base addr
2544 outb(0x00, iobase + 1); // disable UART1
2545 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2546 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2547 tmpbyte = inb(iobase + 1);
2548 if (tmpbyte != (conf->sir_io >> 2) ) {
2549 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2550 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2551 return -ENXIO;
2552 }
2553
2554 /* Set up FIR IRQ channel for UART2 */
2555 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2556 tmpbyte = inb(iobase + 1);
2557 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2558 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2559 outb(tmpbyte, iobase + 1);
2560 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2561 if (tmpbyte != conf->fir_irq) {
2562 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2563 return -ENXIO;
2564 }
2565
2566 /* Set up FIR I/O port */
2567 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2568 outb((conf->fir_io >> 3), iobase + 1);
2569 tmpbyte = inb(iobase + 1);
2570 if (tmpbyte != (conf->fir_io >> 3) ) {
2571 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2572 return -ENXIO;
2573 }
2574
2575 /* Set up FIR DMA channel */
2576 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2577 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2578 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2579 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2580 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2581 return -ENXIO;
2582 }
2583
2584 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2585 tmpbyte = inb(iobase + 1);
2586 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2587 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2588 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2589
2590 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2591 tmpbyte = inb(iobase + 1);
2592 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2593
2594 /* This one was not part of tosh1800 */
2595 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2596 tmpbyte = inb(iobase + 1);
2597 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2598
2599 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2600 tmpbyte = inb(iobase + 1);
2601 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2602
2603 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2604 tmpbyte = inb(iobase + 1);
2605 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2606
2607 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2608
2609 return 0;
2610 }
2611
2612 /* 82801CAM generic registers */
2613 #define VID 0x00
2614 #define DID 0x02
2615 #define PIRQ_A_D_ROUT 0x60
2616 #define SIRQ_CNTL 0x64
2617 #define PIRQ_E_H_ROUT 0x68
2618 #define PCI_DMA_C 0x90
2619 /* LPC-specific registers */
2620 #define COM_DEC 0xe0
2621 #define GEN1_DEC 0xe4
2622 #define LPC_EN 0xe6
2623 #define GEN2_DEC 0xec
2624 /*
2625 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2626 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2627 * They all work the same way!
2628 */
2629 static int __init preconfigure_through_82801(struct pci_dev *dev,
2630 struct
2631 smsc_ircc_subsystem_configuration
2632 *conf)
2633 {
2634 unsigned short tmpword;
2635 unsigned char tmpbyte;
2636
2637 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2638 /*
2639 * Select the range for the COMA COM port (SIR)
2640 * Register COM_DEC:
2641 * Bit 7: reserved
2642 * Bit 6-4, COMB decode range
2643 * Bit 3: reserved
2644 * Bit 2-0, COMA decode range
2645 *
2646 * Decode ranges:
2647 * 000 = 0x3f8-0x3ff (COM1)
2648 * 001 = 0x2f8-0x2ff (COM2)
2649 * 010 = 0x220-0x227
2650 * 011 = 0x228-0x22f
2651 * 100 = 0x238-0x23f
2652 * 101 = 0x2e8-0x2ef (COM4)
2653 * 110 = 0x338-0x33f
2654 * 111 = 0x3e8-0x3ef (COM3)
2655 */
2656 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2657 tmpbyte &= 0xf8; /* mask COMA bits */
2658 switch(conf->sir_io) {
2659 case 0x3f8:
2660 tmpbyte |= 0x00;
2661 break;
2662 case 0x2f8:
2663 tmpbyte |= 0x01;
2664 break;
2665 case 0x220:
2666 tmpbyte |= 0x02;
2667 break;
2668 case 0x228:
2669 tmpbyte |= 0x03;
2670 break;
2671 case 0x238:
2672 tmpbyte |= 0x04;
2673 break;
2674 case 0x2e8:
2675 tmpbyte |= 0x05;
2676 break;
2677 case 0x338:
2678 tmpbyte |= 0x06;
2679 break;
2680 case 0x3e8:
2681 tmpbyte |= 0x07;
2682 break;
2683 default:
2684 tmpbyte |= 0x01; /* COM2 default */
2685 }
2686 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2687 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2688
2689 /* Enable Low Pin Count interface */
2690 pci_read_config_word(dev, LPC_EN, &tmpword);
2691 /* These seem to be set up at all times,
2692 * just make sure it is properly set.
2693 */
2694 switch(conf->cfg_base) {
2695 case 0x04e:
2696 tmpword |= 0x2000;
2697 break;
2698 case 0x02e:
2699 tmpword |= 0x1000;
2700 break;
2701 case 0x062:
2702 tmpword |= 0x0800;
2703 break;
2704 case 0x060:
2705 tmpword |= 0x0400;
2706 break;
2707 default:
2708 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2709 conf->cfg_base);
2710 break;
2711 }
2712 tmpword &= 0xfffd; /* disable LPC COMB */
2713 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2714 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2715 pci_write_config_word(dev, LPC_EN, tmpword);
2716
2717 /*
2718 * Configure LPC DMA channel
2719 * PCI_DMA_C bits:
2720 * Bit 15-14: DMA channel 7 select
2721 * Bit 13-12: DMA channel 6 select
2722 * Bit 11-10: DMA channel 5 select
2723 * Bit 9-8: Reserved
2724 * Bit 7-6: DMA channel 3 select
2725 * Bit 5-4: DMA channel 2 select
2726 * Bit 3-2: DMA channel 1 select
2727 * Bit 1-0: DMA channel 0 select
2728 * 00 = Reserved value
2729 * 01 = PC/PCI DMA
2730 * 10 = Reserved value
2731 * 11 = LPC I/F DMA
2732 */
2733 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2734 switch(conf->fir_dma) {
2735 case 0x07:
2736 tmpword |= 0xc000;
2737 break;
2738 case 0x06:
2739 tmpword |= 0x3000;
2740 break;
2741 case 0x05:
2742 tmpword |= 0x0c00;
2743 break;
2744 case 0x03:
2745 tmpword |= 0x00c0;
2746 break;
2747 case 0x02:
2748 tmpword |= 0x0030;
2749 break;
2750 case 0x01:
2751 tmpword |= 0x000c;
2752 break;
2753 case 0x00:
2754 tmpword |= 0x0003;
2755 break;
2756 default:
2757 break; /* do not change settings */
2758 }
2759 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2760 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2761
2762 /*
2763 * GEN2_DEC bits:
2764 * Bit 15-4: Generic I/O range
2765 * Bit 3-1: reserved (read as 0)
2766 * Bit 0: enable GEN2 range on LPC I/F
2767 */
2768 tmpword = conf->fir_io & 0xfff8;
2769 tmpword |= 0x0001;
2770 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2771 pci_write_config_word(dev, GEN2_DEC, tmpword);
2772
2773 /* Pre-configure chip */
2774 return preconfigure_smsc_chip(conf);
2775 }
2776
2777 /*
2778 * Pre-configure a certain port on the ALi 1533 bridge.
2779 * This is based on reverse-engineering since ALi does not
2780 * provide any data sheet for the 1533 chip.
2781 */
2782 static void __init preconfigure_ali_port(struct pci_dev *dev,
2783 unsigned short port)
2784 {
2785 unsigned char reg;
2786 /* These bits obviously control the different ports */
2787 unsigned char mask;
2788 unsigned char tmpbyte;
2789
2790 switch(port) {
2791 case 0x0130:
2792 case 0x0178:
2793 reg = 0xb0;
2794 mask = 0x80;
2795 break;
2796 case 0x03f8:
2797 reg = 0xb4;
2798 mask = 0x80;
2799 break;
2800 case 0x02f8:
2801 reg = 0xb4;
2802 mask = 0x30;
2803 break;
2804 case 0x02e8:
2805 reg = 0xb4;
2806 mask = 0x08;
2807 break;
2808 default:
2809 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2810 return;
2811 }
2812
2813 pci_read_config_byte(dev, reg, &tmpbyte);
2814 /* Turn on the right bits */
2815 tmpbyte |= mask;
2816 pci_write_config_byte(dev, reg, tmpbyte);
2817 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2818 return;
2819 }
2820
2821 static int __init preconfigure_through_ali(struct pci_dev *dev,
2822 struct
2823 smsc_ircc_subsystem_configuration
2824 *conf)
2825 {
2826 /* Configure the two ports on the ALi 1533 */
2827 preconfigure_ali_port(dev, conf->sir_io);
2828 preconfigure_ali_port(dev, conf->fir_io);
2829
2830 /* Pre-configure chip */
2831 return preconfigure_smsc_chip(conf);
2832 }
2833
2834 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2835 unsigned short ircc_fir,
2836 unsigned short ircc_sir,
2837 unsigned char ircc_dma,
2838 unsigned char ircc_irq)
2839 {
2840 struct pci_dev *dev = NULL;
2841 unsigned short ss_vendor = 0x0000;
2842 unsigned short ss_device = 0x0000;
2843 int ret = 0;
2844
2845 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2846
2847 while (dev != NULL) {
2848 struct smsc_ircc_subsystem_configuration *conf;
2849
2850 /*
2851 * Cache the subsystem vendor/device:
2852 * some manufacturers fail to set this for all components,
2853 * so we save it in case there is just 0x0000 0x0000 on the
2854 * device we want to check.
2855 */
2856 if (dev->subsystem_vendor != 0x0000U) {
2857 ss_vendor = dev->subsystem_vendor;
2858 ss_device = dev->subsystem_device;
2859 }
2860 conf = subsystem_configurations;
2861 for( ; conf->subvendor; conf++) {
2862 if(conf->vendor == dev->vendor &&
2863 conf->device == dev->device &&
2864 conf->subvendor == ss_vendor &&
2865 /* Sometimes these are cached values */
2866 (conf->subdevice == ss_device ||
2867 conf->subdevice == 0xffff)) {
2868 struct smsc_ircc_subsystem_configuration
2869 tmpconf;
2870
2871 memcpy(&tmpconf, conf,
2872 sizeof(struct smsc_ircc_subsystem_configuration));
2873
2874 /*
2875 * Override the default values with anything
2876 * passed in as parameter
2877 */
2878 if (ircc_cfg != 0)
2879 tmpconf.cfg_base = ircc_cfg;
2880 if (ircc_fir != 0)
2881 tmpconf.fir_io = ircc_fir;
2882 if (ircc_sir != 0)
2883 tmpconf.sir_io = ircc_sir;
2884 if (ircc_dma != DMA_INVAL)
2885 tmpconf.fir_dma = ircc_dma;
2886 if (ircc_irq != IRQ_INVAL)
2887 tmpconf.fir_irq = ircc_irq;
2888
2889 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2890 if (conf->preconfigure)
2891 ret = conf->preconfigure(dev, &tmpconf);
2892 else
2893 ret = -ENODEV;
2894 }
2895 }
2896 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2897 }
2898
2899 return ret;
2900 }
2901 #endif // CONFIG_PCI
2902
2903 /************************************************
2904 *
2905 * Transceivers specific functions
2906 *
2907 ************************************************/
2908
2909
2910 /*
2911 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2912 *
2913 * Program transceiver through smsc-ircc ATC circuitry
2914 *
2915 */
2916
2917 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2918 {
2919 unsigned long jiffies_now, jiffies_timeout;
2920 u8 val;
2921
2922 jiffies_now = jiffies;
2923 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2924
2925 /* ATC */
2926 register_bank(fir_base, 4);
2927 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2928 fir_base + IRCC_ATC);
2929
2930 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2931 !time_after(jiffies, jiffies_timeout))
2932 /* empty */;
2933
2934 if (val)
2935 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2936 inb(fir_base + IRCC_ATC));
2937 }
2938
2939 /*
2940 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2941 *
2942 * Probe transceiver smsc-ircc ATC circuitry
2943 *
2944 */
2945
2946 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2947 {
2948 return 0;
2949 }
2950
2951 /*
2952 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2953 *
2954 * Set transceiver
2955 *
2956 */
2957
2958 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2959 {
2960 u8 fast_mode;
2961
2962 switch (speed) {
2963 default:
2964 case 576000 :
2965 fast_mode = 0;
2966 break;
2967 case 1152000 :
2968 case 4000000 :
2969 fast_mode = IRCC_LCR_A_FAST;
2970 break;
2971 }
2972 register_bank(fir_base, 0);
2973 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2974 }
2975
2976 /*
2977 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2978 *
2979 * Probe transceiver
2980 *
2981 */
2982
2983 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2984 {
2985 return 0;
2986 }
2987
2988 /*
2989 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2990 *
2991 * Set transceiver
2992 *
2993 */
2994
2995 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2996 {
2997 u8 fast_mode;
2998
2999 switch (speed) {
3000 default:
3001 case 576000 :
3002 fast_mode = 0;
3003 break;
3004 case 1152000 :
3005 case 4000000 :
3006 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3007 break;
3008
3009 }
3010 /* This causes an interrupt */
3011 register_bank(fir_base, 0);
3012 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3013 }
3014
3015 /*
3016 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3017 *
3018 * Probe transceiver
3019 *
3020 */
3021
3022 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3023 {
3024 return 0;
3025 }
3026
3027
3028 module_init(smsc_ircc_init);
3029 module_exit(smsc_ircc_cleanup);
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