2 * Blackfin CPLB initialization
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Bugs: Enter bugs at http://blackfin.uclinux.org/
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, see the file COPYING, or write
20 * to the Free Software Foundation, Inc.,
21 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/module.h>
26 #include <asm/blackfin.h>
27 #include <asm/cacheflush.h>
29 #include <asm/cplbinit.h>
31 u_long icplb_tables
[NR_CPUS
][CPLB_TBL_ENTRIES
+1];
32 u_long dcplb_tables
[NR_CPUS
][CPLB_TBL_ENTRIES
+1];
34 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
35 #define PDT_ATTR __attribute__((l1_data))
40 u_long ipdt_tables
[NR_CPUS
][MAX_SWITCH_I_CPLBS
+1] PDT_ATTR
;
41 u_long dpdt_tables
[NR_CPUS
][MAX_SWITCH_D_CPLBS
+1] PDT_ATTR
;
42 #ifdef CONFIG_CPLB_INFO
43 u_long ipdt_swapcount_tables
[NR_CPUS
][MAX_SWITCH_I_CPLBS
] PDT_ATTR
;
44 u_long dpdt_swapcount_tables
[NR_CPUS
][MAX_SWITCH_D_CPLBS
] PDT_ATTR
;
48 struct cplb_tab init_i
;
49 struct cplb_tab init_d
;
50 struct cplb_tab switch_i
;
51 struct cplb_tab switch_d
;
54 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
55 static struct cplb_desc cplb_data
[] = {
60 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
| D_CPLB
,
63 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
68 .name
= "Zero Pointer Guard Page",
71 .start
= 0, /* dyanmic */
72 .end
= 0, /* dynamic */
74 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
,
78 .name
= "L1 I-Memory",
81 .start
= 0, /* dynamic */
82 .end
= 0, /* dynamic */
84 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
87 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
92 .name
= "L1 D-Memory",
96 .end
= L2_START
+ L2_LENGTH
,
100 .d_conf
= L2_DMEMORY
,
101 .valid
= (L2_LENGTH
> 0),
106 .end
= 0, /* dynamic */
108 .attr
= INITIAL_T
| SWITCH_T
| I_CPLB
| D_CPLB
,
109 .i_conf
= SDRAM_IGENERIC
,
110 .d_conf
= SDRAM_DGENERIC
,
112 .name
= "Kernel Memory",
115 .start
= 0, /* dynamic */
116 .end
= 0, /* dynamic */
118 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
119 .i_conf
= SDRAM_IGENERIC
,
120 .d_conf
= SDRAM_DNON_CHBL
,
122 .name
= "uClinux MTD Memory",
125 .start
= 0, /* dynamic */
126 .end
= 0, /* dynamic */
128 .attr
= INITIAL_T
| SWITCH_T
| D_CPLB
,
129 .d_conf
= SDRAM_DNON_CHBL
,
131 .name
= "Uncached DMA Zone",
134 .start
= 0, /* dynamic */
135 .end
= 0, /* dynamic */
137 .attr
= SWITCH_T
| D_CPLB
,
138 .i_conf
= 0, /* dynamic */
139 .d_conf
= 0, /* dynamic */
141 .name
= "Reserved Memory",
144 .start
= ASYNC_BANK0_BASE
,
145 .end
= ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
,
147 .attr
= SWITCH_T
| D_CPLB
,
148 .d_conf
= SDRAM_EBIU
,
150 .name
= "Asynchronous Memory Banks",
153 .start
= BOOT_ROM_START
,
154 .end
= BOOT_ROM_START
+ BOOT_ROM_LENGTH
,
156 .attr
= SWITCH_T
| I_CPLB
| D_CPLB
,
157 .i_conf
= SDRAM_IGENERIC
,
158 .d_conf
= SDRAM_DGENERIC
,
160 .name
= "On-Chip BootROM",
164 static bool __init
lock_kernel_check(u32 start
, u32 end
)
166 if (start
>= (u32
)__init_begin
|| end
<= (u32
)_stext
)
169 /* This cplb block overlapped with kernel area. */
174 fill_cplbtab(struct cplb_tab
*table
,
175 unsigned long start
, unsigned long end
,
176 unsigned long block_size
, unsigned long cplb_data
)
180 switch (block_size
) {
196 cplb_data
= (cplb_data
& ~(3 << 16)) | (i
<< 16);
198 while ((start
< end
) && (table
->pos
< table
->size
)) {
200 table
->tab
[table
->pos
++] = start
;
202 if (lock_kernel_check(start
, start
+ block_size
))
203 table
->tab
[table
->pos
++] =
204 cplb_data
| CPLB_LOCK
| CPLB_DIRTY
;
206 table
->tab
[table
->pos
++] = cplb_data
;
212 static void __init
close_cplbtab(struct cplb_tab
*table
)
214 while (table
->pos
< table
->size
)
215 table
->tab
[table
->pos
++] = 0;
218 /* helper function */
220 __fill_code_cplbtab(struct cplb_tab
*t
, int i
, u32 a_start
, u32 a_end
)
222 if (cplb_data
[i
].psize
) {
227 cplb_data
[i
].i_conf
);
229 #if defined(CONFIG_BFIN_ICACHE)
230 if (ANOMALY_05000263
&& i
== SDRAM_KERN
) {
235 cplb_data
[i
].i_conf
);
243 cplb_data
[i
].i_conf
);
248 cplb_data
[i
].i_conf
);
249 fill_cplbtab(t
, a_end
,
252 cplb_data
[i
].i_conf
);
258 __fill_data_cplbtab(struct cplb_tab
*t
, int i
, u32 a_start
, u32 a_end
)
260 if (cplb_data
[i
].psize
) {
265 cplb_data
[i
].d_conf
);
270 cplb_data
[i
].d_conf
);
271 fill_cplbtab(t
, a_start
,
273 cplb_data
[i
].d_conf
);
274 fill_cplbtab(t
, a_end
,
277 cplb_data
[i
].d_conf
);
281 void __init
generate_cplb_tables_cpu(unsigned int cpu
)
285 u32 a_start
, a_end
, as
, ae
, as_1m
;
287 struct cplb_tab
*t_i
= NULL
;
288 struct cplb_tab
*t_d
= NULL
;
291 printk(KERN_INFO
"NOMPU: setting up cplb tables for global access\n");
293 cplb
.init_i
.size
= CPLB_TBL_ENTRIES
;
294 cplb
.init_d
.size
= CPLB_TBL_ENTRIES
;
295 cplb
.switch_i
.size
= MAX_SWITCH_I_CPLBS
;
296 cplb
.switch_d
.size
= MAX_SWITCH_D_CPLBS
;
300 cplb
.switch_i
.pos
= 0;
301 cplb
.switch_d
.pos
= 0;
303 cplb
.init_i
.tab
= icplb_tables
[cpu
];
304 cplb
.init_d
.tab
= dcplb_tables
[cpu
];
305 cplb
.switch_i
.tab
= ipdt_tables
[cpu
];
306 cplb
.switch_d
.tab
= dpdt_tables
[cpu
];
308 cplb_data
[L1I_MEM
].start
= get_l1_code_start_cpu(cpu
);
309 cplb_data
[L1I_MEM
].end
= cplb_data
[L1I_MEM
].start
+ L1_CODE_LENGTH
;
310 cplb_data
[L1D_MEM
].start
= get_l1_data_a_start_cpu(cpu
);
311 cplb_data
[L1D_MEM
].end
= get_l1_data_b_start_cpu(cpu
) + L1_DATA_B_LENGTH
;
312 cplb_data
[SDRAM_KERN
].end
= memory_end
;
314 #ifdef CONFIG_MTD_UCLINUX
315 cplb_data
[SDRAM_RAM_MTD
].start
= memory_mtd_start
;
316 cplb_data
[SDRAM_RAM_MTD
].end
= memory_mtd_start
+ mtd_size
;
317 cplb_data
[SDRAM_RAM_MTD
].valid
= mtd_size
> 0;
318 # if defined(CONFIG_ROMFS_FS)
319 cplb_data
[SDRAM_RAM_MTD
].attr
|= I_CPLB
;
322 * The ROMFS_FS size is often not multiple of 1MB.
323 * This can cause multiple CPLB sets covering the same memory area.
324 * This will then cause multiple CPLB hit exceptions.
325 * Workaround: We ensure a contiguous memory area by extending the kernel
326 * memory section over the mtd section.
327 * For ROMFS_FS memory must be covered with ICPLBs anyways.
328 * So there is no difference between kernel and mtd memory setup.
331 cplb_data
[SDRAM_KERN
].end
= memory_mtd_start
+ mtd_size
;;
332 cplb_data
[SDRAM_RAM_MTD
].valid
= 0;
336 cplb_data
[SDRAM_RAM_MTD
].valid
= 0;
339 cplb_data
[SDRAM_DMAZ
].start
= _ramend
- DMA_UNCACHED_REGION
;
340 cplb_data
[SDRAM_DMAZ
].end
= _ramend
;
342 cplb_data
[RES_MEM
].start
= _ramend
;
343 cplb_data
[RES_MEM
].end
= physical_mem_end
;
345 if (reserved_mem_dcache_on
)
346 cplb_data
[RES_MEM
].d_conf
= SDRAM_DGENERIC
;
348 cplb_data
[RES_MEM
].d_conf
= SDRAM_DNON_CHBL
;
350 if (reserved_mem_icache_on
)
351 cplb_data
[RES_MEM
].i_conf
= SDRAM_IGENERIC
;
353 cplb_data
[RES_MEM
].i_conf
= SDRAM_INON_CHBL
;
355 for (i
= ZERO_P
; i
< ARRAY_SIZE(cplb_data
); ++i
) {
356 if (!cplb_data
[i
].valid
)
359 as_1m
= cplb_data
[i
].start
% SIZE_1M
;
361 /* We need to make sure all sections are properly 1M aligned
362 * However between Kernel Memory and the Kernel mtd section, depending on the
363 * rootfs size, there can be overlapping memory areas.
366 if (as_1m
&& i
!= L1I_MEM
&& i
!= L1D_MEM
) {
367 #ifdef CONFIG_MTD_UCLINUX
368 if (i
== SDRAM_RAM_MTD
) {
369 if ((cplb_data
[SDRAM_KERN
].end
+ 1) > cplb_data
[SDRAM_RAM_MTD
].start
)
370 cplb_data
[SDRAM_RAM_MTD
].start
= (cplb_data
[i
].start
& (-2*SIZE_1M
)) + SIZE_1M
;
372 cplb_data
[SDRAM_RAM_MTD
].start
= (cplb_data
[i
].start
& (-2*SIZE_1M
));
375 printk(KERN_WARNING
"Unaligned Start of %s at 0x%X\n",
376 cplb_data
[i
].name
, cplb_data
[i
].start
);
379 as
= cplb_data
[i
].start
% SIZE_4M
;
380 ae
= cplb_data
[i
].end
% SIZE_4M
;
383 a_start
= cplb_data
[i
].start
+ (SIZE_4M
- (as
));
385 a_start
= cplb_data
[i
].start
;
387 a_end
= cplb_data
[i
].end
- ae
;
389 for (j
= INITIAL_T
; j
<= SWITCH_T
; j
++) {
393 if (cplb_data
[i
].attr
& INITIAL_T
) {
401 if (cplb_data
[i
].attr
& SWITCH_T
) {
402 t_i
= &cplb
.switch_i
;
403 t_d
= &cplb
.switch_d
;
415 if (cplb_data
[i
].attr
& I_CPLB
)
416 __fill_code_cplbtab(t_i
, i
, a_start
, a_end
);
418 if (cplb_data
[i
].attr
& D_CPLB
)
419 __fill_data_cplbtab(t_d
, i
, a_start
, a_end
);
423 /* make sure we locked the kernel start */
424 BUG_ON(cplb
.init_i
.pos
< 2 + cplb_data
[ZERO_P
].valid
);
425 BUG_ON(cplb
.init_d
.pos
< 1 + cplb_data
[ZERO_P
].valid
+ cplb_data
[L1D_MEM
].valid
);
427 /* make sure we didnt overflow the table */
428 BUG_ON(cplb
.init_i
.size
<= cplb
.init_i
.pos
);
429 BUG_ON(cplb
.init_d
.size
<= cplb
.init_d
.pos
);
430 BUG_ON(cplb
.switch_i
.size
<= cplb
.switch_i
.pos
);
431 BUG_ON(cplb
.switch_d
.size
<= cplb
.switch_d
.pos
);
434 close_cplbtab(&cplb
.init_i
);
435 close_cplbtab(&cplb
.init_d
);
437 cplb
.init_i
.tab
[cplb
.init_i
.pos
] = -1;
438 cplb
.init_d
.tab
[cplb
.init_d
.pos
] = -1;
439 cplb
.switch_i
.tab
[cplb
.switch_i
.pos
] = -1;
440 cplb
.switch_d
.tab
[cplb
.switch_d
.pos
] = -1;