include/asm-ia64/io.h

   1 #ifndef _ASM_IA64_IO_H
   2 #define _ASM_IA64_IO_H
   3
   4 /*
   5  * This file contains the definitions for the emulated IO instructions
   6  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
   7  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
   8  * versions of the single-IO instructions (inb_p/inw_p/..).
   9  *
  10  * This file is not meant to be obfuscating: it's just complicated to
  11  * (a) handle it all in a way that makes gcc able to optimize it as
  12  * well as possible and (b) trying to avoid writing the same thing
  13  * over and over again with slight variations and possibly making a
  14  * mistake somewhere.
  15  *
  16  * Copyright (C) 1998-2003 Hewlett-Packard Co
  17  *      David Mosberger-Tang <davidm@hpl.hp.com>
  18  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
  19  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  20  */
  21
  22 /* We don't use IO slowdowns on the ia64, but.. */
  23 #define __SLOW_DOWN_IO  do { } while (0)
  24 #define SLOW_DOWN_IO    do { } while (0)
  25
  26 #define __IA64_UNCACHED_OFFSET  RGN_BASE(RGN_UNCACHED)
  27
  28 /*
  29  * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
  30  * large machines may have multiple other I/O spaces so we can't place any a priori limit
  31  * on IO_SPACE_LIMIT.  These additional spaces are described in ACPI.
  32  */
  33 #define IO_SPACE_LIMIT          0xffffffffffffffffUL
  34
  35 #define MAX_IO_SPACES_BITS              4
  36 #define MAX_IO_SPACES                   (1UL << MAX_IO_SPACES_BITS)
  37 #define IO_SPACE_BITS                   24
  38 #define IO_SPACE_SIZE                   (1UL << IO_SPACE_BITS)
  39
  40 #define IO_SPACE_NR(port)               ((port) >> IO_SPACE_BITS)
  41 #define IO_SPACE_BASE(space)            ((space) << IO_SPACE_BITS)
  42 #define IO_SPACE_PORT(port)             ((port) & (IO_SPACE_SIZE - 1))
  43
  44 #define IO_SPACE_SPARSE_ENCODING(p)     ((((p) >> 2) << 12) | ((p) & 0xfff))
  45
  46 struct io_space {
  47         unsigned long mmio_base;        /* base in MMIO space */
  48         int sparse;
  49 };
  50
  51 extern struct io_space io_space[];
  52 extern unsigned int num_io_spaces;
  53
  54 # ifdef __KERNEL__
  55
  56 /*
  57  * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
  58  *      0xCxxxxxxxxxxxxxxx      MMIO cookie (return from ioremap)
  59  *      0x000000001SPPPPPP      PIO cookie (S=space number, P..P=port)
  60  *
  61  * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
  62  * code that uses bare port numbers without the prerequisite pci_iomap().
  63  */
  64 #define PIO_OFFSET              (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
  65 #define PIO_MASK                (PIO_OFFSET - 1)
  66 #define PIO_RESERVED            __IA64_UNCACHED_OFFSET
  67 #define HAVE_ARCH_PIO_SIZE
  68
  69 #include <asm/intrinsics.h>
  70 #include <asm/machvec.h>
  71 #include <asm/page.h>
  72 #include <asm/system.h>
  73 #include <asm-generic/iomap.h>
  74
  75 /*
  76  * Change virtual addresses to physical addresses and vv.
  77  */
  78 static inline unsigned long
  79 virt_to_phys (volatile void *address)
  80 {
  81         return (unsigned long) address - PAGE_OFFSET;
  82 }
  83
  84 static inline void*
  85 phys_to_virt (unsigned long address)
  86 {
  87         return (void *) (address + PAGE_OFFSET);
  88 }
  89
  90 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
  91 extern int valid_phys_addr_range (unsigned long addr, size_t count); /* efi.c */
  92 extern int valid_mmap_phys_addr_range (unsigned long addr, size_t count);
  93
  94 /*
  95  * The following two macros are deprecated and scheduled for removal.
  96  * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
  97  */
  98 #define bus_to_virt     phys_to_virt
  99 #define virt_to_bus     virt_to_phys
 100 #define page_to_bus     page_to_phys
 101
 102 # endif /* KERNEL */
 103
 104 /*
 105  * Memory fence w/accept.  This should never be used in code that is
 106  * not IA-64 specific.
 107  */
 108 #define __ia64_mf_a()   ia64_mfa()
 109
 110 /**
 111  * ___ia64_mmiowb - I/O write barrier
 112  *
 113  * Ensure ordering of I/O space writes.  This will make sure that writes
 114  * following the barrier will arrive after all previous writes.  For most
 115  * ia64 platforms, this is a simple 'mf.a' instruction.
 116  *
 117  * See Documentation/DocBook/deviceiobook.tmpl for more information.
 118  */
 119 static inline void ___ia64_mmiowb(void)
 120 {
 121         ia64_mfa();
 122 }
 123
 124 static inline void*
 125 __ia64_mk_io_addr (unsigned long port)
 126 {
 127         struct io_space *space;
 128         unsigned long offset;
 129
 130         space = &io_space[IO_SPACE_NR(port)];
 131         port = IO_SPACE_PORT(port);
 132         if (space->sparse)
 133                 offset = IO_SPACE_SPARSE_ENCODING(port);
 134         else
 135                 offset = port;
 136
 137         return (void *) (space->mmio_base | offset);
 138 }
 139
 140 #define __ia64_inb      ___ia64_inb
 141 #define __ia64_inw      ___ia64_inw
 142 #define __ia64_inl      ___ia64_inl
 143 #define __ia64_outb     ___ia64_outb
 144 #define __ia64_outw     ___ia64_outw
 145 #define __ia64_outl     ___ia64_outl
 146 #define __ia64_readb    ___ia64_readb
 147 #define __ia64_readw    ___ia64_readw
 148 #define __ia64_readl    ___ia64_readl
 149 #define __ia64_readq    ___ia64_readq
 150 #define __ia64_readb_relaxed    ___ia64_readb
 151 #define __ia64_readw_relaxed    ___ia64_readw
 152 #define __ia64_readl_relaxed    ___ia64_readl
 153 #define __ia64_readq_relaxed    ___ia64_readq
 154 #define __ia64_writeb   ___ia64_writeb
 155 #define __ia64_writew   ___ia64_writew
 156 #define __ia64_writel   ___ia64_writel
 157 #define __ia64_writeq   ___ia64_writeq
 158 #define __ia64_mmiowb   ___ia64_mmiowb
 159
 160 /*
 161  * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
 162  * that the access has completed before executing other I/O accesses.  Since we're doing
 163  * the accesses through an uncachable (UC) translation, the CPU will execute them in
 164  * program order.  However, we still need to tell the compiler not to shuffle them around
 165  * during optimization, which is why we use "volatile" pointers.
 166  */
 167
 168 static inline unsigned int
 169 ___ia64_inb (unsigned long port)
 170 {
 171         volatile unsigned char *addr = __ia64_mk_io_addr(port);
 172         unsigned char ret;
 173
 174         ret = *addr;
 175         __ia64_mf_a();
 176         return ret;
 177 }
 178
 179 static inline unsigned int
 180 ___ia64_inw (unsigned long port)
 181 {
 182         volatile unsigned short *addr = __ia64_mk_io_addr(port);
 183         unsigned short ret;
 184
 185         ret = *addr;
 186         __ia64_mf_a();
 187         return ret;
 188 }
 189
 190 static inline unsigned int
 191 ___ia64_inl (unsigned long port)
 192 {
 193         volatile unsigned int *addr = __ia64_mk_io_addr(port);
 194         unsigned int ret;
 195
 196         ret = *addr;
 197         __ia64_mf_a();
 198         return ret;
 199 }
 200
 201 static inline void
 202 ___ia64_outb (unsigned char val, unsigned long port)
 203 {
 204         volatile unsigned char *addr = __ia64_mk_io_addr(port);
 205
 206         *addr = val;
 207         __ia64_mf_a();
 208 }
 209
 210 static inline void
 211 ___ia64_outw (unsigned short val, unsigned long port)
 212 {
 213         volatile unsigned short *addr = __ia64_mk_io_addr(port);
 214
 215         *addr = val;
 216         __ia64_mf_a();
 217 }
 218
 219 static inline void
 220 ___ia64_outl (unsigned int val, unsigned long port)
 221 {
 222         volatile unsigned int *addr = __ia64_mk_io_addr(port);
 223
 224         *addr = val;
 225         __ia64_mf_a();
 226 }
 227
 228 static inline void
 229 __insb (unsigned long port, void *dst, unsigned long count)
 230 {
 231         unsigned char *dp = dst;
 232
 233         while (count--)
 234                 *dp++ = platform_inb(port);
 235 }
 236
 237 static inline void
 238 __insw (unsigned long port, void *dst, unsigned long count)
 239 {
 240         unsigned short *dp = dst;
 241
 242         while (count--)
 243                 *dp++ = platform_inw(port);
 244 }
 245
 246 static inline void
 247 __insl (unsigned long port, void *dst, unsigned long count)
 248 {
 249         unsigned int *dp = dst;
 250
 251         while (count--)
 252                 *dp++ = platform_inl(port);
 253 }
 254
 255 static inline void
 256 __outsb (unsigned long port, const void *src, unsigned long count)
 257 {
 258         const unsigned char *sp = src;
 259
 260         while (count--)
 261                 platform_outb(*sp++, port);
 262 }
 263
 264 static inline void
 265 __outsw (unsigned long port, const void *src, unsigned long count)
 266 {
 267         const unsigned short *sp = src;
 268
 269         while (count--)
 270                 platform_outw(*sp++, port);
 271 }
 272
 273 static inline void
 274 __outsl (unsigned long port, const void *src, unsigned long count)
 275 {
 276         const unsigned int *sp = src;
 277
 278         while (count--)
 279                 platform_outl(*sp++, port);
 280 }
 281
 282 /*
 283  * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
 284  * specification regarding legacy I/O support.  Thus, we have to make these operations
 285  * platform dependent...
 286  */
 287 #define __inb           platform_inb
 288 #define __inw           platform_inw
 289 #define __inl           platform_inl
 290 #define __outb          platform_outb
 291 #define __outw          platform_outw
 292 #define __outl          platform_outl
 293 #define __mmiowb        platform_mmiowb
 294
 295 #define inb(p)          __inb(p)
 296 #define inw(p)          __inw(p)
 297 #define inl(p)          __inl(p)
 298 #define insb(p,d,c)     __insb(p,d,c)
 299 #define insw(p,d,c)     __insw(p,d,c)
 300 #define insl(p,d,c)     __insl(p,d,c)
 301 #define outb(v,p)       __outb(v,p)
 302 #define outw(v,p)       __outw(v,p)
 303 #define outl(v,p)       __outl(v,p)
 304 #define outsb(p,s,c)    __outsb(p,s,c)
 305 #define outsw(p,s,c)    __outsw(p,s,c)
 306 #define outsl(p,s,c)    __outsl(p,s,c)
 307 #define mmiowb()        __mmiowb()
 308
 309 /*
 310  * The address passed to these functions are ioremap()ped already.
 311  *
 312  * We need these to be machine vectors since some platforms don't provide
 313  * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
 314  * a good idea).  Writes are ok though for all existing ia64 platforms (and
 315  * hopefully it'll stay that way).
 316  */
 317 static inline unsigned char
 318 ___ia64_readb (const volatile void __iomem *addr)
 319 {
 320         return *(volatile unsigned char __force *)addr;
 321 }
 322
 323 static inline unsigned short
 324 ___ia64_readw (const volatile void __iomem *addr)
 325 {
 326         return *(volatile unsigned short __force *)addr;
 327 }
 328
 329 static inline unsigned int
 330 ___ia64_readl (const volatile void __iomem *addr)
 331 {
 332         return *(volatile unsigned int __force *) addr;
 333 }
 334
 335 static inline unsigned long
 336 ___ia64_readq (const volatile void __iomem *addr)
 337 {
 338         return *(volatile unsigned long __force *) addr;
 339 }
 340
 341 static inline void
 342 __writeb (unsigned char val, volatile void __iomem *addr)
 343 {
 344         *(volatile unsigned char __force *) addr = val;
 345 }
 346
 347 static inline void
 348 __writew (unsigned short val, volatile void __iomem *addr)
 349 {
 350         *(volatile unsigned short __force *) addr = val;
 351 }
 352
 353 static inline void
 354 __writel (unsigned int val, volatile void __iomem *addr)
 355 {
 356         *(volatile unsigned int __force *) addr = val;
 357 }
 358
 359 static inline void
 360 __writeq (unsigned long val, volatile void __iomem *addr)
 361 {
 362         *(volatile unsigned long __force *) addr = val;
 363 }
 364
 365 #define __readb         platform_readb
 366 #define __readw         platform_readw
 367 #define __readl         platform_readl
 368 #define __readq         platform_readq
 369 #define __readb_relaxed platform_readb_relaxed
 370 #define __readw_relaxed platform_readw_relaxed
 371 #define __readl_relaxed platform_readl_relaxed
 372 #define __readq_relaxed platform_readq_relaxed
 373
 374 #define readb(a)        __readb((a))
 375 #define readw(a)        __readw((a))
 376 #define readl(a)        __readl((a))
 377 #define readq(a)        __readq((a))
 378 #define readb_relaxed(a)        __readb_relaxed((a))
 379 #define readw_relaxed(a)        __readw_relaxed((a))
 380 #define readl_relaxed(a)        __readl_relaxed((a))
 381 #define readq_relaxed(a)        __readq_relaxed((a))
 382 #define __raw_readb     readb
 383 #define __raw_readw     readw
 384 #define __raw_readl     readl
 385 #define __raw_readq     readq
 386 #define __raw_readb_relaxed     readb_relaxed
 387 #define __raw_readw_relaxed     readw_relaxed
 388 #define __raw_readl_relaxed     readl_relaxed
 389 #define __raw_readq_relaxed     readq_relaxed
 390 #define writeb(v,a)     __writeb((v), (a))
 391 #define writew(v,a)     __writew((v), (a))
 392 #define writel(v,a)     __writel((v), (a))
 393 #define writeq(v,a)     __writeq((v), (a))
 394 #define __raw_writeb    writeb
 395 #define __raw_writew    writew
 396 #define __raw_writel    writel
 397 #define __raw_writeq    writeq
 398
 399 #ifndef inb_p
 400 # define inb_p          inb
 401 #endif
 402 #ifndef inw_p
 403 # define inw_p          inw
 404 #endif
 405 #ifndef inl_p
 406 # define inl_p          inl
 407 #endif
 408
 409 #ifndef outb_p
 410 # define outb_p         outb
 411 #endif
 412 #ifndef outw_p
 413 # define outw_p         outw
 414 #endif
 415 #ifndef outl_p
 416 # define outl_p         outl
 417 #endif
 418
 419 extern void __iomem * ioremap(unsigned long offset, unsigned long size);
 420 extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
 421
 422 static inline void
 423 iounmap (volatile void __iomem *addr)
 424 {
 425 }
 426
 427 /* Use normal IO mappings for DMI */
 428 #define dmi_ioremap ioremap
 429 #define dmi_iounmap(x,l) iounmap(x)
 430 #define dmi_alloc(l) kmalloc(l, GFP_ATOMIC)
 431
 432 # ifdef __KERNEL__
 433
 434 /*
 435  * String version of IO memory access ops:
 436  */
 437 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
 438 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
 439 extern void memset_io(volatile void __iomem *s, int c, long n);
 440
 441 #define dma_cache_inv(_start,_size)             do { } while (0)
 442 #define dma_cache_wback(_start,_size)           do { } while (0)
 443 #define dma_cache_wback_inv(_start,_size)       do { } while (0)
 444
 445 # endif /* __KERNEL__ */
 446
 447 /*
 448  * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing.  It is said that
 449  * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
 450  * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
 451  * SPECweb-like workloads on zx1-based machines.  Thus, for now we favor I/O MMU bypassing
 452  * over BIO-level virtual merging.
 453  */
 454 extern unsigned long ia64_max_iommu_merge_mask;
 455 #if 1
 456 #define BIO_VMERGE_BOUNDARY     0
 457 #else
 458 /*
 459  * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here.  Should be
 460  * replaced by dma_merge_mask() or something of that sort.  Note: the only way
 461  * BIO_VMERGE_BOUNDARY is used is to mask off bits.  Effectively, our definition gets
 462  * expanded into:
 463  *
 464  *      addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
 465  *
 466  * which is precisely what we want.
 467  */
 468 #define BIO_VMERGE_BOUNDARY     (ia64_max_iommu_merge_mask + 1)
 469 #endif
 470
 471 #endif /* _ASM_IA64_IO_H */