2 * BRIEF MODULE DESCRIPTION
3 * ITE 8172G interrupt/setup routines.
5 * Copyright 2000,2001 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 * ppopov@mvista.com or source@mvista.com
9 * Part of this file was derived from Carsten Langgaard's
10 * arch/mips/mips-boards/atlas/atlas_int.c.
12 * Carsten Langgaard, carstenl@mips.com
13 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * You should have received a copy of the GNU General Public License along
32 * with this program; if not, write to the Free Software Foundation, Inc.,
33 * 675 Mass Ave, Cambridge, MA 02139, USA.
35 #include <linux/errno.h>
36 #include <linux/init.h>
37 #include <linux/irq.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/module.h>
40 #include <linux/signal.h>
41 #include <linux/sched.h>
42 #include <linux/types.h>
43 #include <linux/interrupt.h>
44 #include <linux/ioport.h>
45 #include <linux/timex.h>
46 #include <linux/slab.h>
47 #include <linux/random.h>
48 #include <linux/serial_reg.h>
49 #include <linux/bitops.h>
51 #include <asm/bootinfo.h>
53 #include <asm/mipsregs.h>
54 #include <asm/system.h>
55 #include <asm/it8172/it8172.h>
56 #include <asm/it8172/it8172_int.h>
57 #include <asm/it8172/it8172_dbg.h>
60 #define EXT_IRQ0_TO_IP 2 /* IP 2 */
61 #define EXT_IRQ5_TO_IP 7 /* IP 7 */
63 #define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
65 extern void set_debug_traps(void);
66 extern void mips_timer_interrupt(int irq
, struct pt_regs
*regs
);
68 struct it8172_intc_regs
volatile *it8172_hw0_icregs
=
69 (struct it8172_intc_regs
volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE
+ IT_INTC_BASE
));
71 static void disable_it8172_irq(unsigned int irq_nr
)
73 if ( (irq_nr
>= IT8172_LPC_IRQ_BASE
) && (irq_nr
<= IT8172_SERIRQ_15
)) {
75 it8172_hw0_icregs
->lpc_mask
|=
76 (1 << (irq_nr
- IT8172_LPC_IRQ_BASE
));
77 } else if ( (irq_nr
>= IT8172_LB_IRQ_BASE
) && (irq_nr
<= IT8172_IOCHK_IRQ
)) {
78 /* Local Bus interrupt */
79 it8172_hw0_icregs
->lb_mask
|=
80 (1 << (irq_nr
- IT8172_LB_IRQ_BASE
));
81 } else if ( (irq_nr
>= IT8172_PCI_DEV_IRQ_BASE
) && (irq_nr
<= IT8172_DMA_IRQ
)) {
82 /* PCI and other interrupts */
83 it8172_hw0_icregs
->pci_mask
|=
84 (1 << (irq_nr
- IT8172_PCI_DEV_IRQ_BASE
));
85 } else if ( (irq_nr
>= IT8172_NMI_IRQ_BASE
) && (irq_nr
<= IT8172_POWER_NMI_IRQ
)) {
87 it8172_hw0_icregs
->nmi_mask
|=
88 (1 << (irq_nr
- IT8172_NMI_IRQ_BASE
));
90 panic("disable_it8172_irq: bad irq %d", irq_nr
);
94 static void enable_it8172_irq(unsigned int irq_nr
)
96 if ( (irq_nr
>= IT8172_LPC_IRQ_BASE
) && (irq_nr
<= IT8172_SERIRQ_15
)) {
98 it8172_hw0_icregs
->lpc_mask
&=
99 ~(1 << (irq_nr
- IT8172_LPC_IRQ_BASE
));
101 else if ( (irq_nr
>= IT8172_LB_IRQ_BASE
) && (irq_nr
<= IT8172_IOCHK_IRQ
)) {
102 /* Local Bus interrupt */
103 it8172_hw0_icregs
->lb_mask
&=
104 ~(1 << (irq_nr
- IT8172_LB_IRQ_BASE
));
106 else if ( (irq_nr
>= IT8172_PCI_DEV_IRQ_BASE
) && (irq_nr
<= IT8172_DMA_IRQ
)) {
107 /* PCI and other interrupts */
108 it8172_hw0_icregs
->pci_mask
&=
109 ~(1 << (irq_nr
- IT8172_PCI_DEV_IRQ_BASE
));
111 else if ( (irq_nr
>= IT8172_NMI_IRQ_BASE
) && (irq_nr
<= IT8172_POWER_NMI_IRQ
)) {
113 it8172_hw0_icregs
->nmi_mask
&=
114 ~(1 << (irq_nr
- IT8172_NMI_IRQ_BASE
));
117 panic("enable_it8172_irq: bad irq %d", irq_nr
);
121 static unsigned int startup_ite_irq(unsigned int irq
)
123 enable_it8172_irq(irq
);
127 #define shutdown_ite_irq disable_it8172_irq
128 #define mask_and_ack_ite_irq disable_it8172_irq
130 static void end_ite_irq(unsigned int irq
)
132 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
)))
133 enable_it8172_irq(irq
);
136 static struct hw_interrupt_type it8172_irq_type
= {
137 .typename
= "ITE8172",
138 .startup
= startup_ite_irq
,
139 .shutdown
= shutdown_ite_irq
,
140 .enable
= enable_it8172_irq
,
141 .disable
= disable_it8172_irq
,
142 .ack
= mask_and_ack_ite_irq
,
147 static void enable_none(unsigned int irq
) { }
148 static unsigned int startup_none(unsigned int irq
) { return 0; }
149 static void disable_none(unsigned int irq
) { }
150 static void ack_none(unsigned int irq
) { }
152 /* startup is the same as "enable", shutdown is same as "disable" */
153 #define shutdown_none disable_none
154 #define end_none enable_none
156 static struct hw_interrupt_type cp0_irq_type
= {
157 .typename
= "CP0 Count",
158 .startup
= startup_none
,
159 .shutdown
= shutdown_none
,
160 .enable
= enable_none
,
161 .disable
= disable_none
,
166 void enable_cpu_timer(void)
170 local_irq_save(flags
);
171 set_c0_status(0x100 << EXT_IRQ5_TO_IP
);
172 local_irq_restore(flags
);
175 void __init
arch_init_irq(void)
180 /* mask all interrupts */
181 it8172_hw0_icregs
->lb_mask
= 0xffff;
182 it8172_hw0_icregs
->lpc_mask
= 0xffff;
183 it8172_hw0_icregs
->pci_mask
= 0xffff;
184 it8172_hw0_icregs
->nmi_mask
= 0xffff;
186 /* make all interrupts level triggered */
187 it8172_hw0_icregs
->lb_trigger
= 0;
188 it8172_hw0_icregs
->lpc_trigger
= 0;
189 it8172_hw0_icregs
->pci_trigger
= 0;
190 it8172_hw0_icregs
->nmi_trigger
= 0;
192 /* active level setting */
193 /* uart, keyboard, and mouse are active high */
194 it8172_hw0_icregs
->lpc_level
= (0x10 | 0x2 | 0x1000);
195 it8172_hw0_icregs
->lb_level
|= 0x20;
197 /* keyboard and mouse are edge triggered */
198 it8172_hw0_icregs
->lpc_trigger
|= (0x2 | 0x1000);
202 // Enable this piece of code to make internal USB interrupt
204 it8172_hw0_icregs
->pci_trigger
|=
205 (1 << (IT8172_USB_IRQ
- IT8172_PCI_DEV_IRQ_BASE
));
206 it8172_hw0_icregs
->pci_level
&=
207 ~(1 << (IT8172_USB_IRQ
- IT8172_PCI_DEV_IRQ_BASE
));
210 for (i
= 0; i
<= IT8172_LAST_IRQ
; i
++) {
211 irq_desc
[i
].chip
= &it8172_irq_type
;
212 spin_lock_init(&irq_desc
[i
].lock
);
214 irq_desc
[MIPS_CPU_TIMER_IRQ
].chip
= &cp0_irq_type
;
215 set_c0_status(ALLINTS_NOTIMER
);
218 void mips_spurious_interrupt(struct pt_regs
*regs
)
223 unsigned long status
, cause
;
225 printk("got spurious interrupt\n");
226 status
= read_c0_status();
227 cause
= read_c0_cause();
228 printk("status %x cause %x\n", status
, cause
);
229 printk("epc %x badvaddr %x \n", regs
->cp0_epc
, regs
->cp0_badvaddr
);
233 void it8172_hw0_irqdispatch(struct pt_regs
*regs
)
236 unsigned short intstatus
= 0, status
= 0;
238 intstatus
= it8172_hw0_icregs
->intstatus
;
239 if (intstatus
& 0x8) {
240 panic("Got NMI interrupt");
241 } else if (intstatus
& 0x4) {
244 status
|= it8172_hw0_icregs
->pci_req
;
245 while (!(status
& 0x1)) {
249 irq
+= IT8172_PCI_DEV_IRQ_BASE
;
250 } else if (intstatus
& 0x1) {
251 /* Local Bus interrupt */
253 status
|= it8172_hw0_icregs
->lb_req
;
254 while (!(status
& 0x1)) {
258 irq
+= IT8172_LB_IRQ_BASE
;
259 } else if (intstatus
& 0x2) {
261 /* Since some lpc interrupts are edge triggered,
262 * we could lose an interrupt this way because
263 * we acknowledge all ints at onces. Revisit.
265 status
|= it8172_hw0_icregs
->lpc_req
;
266 it8172_hw0_icregs
->lpc_req
= 0; /* acknowledge ints */
268 while (!(status
& 0x1)) {
272 irq
+= IT8172_LPC_IRQ_BASE
;
279 asmlinkage
void plat_irq_dispatch(struct pt_regs
*regs
)
281 unsigned int pending
= read_c0_cause() & read_c0_status() & ST0_IM
;
284 mips_spurious_interrupt(regs
);
285 else if (pending
& CAUSEF_IP7
)
286 ll_timer_interrupt(127, regs
);
287 else if (pending
& CAUSEF_IP2
)
288 it8172_hw0_irqdispatch(regs
);
291 void show_pending_irqs(void)
293 fputs("intstatus: ");
294 put32(it8172_hw0_icregs
->intstatus
);
298 put32(it8172_hw0_icregs
->pci_req
);
302 put32(it8172_hw0_icregs
->lb_req
);
306 put32(it8172_hw0_icregs
->lpc_req
);