drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include <linux/io-mapping.h>
  36
  37 /* General customization:
  38  */
  39
  40 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  41
  42 #define DRIVER_NAME             "i915"
  43 #define DRIVER_DESC             "Intel Graphics"
  44 #define DRIVER_DATE             "20080730"
  45
  46 enum pipe {
  47         PIPE_A = 0,
  48         PIPE_B,
  49 };
  50
  51 #define I915_NUM_PIPE   2
  52
  53 /* Interface history:
  54  *
  55  * 1.1: Original.
  56  * 1.2: Add Power Management
  57  * 1.3: Add vblank support
  58  * 1.4: Fix cmdbuffer path, add heap destroy
  59  * 1.5: Add vblank pipe configuration
  60  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  61  *      - Support vertical blank on secondary display pipe
  62  */
  63 #define DRIVER_MAJOR            1
  64 #define DRIVER_MINOR            6
  65 #define DRIVER_PATCHLEVEL       0
  66
  67 #define WATCH_COHERENCY 0
  68 #define WATCH_BUF       0
  69 #define WATCH_EXEC      0
  70 #define WATCH_LRU       0
  71 #define WATCH_RELOC     0
  72 #define WATCH_INACTIVE  0
  73 #define WATCH_PWRITE    0
  74
  75 #define I915_GEM_PHYS_CURSOR_0 1
  76 #define I915_GEM_PHYS_CURSOR_1 2
  77 #define I915_GEM_PHYS_OVERLAY_REGS 3
  78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  79
  80 struct drm_i915_gem_phys_object {
  81         int id;
  82         struct page **page_list;
  83         drm_dma_handle_t *handle;
  84         struct drm_gem_object *cur_obj;
  85 };
  86
  87 typedef struct _drm_i915_ring_buffer {
  88         unsigned long Size;
  89         u8 *virtual_start;
  90         int head;
  91         int tail;
  92         int space;
  93         drm_local_map_t map;
  94         struct drm_gem_object *ring_obj;
  95 } drm_i915_ring_buffer_t;
  96
  97 struct mem_block {
  98         struct mem_block *next;
  99         struct mem_block *prev;
 100         int start;
 101         int size;
 102         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 103 };
 104
 105 struct opregion_header;
 106 struct opregion_acpi;
 107 struct opregion_swsci;
 108 struct opregion_asle;
 109
 110 struct intel_opregion {
 111         struct opregion_header *header;
 112         struct opregion_acpi *acpi;
 113         struct opregion_swsci *swsci;
 114         struct opregion_asle *asle;
 115         int enabled;
 116 };
 117
 118 struct drm_i915_master_private {
 119         drm_local_map_t *sarea;
 120         struct _drm_i915_sarea *sarea_priv;
 121 };
 122 #define I915_FENCE_REG_NONE -1
 123
 124 struct drm_i915_fence_reg {
 125         struct drm_gem_object *obj;
 126 };
 127
 128 struct sdvo_device_mapping {
 129         u8 dvo_port;
 130         u8 slave_addr;
 131         u8 dvo_wiring;
 132         u8 initialized;
 133 };
 134
 135 struct drm_i915_error_state {
 136         u32 eir;
 137         u32 pgtbl_er;
 138         u32 pipeastat;
 139         u32 pipebstat;
 140         u32 ipeir;
 141         u32 ipehr;
 142         u32 instdone;
 143         u32 acthd;
 144         u32 instpm;
 145         u32 instps;
 146         u32 instdone1;
 147         u32 seqno;
 148         struct timeval time;
 149 };
 150
 151 typedef struct drm_i915_private {
 152         struct drm_device *dev;
 153
 154         int has_gem;
 155
 156         void __iomem *regs;
 157
 158         struct pci_dev *bridge_dev;
 159         drm_i915_ring_buffer_t ring;
 160
 161         drm_dma_handle_t *status_page_dmah;
 162         void *hw_status_page;
 163         dma_addr_t dma_status_page;
 164         uint32_t counter;
 165         unsigned int status_gfx_addr;
 166         drm_local_map_t hws_map;
 167         struct drm_gem_object *hws_obj;
 168
 169         struct resource mch_res;
 170
 171         unsigned int cpp;
 172         int back_offset;
 173         int front_offset;
 174         int current_page;
 175         int page_flipping;
 176
 177         wait_queue_head_t irq_queue;
 178         atomic_t irq_received;
 179         /** Protects user_irq_refcount and irq_mask_reg */
 180         spinlock_t user_irq_lock;
 181         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 182         int user_irq_refcount;
 183         /** Cached value of IMR to avoid reads in updating the bitfield */
 184         u32 irq_mask_reg;
 185         u32 pipestat[2];
 186         /** splitted irq regs for graphics and display engine on IGDNG,
 187             irq_mask_reg is still used for display irq. */
 188         u32 gt_irq_mask_reg;
 189         u32 gt_irq_enable_reg;
 190         u32 de_irq_enable_reg;
 191
 192         u32 hotplug_supported_mask;
 193         struct work_struct hotplug_work;
 194
 195         int tex_lru_log_granularity;
 196         int allow_batchbuffer;
 197         struct mem_block *agp_heap;
 198         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 199         int vblank_pipe;
 200
 201         bool cursor_needs_physical;
 202
 203         struct drm_mm vram;
 204
 205         int irq_enabled;
 206
 207         struct intel_opregion opregion;
 208
 209         /* LVDS info */
 210         int backlight_duty_cycle;  /* restore backlight to this value */
 211         bool panel_wants_dither;
 212         struct drm_display_mode *panel_fixed_mode;
 213         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 214         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 215
 216         /* Feature bits from the VBIOS */
 217         unsigned int int_tv_support:1;
 218         unsigned int lvds_dither:1;
 219         unsigned int lvds_vbt:1;
 220         unsigned int int_crt_support:1;
 221         unsigned int lvds_use_ssc:1;
 222         unsigned int edp_support:1;
 223         int lvds_ssc_freq;
 224
 225         int crt_ddc_bus; /* -1 = unknown, else GPIO to use for CRT DDC */
 226         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 227         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 228         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 229
 230         unsigned int fsb_freq, mem_freq;
 231
 232         spinlock_t error_lock;
 233         struct drm_i915_error_state *first_error;
 234         struct work_struct error_work;
 235         struct workqueue_struct *wq;
 236
 237         /* Register state */
 238         u8 saveLBB;
 239         u32 saveDSPACNTR;
 240         u32 saveDSPBCNTR;
 241         u32 saveDSPARB;
 242         u32 saveRENDERSTANDBY;
 243         u32 saveHWS;
 244         u32 savePIPEACONF;
 245         u32 savePIPEBCONF;
 246         u32 savePIPEASRC;
 247         u32 savePIPEBSRC;
 248         u32 saveFPA0;
 249         u32 saveFPA1;
 250         u32 saveDPLL_A;
 251         u32 saveDPLL_A_MD;
 252         u32 saveHTOTAL_A;
 253         u32 saveHBLANK_A;
 254         u32 saveHSYNC_A;
 255         u32 saveVTOTAL_A;
 256         u32 saveVBLANK_A;
 257         u32 saveVSYNC_A;
 258         u32 saveBCLRPAT_A;
 259         u32 savePIPEASTAT;
 260         u32 saveDSPASTRIDE;
 261         u32 saveDSPASIZE;
 262         u32 saveDSPAPOS;
 263         u32 saveDSPAADDR;
 264         u32 saveDSPASURF;
 265         u32 saveDSPATILEOFF;
 266         u32 savePFIT_PGM_RATIOS;
 267         u32 saveBLC_PWM_CTL;
 268         u32 saveBLC_PWM_CTL2;
 269         u32 saveFPB0;
 270         u32 saveFPB1;
 271         u32 saveDPLL_B;
 272         u32 saveDPLL_B_MD;
 273         u32 saveHTOTAL_B;
 274         u32 saveHBLANK_B;
 275         u32 saveHSYNC_B;
 276         u32 saveVTOTAL_B;
 277         u32 saveVBLANK_B;
 278         u32 saveVSYNC_B;
 279         u32 saveBCLRPAT_B;
 280         u32 savePIPEBSTAT;
 281         u32 saveDSPBSTRIDE;
 282         u32 saveDSPBSIZE;
 283         u32 saveDSPBPOS;
 284         u32 saveDSPBADDR;
 285         u32 saveDSPBSURF;
 286         u32 saveDSPBTILEOFF;
 287         u32 saveVGA0;
 288         u32 saveVGA1;
 289         u32 saveVGA_PD;
 290         u32 saveVGACNTRL;
 291         u32 saveADPA;
 292         u32 saveLVDS;
 293         u32 savePP_ON_DELAYS;
 294         u32 savePP_OFF_DELAYS;
 295         u32 saveDVOA;
 296         u32 saveDVOB;
 297         u32 saveDVOC;
 298         u32 savePP_ON;
 299         u32 savePP_OFF;
 300         u32 savePP_CONTROL;
 301         u32 savePP_DIVISOR;
 302         u32 savePFIT_CONTROL;
 303         u32 save_palette_a[256];
 304         u32 save_palette_b[256];
 305         u32 saveFBC_CFB_BASE;
 306         u32 saveFBC_LL_BASE;
 307         u32 saveFBC_CONTROL;
 308         u32 saveFBC_CONTROL2;
 309         u32 saveIER;
 310         u32 saveIIR;
 311         u32 saveIMR;
 312         u32 saveCACHE_MODE_0;
 313         u32 saveD_STATE;
 314         u32 saveDSPCLK_GATE_D;
 315         u32 saveMI_ARB_STATE;
 316         u32 saveSWF0[16];
 317         u32 saveSWF1[16];
 318         u32 saveSWF2[3];
 319         u8 saveMSR;
 320         u8 saveSR[8];
 321         u8 saveGR[25];
 322         u8 saveAR_INDEX;
 323         u8 saveAR[21];
 324         u8 saveDACMASK;
 325         u8 saveCR[37];
 326         uint64_t saveFENCE[16];
 327         u32 saveCURACNTR;
 328         u32 saveCURAPOS;
 329         u32 saveCURABASE;
 330         u32 saveCURBCNTR;
 331         u32 saveCURBPOS;
 332         u32 saveCURBBASE;
 333         u32 saveCURSIZE;
 334         u32 saveDP_B;
 335         u32 saveDP_C;
 336         u32 saveDP_D;
 337         u32 savePIPEA_GMCH_DATA_M;
 338         u32 savePIPEB_GMCH_DATA_M;
 339         u32 savePIPEA_GMCH_DATA_N;
 340         u32 savePIPEB_GMCH_DATA_N;
 341         u32 savePIPEA_DP_LINK_M;
 342         u32 savePIPEB_DP_LINK_M;
 343         u32 savePIPEA_DP_LINK_N;
 344         u32 savePIPEB_DP_LINK_N;
 345
 346         struct {
 347                 struct drm_mm gtt_space;
 348
 349                 struct io_mapping *gtt_mapping;
 350                 int gtt_mtrr;
 351
 352                 /**
 353                  * List of objects currently involved in rendering from the
 354                  * ringbuffer.
 355                  *
 356                  * Includes buffers having the contents of their GPU caches
 357                  * flushed, not necessarily primitives.  last_rendering_seqno
 358                  * represents when the rendering involved will be completed.
 359                  *
 360                  * A reference is held on the buffer while on this list.
 361                  */
 362                 spinlock_t active_list_lock;
 363                 struct list_head active_list;
 364
 365                 /**
 366                  * List of objects which are not in the ringbuffer but which
 367                  * still have a write_domain which needs to be flushed before
 368                  * unbinding.
 369                  *
 370                  * last_rendering_seqno is 0 while an object is in this list.
 371                  *
 372                  * A reference is held on the buffer while on this list.
 373                  */
 374                 struct list_head flushing_list;
 375
 376                 /**
 377                  * LRU list of objects which are not in the ringbuffer and
 378                  * are ready to unbind, but are still in the GTT.
 379                  *
 380                  * last_rendering_seqno is 0 while an object is in this list.
 381                  *
 382                  * A reference is not held on the buffer while on this list,
 383                  * as merely being GTT-bound shouldn't prevent its being
 384                  * freed, and we'll pull it off the list in the free path.
 385                  */
 386                 struct list_head inactive_list;
 387
 388                 /** LRU list of objects with fence regs on them. */
 389                 struct list_head fence_list;
 390
 391                 /**
 392                  * List of breadcrumbs associated with GPU requests currently
 393                  * outstanding.
 394                  */
 395                 struct list_head request_list;
 396
 397                 /**
 398                  * We leave the user IRQ off as much as possible,
 399                  * but this means that requests will finish and never
 400                  * be retired once the system goes idle. Set a timer to
 401                  * fire periodically while the ring is running. When it
 402                  * fires, go retire requests.
 403                  */
 404                 struct delayed_work retire_work;
 405
 406                 uint32_t next_gem_seqno;
 407
 408                 /**
 409                  * Waiting sequence number, if any
 410                  */
 411                 uint32_t waiting_gem_seqno;
 412
 413                 /**
 414                  * Last seq seen at irq time
 415                  */
 416                 uint32_t irq_gem_seqno;
 417
 418                 /**
 419                  * Flag if the X Server, and thus DRM, is not currently in
 420                  * control of the device.
 421                  *
 422                  * This is set between LeaveVT and EnterVT.  It needs to be
 423                  * replaced with a semaphore.  It also needs to be
 424                  * transitioned away from for kernel modesetting.
 425                  */
 426                 int suspended;
 427
 428                 /**
 429                  * Flag if the hardware appears to be wedged.
 430                  *
 431                  * This is set when attempts to idle the device timeout.
 432                  * It prevents command submission from occuring and makes
 433                  * every pending request fail
 434                  */
 435                 int wedged;
 436
 437                 /** Bit 6 swizzling required for X tiling */
 438                 uint32_t bit_6_swizzle_x;
 439                 /** Bit 6 swizzling required for Y tiling */
 440                 uint32_t bit_6_swizzle_y;
 441
 442                 /* storage for physical objects */
 443                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 444         } mm;
 445         struct sdvo_device_mapping sdvo_mappings[2];
 446
 447         /* Reclocking support */
 448         bool render_reclock_avail;
 449         bool lvds_downclock_avail;
 450         struct work_struct idle_work;
 451         struct timer_list idle_timer;
 452         bool busy;
 453         u16 orig_clock;
 454 } drm_i915_private_t;
 455
 456 /** driver private structure attached to each drm_gem_object */
 457 struct drm_i915_gem_object {
 458         struct drm_gem_object *obj;
 459
 460         /** Current space allocated to this object in the GTT, if any. */
 461         struct drm_mm_node *gtt_space;
 462
 463         /** This object's place on the active/flushing/inactive lists */
 464         struct list_head list;
 465
 466         /** This object's place on the fenced object LRU */
 467         struct list_head fence_list;
 468
 469         /**
 470          * This is set if the object is on the active or flushing lists
 471          * (has pending rendering), and is not set if it's on inactive (ready
 472          * to be unbound).
 473          */
 474         int active;
 475
 476         /**
 477          * This is set if the object has been written to since last bound
 478          * to the GTT
 479          */
 480         int dirty;
 481
 482         /** AGP memory structure for our GTT binding. */
 483         DRM_AGP_MEM *agp_mem;
 484
 485         struct page **pages;
 486         int pages_refcount;
 487
 488         /**
 489          * Current offset of the object in GTT space.
 490          *
 491          * This is the same as gtt_space->start
 492          */
 493         uint32_t gtt_offset;
 494         /**
 495          * Required alignment for the object
 496          */
 497         uint32_t gtt_alignment;
 498         /**
 499          * Fake offset for use by mmap(2)
 500          */
 501         uint64_t mmap_offset;
 502
 503         /**
 504          * Fence register bits (if any) for this object.  Will be set
 505          * as needed when mapped into the GTT.
 506          * Protected by dev->struct_mutex.
 507          */
 508         int fence_reg;
 509
 510         /** How many users have pinned this object in GTT space */
 511         int pin_count;
 512
 513         /** Breadcrumb of last rendering to the buffer. */
 514         uint32_t last_rendering_seqno;
 515
 516         /** Current tiling mode for the object. */
 517         uint32_t tiling_mode;
 518         uint32_t stride;
 519
 520         /** Record of address bit 17 of each page at last unbind. */
 521         long *bit_17;
 522
 523         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 524         uint32_t agp_type;
 525
 526         /**
 527          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 528          * flags which individual pages are valid.
 529          */
 530         uint8_t *page_cpu_valid;
 531
 532         /** User space pin count and filp owning the pin */
 533         uint32_t user_pin_count;
 534         struct drm_file *pin_filp;
 535
 536         /** for phy allocated objects */
 537         struct drm_i915_gem_phys_object *phys_obj;
 538
 539         /**
 540          * Used for checking the object doesn't appear more than once
 541          * in an execbuffer object list.
 542          */
 543         int in_execbuffer;
 544 };
 545
 546 /**
 547  * Request queue structure.
 548  *
 549  * The request queue allows us to note sequence numbers that have been emitted
 550  * and may be associated with active buffers to be retired.
 551  *
 552  * By keeping this list, we can avoid having to do questionable
 553  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 554  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 555  */
 556 struct drm_i915_gem_request {
 557         /** GEM sequence number associated with this request. */
 558         uint32_t seqno;
 559
 560         /** Time at which this request was emitted, in jiffies. */
 561         unsigned long emitted_jiffies;
 562
 563         /** global list entry for this request */
 564         struct list_head list;
 565
 566         /** file_priv list entry for this request */
 567         struct list_head client_list;
 568 };
 569
 570 struct drm_i915_file_private {
 571         struct {
 572                 struct list_head request_list;
 573         } mm;
 574 };
 575
 576 enum intel_chip_family {
 577         CHIP_I8XX = 0x01,
 578         CHIP_I9XX = 0x02,
 579         CHIP_I915 = 0x04,
 580         CHIP_I965 = 0x08,
 581 };
 582
 583 extern struct drm_ioctl_desc i915_ioctls[];
 584 extern int i915_max_ioctl;
 585 extern unsigned int i915_fbpercrtc;
 586 extern unsigned int i915_powersave;
 587
 588 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 589 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 590
 591                                 /* i915_dma.c */
 592 extern void i915_kernel_lost_context(struct drm_device * dev);
 593 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 594 extern int i915_driver_unload(struct drm_device *);
 595 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 596 extern void i915_driver_lastclose(struct drm_device * dev);
 597 extern void i915_driver_preclose(struct drm_device *dev,
 598                                  struct drm_file *file_priv);
 599 extern void i915_driver_postclose(struct drm_device *dev,
 600                                   struct drm_file *file_priv);
 601 extern int i915_driver_device_is_agp(struct drm_device * dev);
 602 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 603                               unsigned long arg);
 604 extern int i915_emit_box(struct drm_device *dev,
 605                          struct drm_clip_rect *boxes,
 606                          int i, int DR1, int DR4);
 607
 608 /* i915_irq.c */
 609 extern int i915_irq_emit(struct drm_device *dev, void *data,
 610                          struct drm_file *file_priv);
 611 extern int i915_irq_wait(struct drm_device *dev, void *data,
 612                          struct drm_file *file_priv);
 613 void i915_user_irq_get(struct drm_device *dev);
 614 void i915_user_irq_put(struct drm_device *dev);
 615 extern void i915_enable_interrupt (struct drm_device *dev);
 616
 617 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 618 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 619 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 620 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 621 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 622                                 struct drm_file *file_priv);
 623 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 624                                 struct drm_file *file_priv);
 625 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 626 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 627 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 628 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 629 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 630                             struct drm_file *file_priv);
 631 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 632
 633 void
 634 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 635
 636 void
 637 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 638
 639
 640 /* i915_mem.c */
 641 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 642                           struct drm_file *file_priv);
 643 extern int i915_mem_free(struct drm_device *dev, void *data,
 644                          struct drm_file *file_priv);
 645 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 646                               struct drm_file *file_priv);
 647 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 648                                  struct drm_file *file_priv);
 649 extern void i915_mem_takedown(struct mem_block **heap);
 650 extern void i915_mem_release(struct drm_device * dev,
 651                              struct drm_file *file_priv, struct mem_block *heap);
 652 /* i915_gem.c */
 653 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 654                         struct drm_file *file_priv);
 655 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 656                           struct drm_file *file_priv);
 657 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 658                          struct drm_file *file_priv);
 659 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 660                           struct drm_file *file_priv);
 661 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 662                         struct drm_file *file_priv);
 663 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 664                         struct drm_file *file_priv);
 665 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 666                               struct drm_file *file_priv);
 667 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 668                              struct drm_file *file_priv);
 669 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 670                         struct drm_file *file_priv);
 671 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 672                        struct drm_file *file_priv);
 673 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 674                          struct drm_file *file_priv);
 675 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 676                         struct drm_file *file_priv);
 677 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 678                             struct drm_file *file_priv);
 679 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 680                            struct drm_file *file_priv);
 681 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 682                            struct drm_file *file_priv);
 683 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 684                         struct drm_file *file_priv);
 685 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 686                         struct drm_file *file_priv);
 687 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 688                                 struct drm_file *file_priv);
 689 void i915_gem_load(struct drm_device *dev);
 690 int i915_gem_init_object(struct drm_gem_object *obj);
 691 void i915_gem_free_object(struct drm_gem_object *obj);
 692 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 693 void i915_gem_object_unpin(struct drm_gem_object *obj);
 694 int i915_gem_object_unbind(struct drm_gem_object *obj);
 695 void i915_gem_release_mmap(struct drm_gem_object *obj);
 696 void i915_gem_lastclose(struct drm_device *dev);
 697 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 698 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
 699 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
 700 void i915_gem_retire_requests(struct drm_device *dev);
 701 void i915_gem_retire_work_handler(struct work_struct *work);
 702 void i915_gem_clflush_object(struct drm_gem_object *obj);
 703 int i915_gem_object_set_domain(struct drm_gem_object *obj,
 704                                uint32_t read_domains,
 705                                uint32_t write_domain);
 706 int i915_gem_init_ringbuffer(struct drm_device *dev);
 707 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 708 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 709                      unsigned long end);
 710 int i915_gem_idle(struct drm_device *dev);
 711 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 712 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
 713                                       int write);
 714 int i915_gem_attach_phys_object(struct drm_device *dev,
 715                                 struct drm_gem_object *obj, int id);
 716 void i915_gem_detach_phys_object(struct drm_device *dev,
 717                                  struct drm_gem_object *obj);
 718 void i915_gem_free_all_phys_object(struct drm_device *dev);
 719 int i915_gem_object_get_pages(struct drm_gem_object *obj);
 720 void i915_gem_object_put_pages(struct drm_gem_object *obj);
 721 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
 722
 723 /* i915_gem_tiling.c */
 724 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 725 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
 726 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
 727
 728 /* i915_gem_debug.c */
 729 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 730                           const char *where, uint32_t mark);
 731 #if WATCH_INACTIVE
 732 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 733 #else
 734 #define i915_verify_inactive(dev, file, line)
 735 #endif
 736 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 737 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 738                           const char *where, uint32_t mark);
 739 void i915_dump_lru(struct drm_device *dev, const char *where);
 740
 741 /* i915_debugfs.c */
 742 int i915_debugfs_init(struct drm_minor *minor);
 743 void i915_debugfs_cleanup(struct drm_minor *minor);
 744
 745 /* i915_suspend.c */
 746 extern int i915_save_state(struct drm_device *dev);
 747 extern int i915_restore_state(struct drm_device *dev);
 748
 749 /* i915_suspend.c */
 750 extern int i915_save_state(struct drm_device *dev);
 751 extern int i915_restore_state(struct drm_device *dev);
 752
 753 #ifdef CONFIG_ACPI
 754 /* i915_opregion.c */
 755 extern int intel_opregion_init(struct drm_device *dev, int resume);
 756 extern void intel_opregion_free(struct drm_device *dev, int suspend);
 757 extern void opregion_asle_intr(struct drm_device *dev);
 758 extern void opregion_enable_asle(struct drm_device *dev);
 759 #else
 760 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
 761 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
 762 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 763 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 764 #endif
 765
 766 /* modesetting */
 767 extern void intel_modeset_init(struct drm_device *dev);
 768 extern void intel_modeset_cleanup(struct drm_device *dev);
 769
 770 /**
 771  * Lock test for when it's just for synchronization of ring access.
 772  *
 773  * In that case, we don't need to do it when GEM is initialized as nobody else
 774  * has access to the ring.
 775  */
 776 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 777         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 778                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 779 } while (0)
 780
 781 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 782 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 783 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 784 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 785 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 786 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 787 #define I915_WRITE64(reg, val)  writeq(val, dev_priv->regs + (reg))
 788 #define I915_READ64(reg)        readq(dev_priv->regs + (reg))
 789 #define POSTING_READ(reg)       (void)I915_READ(reg)
 790
 791 #define I915_VERBOSE 0
 792
 793 #define RING_LOCALS     volatile unsigned int *ring_virt__;
 794
 795 #define BEGIN_LP_RING(n) do {                                           \
 796         int bytes__ = 4*(n);                                            \
 797         if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));        \
 798         /* a wrap must occur between instructions so pad beforehand */  \
 799         if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
 800                 i915_wrap_ring(dev);                                    \
 801         if (unlikely (dev_priv->ring.space < bytes__))                  \
 802                 i915_wait_ring(dev, bytes__, __func__);                 \
 803         ring_virt__ = (unsigned int *)                                  \
 804                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);   \
 805         dev_priv->ring.tail += bytes__;                                 \
 806         dev_priv->ring.tail &= dev_priv->ring.Size - 1;                 \
 807         dev_priv->ring.space -= bytes__;                                \
 808 } while (0)
 809
 810 #define OUT_RING(n) do {                                                \
 811         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 812         *ring_virt__++ = (n);                                           \
 813 } while (0)
 814
 815 #define ADVANCE_LP_RING() do {                                          \
 816         if (I915_VERBOSE)                                               \
 817                 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
 818         I915_WRITE(PRB0_TAIL, dev_priv->ring.tail);                     \
 819 } while(0)
 820
 821 /**
 822  * Reads a dword out of the status page, which is written to from the command
 823  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 824  * MI_STORE_DATA_IMM.
 825  *
 826  * The following dwords have a reserved meaning:
 827  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 828  * 0x04: ring 0 head pointer
 829  * 0x05: ring 1 head pointer (915-class)
 830  * 0x06: ring 2 head pointer (915-class)
 831  * 0x10-0x1b: Context status DWords (GM45)
 832  * 0x1f: Last written status offset. (GM45)
 833  *
 834  * The area from dword 0x20 to 0x3ff is available for driver usage.
 835  */
 836 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 837 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 838 #define I915_GEM_HWS_INDEX              0x20
 839 #define I915_BREADCRUMB_INDEX           0x21
 840
 841 extern int i915_wrap_ring(struct drm_device * dev);
 842 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 843
 844 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 845 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 846 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 847 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 848 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 849
 850 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 851 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 852 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 853 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 854                         (dev)->pci_device == 0x27AE)
 855 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 856                        (dev)->pci_device == 0x2982 || \
 857                        (dev)->pci_device == 0x2992 || \
 858                        (dev)->pci_device == 0x29A2 || \
 859                        (dev)->pci_device == 0x2A02 || \
 860                        (dev)->pci_device == 0x2A12 || \
 861                        (dev)->pci_device == 0x2A42 || \
 862                        (dev)->pci_device == 0x2E02 || \
 863                        (dev)->pci_device == 0x2E12 || \
 864                        (dev)->pci_device == 0x2E22 || \
 865                        (dev)->pci_device == 0x2E32 || \
 866                        (dev)->pci_device == 0x2E42 || \
 867                        (dev)->pci_device == 0x0042 || \
 868                        (dev)->pci_device == 0x0046)
 869
 870 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
 871                         (dev)->pci_device == 0x2A12)
 872
 873 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 874
 875 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 876                      (dev)->pci_device == 0x2E12 || \
 877                      (dev)->pci_device == 0x2E22 || \
 878                      (dev)->pci_device == 0x2E32 || \
 879                      (dev)->pci_device == 0x2E42 || \
 880                      IS_GM45(dev))
 881
 882 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
 883 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
 884 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
 885
 886 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 887                         (dev)->pci_device == 0x29B2 ||  \
 888                         (dev)->pci_device == 0x29D2 ||  \
 889                         (IS_IGD(dev)))
 890
 891 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
 892 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
 893 #define IS_IGDNG(dev)   (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
 894
 895 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 896                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
 897                       IS_IGDNG(dev))
 898
 899 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 900                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
 901                         IS_IGD(dev) || IS_IGDNG_M(dev))
 902
 903 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
 904                                 IS_IGDNG(dev))
 905 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 906  * rows, which changed the alignment requirements and fence programming.
 907  */
 908 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
 909                                                       IS_I915GM(dev)))
 910 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_IGDNG(dev))
 911 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_IGDNG(dev))
 912 #define SUPPORTS_EDP(dev)               (IS_IGDNG_M(dev))
 913 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_I965G(dev))
 914 /* dsparb controlled by hw only */
 915 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
 916
 917 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
 918 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
 919
 920 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 921
 922 #endif