2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define AH_USE_EEPROM 0x1
23 #define AR5416_EEPROM_MAGIC 0x5aa5
25 #define AR5416_EEPROM_MAGIC 0xa55a
28 #define CTRY_DEBUG 0x1ff
29 #define CTRY_DEFAULT 0
31 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
32 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
33 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
34 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
35 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
36 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
37 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
38 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
39 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
41 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
42 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
43 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
44 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
45 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
46 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
48 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
49 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
51 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
52 #define AR5416_EEPROM_S 2
53 #define AR5416_EEPROM_OFFSET 0x2000
54 #define AR5416_EEPROM_MAX 0xae0
56 #define AR5416_EEPROM_START_ADDR \
57 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
59 #define SD_NO_CTL 0xE0
70 #define EXT_ADDITIVE (0x8000)
71 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
72 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
73 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
75 #define SUB_NUM_CTL_MODES_AT_5G_40 2
76 #define SUB_NUM_CTL_MODES_AT_2G_40 3
78 #define AR_EEPROM_MAC(i) (0x1d+(i))
79 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
80 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
81 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
83 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
84 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
85 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
86 #define AR_EEPROM_RFSILENT_POLARITY_S 1
88 #define EEP_RFSILENT_ENABLED 0x0001
89 #define EEP_RFSILENT_ENABLED_S 0
90 #define EEP_RFSILENT_POLARITY 0x0002
91 #define EEP_RFSILENT_POLARITY_S 1
92 #define EEP_RFSILENT_GPIO_SEL 0x001c
93 #define EEP_RFSILENT_GPIO_SEL_S 2
95 #define AR5416_OPFLAGS_11A 0x01
96 #define AR5416_OPFLAGS_11G 0x02
97 #define AR5416_OPFLAGS_N_5G_HT40 0x04
98 #define AR5416_OPFLAGS_N_2G_HT40 0x08
99 #define AR5416_OPFLAGS_N_5G_HT20 0x10
100 #define AR5416_OPFLAGS_N_2G_HT20 0x20
102 #define AR5416_EEP_NO_BACK_VER 0x1
103 #define AR5416_EEP_VER 0xE
104 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
105 #define AR5416_EEP_MINOR_VER_2 0x2
106 #define AR5416_EEP_MINOR_VER_3 0x3
107 #define AR5416_EEP_MINOR_VER_7 0x7
108 #define AR5416_EEP_MINOR_VER_9 0x9
109 #define AR5416_EEP_MINOR_VER_16 0x10
110 #define AR5416_EEP_MINOR_VER_17 0x11
111 #define AR5416_EEP_MINOR_VER_19 0x13
112 #define AR5416_EEP_MINOR_VER_20 0x14
114 #define AR5416_NUM_5G_CAL_PIERS 8
115 #define AR5416_NUM_2G_CAL_PIERS 4
116 #define AR5416_NUM_5G_20_TARGET_POWERS 8
117 #define AR5416_NUM_5G_40_TARGET_POWERS 8
118 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
119 #define AR5416_NUM_2G_20_TARGET_POWERS 4
120 #define AR5416_NUM_2G_40_TARGET_POWERS 4
121 #define AR5416_NUM_CTLS 24
122 #define AR5416_NUM_BAND_EDGES 8
123 #define AR5416_NUM_PD_GAINS 4
124 #define AR5416_PD_GAINS_IN_MASK 4
125 #define AR5416_PD_GAIN_ICEPTS 5
126 #define AR5416_EEPROM_MODAL_SPURS 5
127 #define AR5416_MAX_RATE_POWER 63
128 #define AR5416_NUM_PDADC_VALUES 128
129 #define AR5416_BCHAN_UNUSED 0xFF
130 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
131 #define AR5416_MAX_CHAINS 3
132 #define AR5416_PWR_TABLE_OFFSET -5
134 /* Rx gain type values */
135 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
136 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
137 #define AR5416_EEP_RXGAIN_ORIG 2
139 /* Tx gain type values */
140 #define AR5416_EEP_TXGAIN_ORIGINAL 0
141 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
143 #define AR5416_EEP4K_START_LOC 64
144 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
145 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
146 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
147 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
148 #define AR5416_EEP4K_NUM_CTLS 12
149 #define AR5416_EEP4K_NUM_BAND_EDGES 4
150 #define AR5416_EEP4K_NUM_PD_GAINS 2
151 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
152 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
153 #define AR5416_EEP4K_MAX_CHAINS 1
179 rate6mb
, rate9mb
, rate12mb
, rate18mb
,
180 rate24mb
, rate36mb
, rate48mb
, rate54mb
,
181 rate1l
, rate2l
, rate2s
, rate5_5l
,
182 rate5_5s
, rate11l
, rate11s
, rateXr
,
183 rateHt20_0
, rateHt20_1
, rateHt20_2
, rateHt20_3
,
184 rateHt20_4
, rateHt20_5
, rateHt20_6
, rateHt20_7
,
185 rateHt40_0
, rateHt40_1
, rateHt40_2
, rateHt40_3
,
186 rateHt40_4
, rateHt40_5
, rateHt40_6
, rateHt40_7
,
187 rateDupCck
, rateDupOfdm
, rateExtCck
, rateExtOfdm
,
191 enum ath9k_hal_freq_band
{
192 ATH9K_HAL_FREQ_BAND_5GHZ
= 0,
193 ATH9K_HAL_FREQ_BAND_2GHZ
= 1
196 struct base_eep_header
{
207 u16 blueToothOptions
;
223 struct base_eep_header_4k
{
234 u16 blueToothOptions
;
248 struct modal_eep_header
{
249 u32 antCtrlChain
[AR5416_MAX_CHAINS
];
251 u8 antennaGainCh
[AR5416_MAX_CHAINS
];
253 u8 txRxAttenCh
[AR5416_MAX_CHAINS
];
254 u8 rxTxMarginCh
[AR5416_MAX_CHAINS
];
257 u8 xlnaGainCh
[AR5416_MAX_CHAINS
];
262 u8 noiseFloorThreshCh
[AR5416_MAX_CHAINS
];
265 u8 iqCalICh
[AR5416_MAX_CHAINS
];
266 u8 iqCalQCh
[AR5416_MAX_CHAINS
];
271 u8 pwrDecreaseFor2Chain
;
272 u8 pwrDecreaseFor3Chain
;
273 u8 txFrameToDataStart
;
275 u8 ht40PowerIncForPdadc
;
276 u8 bswAtten
[AR5416_MAX_CHAINS
];
277 u8 bswMargin
[AR5416_MAX_CHAINS
];
279 u8 xatten2Db
[AR5416_MAX_CHAINS
];
280 u8 xatten2Margin
[AR5416_MAX_CHAINS
];
286 femBandSelectUsed
:1, xlnabufin
:1, xlnaisel
:2, xlnabufmode
:1;
288 u16 xpaBiasLvlFreq
[3];
291 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
294 struct modal_eep_4k_header
{
295 u32 antCtrlChain
[AR5416_EEP4K_MAX_CHAINS
];
297 u8 antennaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
299 u8 txRxAttenCh
[AR5416_EEP4K_MAX_CHAINS
];
300 u8 rxTxMarginCh
[AR5416_EEP4K_MAX_CHAINS
];
303 u8 xlnaGainCh
[AR5416_EEP4K_MAX_CHAINS
];
308 u8 noiseFloorThreshCh
[AR5416_EEP4K_MAX_CHAINS
];
311 u8 iqCalICh
[AR5416_EEP4K_MAX_CHAINS
];
312 u8 iqCalQCh
[AR5416_EEP4K_MAX_CHAINS
];
317 u8 txFrameToDataStart
;
319 u8 ht40PowerIncForPdadc
;
320 u8 bswAtten
[AR5416_EEP4K_MAX_CHAINS
];
321 u8 bswMargin
[AR5416_EEP4K_MAX_CHAINS
];
323 u8 xatten2Db
[AR5416_EEP4K_MAX_CHAINS
];
324 u8 xatten2Margin
[AR5416_EEP4K_MAX_CHAINS
];
332 struct spur_chan spurChans
[AR5416_EEPROM_MODAL_SPURS
];
336 struct cal_data_per_freq
{
337 u8 pwrPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
338 u8 vpdPdg
[AR5416_NUM_PD_GAINS
][AR5416_PD_GAIN_ICEPTS
];
341 struct cal_data_per_freq_4k
{
342 u8 pwrPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
343 u8 vpdPdg
[AR5416_EEP4K_NUM_PD_GAINS
][AR5416_EEP4K_PD_GAIN_ICEPTS
];
346 struct cal_target_power_leg
{
351 struct cal_target_power_ht
{
357 #ifdef __BIG_ENDIAN_BITFIELD
358 struct cal_ctl_edges
{
363 struct cal_ctl_edges
{
369 struct cal_ctl_data
{
371 ctlEdges
[AR5416_MAX_CHAINS
][AR5416_NUM_BAND_EDGES
];
374 struct cal_ctl_data_4k
{
376 ctlEdges
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_BAND_EDGES
];
379 struct ar5416_eeprom_def
{
380 struct base_eep_header baseEepHeader
;
382 struct modal_eep_header modalHeader
[2];
383 u8 calFreqPier5G
[AR5416_NUM_5G_CAL_PIERS
];
384 u8 calFreqPier2G
[AR5416_NUM_2G_CAL_PIERS
];
385 struct cal_data_per_freq
386 calPierData5G
[AR5416_MAX_CHAINS
][AR5416_NUM_5G_CAL_PIERS
];
387 struct cal_data_per_freq
388 calPierData2G
[AR5416_MAX_CHAINS
][AR5416_NUM_2G_CAL_PIERS
];
389 struct cal_target_power_leg
390 calTargetPower5G
[AR5416_NUM_5G_20_TARGET_POWERS
];
391 struct cal_target_power_ht
392 calTargetPower5GHT20
[AR5416_NUM_5G_20_TARGET_POWERS
];
393 struct cal_target_power_ht
394 calTargetPower5GHT40
[AR5416_NUM_5G_40_TARGET_POWERS
];
395 struct cal_target_power_leg
396 calTargetPowerCck
[AR5416_NUM_2G_CCK_TARGET_POWERS
];
397 struct cal_target_power_leg
398 calTargetPower2G
[AR5416_NUM_2G_20_TARGET_POWERS
];
399 struct cal_target_power_ht
400 calTargetPower2GHT20
[AR5416_NUM_2G_20_TARGET_POWERS
];
401 struct cal_target_power_ht
402 calTargetPower2GHT40
[AR5416_NUM_2G_40_TARGET_POWERS
];
403 u8 ctlIndex
[AR5416_NUM_CTLS
];
404 struct cal_ctl_data ctlData
[AR5416_NUM_CTLS
];
408 struct ar5416_eeprom_4k
{
409 struct base_eep_header_4k baseEepHeader
;
411 struct modal_eep_4k_header modalHeader
;
412 u8 calFreqPier2G
[AR5416_EEP4K_NUM_2G_CAL_PIERS
];
413 struct cal_data_per_freq_4k
414 calPierData2G
[AR5416_EEP4K_MAX_CHAINS
][AR5416_EEP4K_NUM_2G_CAL_PIERS
];
415 struct cal_target_power_leg
416 calTargetPowerCck
[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS
];
417 struct cal_target_power_leg
418 calTargetPower2G
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
419 struct cal_target_power_ht
420 calTargetPower2GHT20
[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS
];
421 struct cal_target_power_ht
422 calTargetPower2GHT40
[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS
];
423 u8 ctlIndex
[AR5416_EEP4K_NUM_CTLS
];
424 struct cal_ctl_data_4k ctlData
[AR5416_EEP4K_NUM_CTLS
];
428 enum reg_ext_bitmap
{
429 REG_EXT_JAPAN_MIDBAND
= 1,
430 REG_EXT_FCC_DFS_HT40
= 2,
431 REG_EXT_JAPAN_NONDFS_HT40
= 3,
432 REG_EXT_JAPAN_DFS_HT40
= 4
435 struct ath9k_country_entry
{
445 EEP_MAP_DEFAULT
= 0x0,
450 #define ar5416_get_eep_ver(_ah) \
451 (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
452 #define ar5416_get_eep_rev(_ah) \
453 (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
454 #define ar5416_get_ntxchains(_txchainmask) \
455 (((_txchainmask >> 2) & 1) + \
456 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
458 #define ar5416_get_eep4k_ver(_ah) \
459 (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
460 #define ar5416_get_eep4k_rev(_ah) \
461 (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
463 int ath9k_hw_set_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
464 u16 cfgCtl
, u8 twiceAntennaReduction
,
465 u8 twiceMaxRegulatoryPower
, u8 powerLimit
);
466 void ath9k_hw_set_addac(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
467 bool ath9k_hw_set_power_per_rate_table(struct ath_hw
*ah
,
468 struct ath9k_channel
*chan
, int16_t *ratesArray
,
469 u16 cfgCtl
, u8 AntennaReduction
,
470 u8 twiceMaxRegulatoryPower
, u8 powerLimit
);
471 bool ath9k_hw_set_power_cal_table(struct ath_hw
*ah
,
472 struct ath9k_channel
*chan
,
473 int16_t *pTxPowerIndexOffset
);
474 bool ath9k_hw_eeprom_set_board_values(struct ath_hw
*ah
,
475 struct ath9k_channel
*chan
);
476 u16
ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw
*ah
,
477 struct ath9k_channel
*chan
);
478 u8
ath9k_hw_get_num_ant_config(struct ath_hw
*ah
,
479 enum ieee80211_band freq_band
);
480 u16
ath9k_hw_eeprom_get_spur_chan(struct ath_hw
*ah
, u16 i
, bool is2GHz
);
481 u32
ath9k_hw_get_eeprom(struct ath_hw
*ah
, enum eeprom_param param
);
482 int ath9k_hw_eeprom_attach(struct ath_hw
*ah
);
484 #endif /* EEPROM_H */