2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 mutex_lock(&dev
->struct_mutex
);
132 drm_gem_object_handle_unreference(obj
);
133 mutex_unlock(&dev
->struct_mutex
);
138 args
->handle
= handle
;
144 fast_shmem_read(struct page
**pages
,
145 loff_t page_base
, int page_offset
,
152 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
155 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
156 kunmap_atomic(vaddr
, KM_USER0
);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
166 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
167 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
169 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
170 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
174 slow_shmem_copy(struct page
*dst_page
,
176 struct page
*src_page
,
180 char *dst_vaddr
, *src_vaddr
;
182 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
183 if (dst_vaddr
== NULL
)
186 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
187 if (src_vaddr
== NULL
) {
188 kunmap_atomic(dst_vaddr
, KM_USER0
);
192 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
194 kunmap_atomic(src_vaddr
, KM_USER1
);
195 kunmap_atomic(dst_vaddr
, KM_USER0
);
201 slow_shmem_bit17_copy(struct page
*gpu_page
,
203 struct page
*cpu_page
,
208 char *gpu_vaddr
, *cpu_vaddr
;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page
, cpu_offset
,
214 gpu_page
, gpu_offset
, length
);
216 return slow_shmem_copy(gpu_page
, gpu_offset
,
217 cpu_page
, cpu_offset
, length
);
220 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
221 if (gpu_vaddr
== NULL
)
224 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
225 if (cpu_vaddr
== NULL
) {
226 kunmap_atomic(gpu_vaddr
, KM_USER0
);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
235 int this_length
= min(cacheline_end
- gpu_offset
, length
);
236 int swizzled_gpu_offset
= gpu_offset
^ 64;
239 memcpy(cpu_vaddr
+ cpu_offset
,
240 gpu_vaddr
+ swizzled_gpu_offset
,
243 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
244 cpu_vaddr
+ cpu_offset
,
247 cpu_offset
+= this_length
;
248 gpu_offset
+= this_length
;
249 length
-= this_length
;
252 kunmap_atomic(cpu_vaddr
, KM_USER1
);
253 kunmap_atomic(gpu_vaddr
, KM_USER0
);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
265 struct drm_i915_gem_pread
*args
,
266 struct drm_file
*file_priv
)
268 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
270 loff_t offset
, page_base
;
271 char __user
*user_data
;
272 int page_offset
, page_length
;
275 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
278 mutex_lock(&dev
->struct_mutex
);
280 ret
= i915_gem_object_get_pages(obj
);
284 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
289 obj_priv
= obj
->driver_private
;
290 offset
= args
->offset
;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base
= (offset
& ~(PAGE_SIZE
-1));
300 page_offset
= offset
& (PAGE_SIZE
-1);
301 page_length
= remain
;
302 if ((page_offset
+ remain
) > PAGE_SIZE
)
303 page_length
= PAGE_SIZE
- page_offset
;
305 ret
= fast_shmem_read(obj_priv
->pages
,
306 page_base
, page_offset
,
307 user_data
, page_length
);
311 remain
-= page_length
;
312 user_data
+= page_length
;
313 offset
+= page_length
;
317 i915_gem_object_put_pages(obj
);
319 mutex_unlock(&dev
->struct_mutex
);
325 i915_gem_object_get_page_gfp_mask (struct drm_gem_object
*obj
)
327 return mapping_gfp_mask(obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
);
331 i915_gem_object_set_page_gfp_mask (struct drm_gem_object
*obj
, gfp_t gfp
)
333 mapping_set_gfp_mask(obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
, gfp
);
337 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
341 ret
= i915_gem_object_get_pages(obj
);
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
346 if (ret
== -ENOMEM
) {
347 struct drm_device
*dev
= obj
->dev
;
350 ret
= i915_gem_evict_something(dev
, obj
->size
);
354 gfp
= i915_gem_object_get_page_gfp_mask(obj
);
355 i915_gem_object_set_page_gfp_mask(obj
, gfp
& ~__GFP_NORETRY
);
356 ret
= i915_gem_object_get_pages(obj
);
357 i915_gem_object_set_page_gfp_mask (obj
, gfp
);
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
371 struct drm_i915_gem_pread
*args
,
372 struct drm_file
*file_priv
)
374 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
375 struct mm_struct
*mm
= current
->mm
;
376 struct page
**user_pages
;
378 loff_t offset
, pinned_pages
, i
;
379 loff_t first_data_page
, last_data_page
, num_pages
;
380 int shmem_page_index
, shmem_page_offset
;
381 int data_page_index
, data_page_offset
;
384 uint64_t data_ptr
= args
->data_ptr
;
385 int do_bit17_swizzling
;
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
393 first_data_page
= data_ptr
/ PAGE_SIZE
;
394 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
395 num_pages
= last_data_page
- first_data_page
+ 1;
397 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
398 if (user_pages
== NULL
)
401 down_read(&mm
->mmap_sem
);
402 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
403 num_pages
, 1, 0, user_pages
, NULL
);
404 up_read(&mm
->mmap_sem
);
405 if (pinned_pages
< num_pages
) {
407 goto fail_put_user_pages
;
410 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
412 mutex_lock(&dev
->struct_mutex
);
414 ret
= i915_gem_object_get_pages_or_evict(obj
);
418 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
423 obj_priv
= obj
->driver_private
;
424 offset
= args
->offset
;
427 /* Operation in this page
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
435 shmem_page_index
= offset
/ PAGE_SIZE
;
436 shmem_page_offset
= offset
& ~PAGE_MASK
;
437 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
438 data_page_offset
= data_ptr
& ~PAGE_MASK
;
440 page_length
= remain
;
441 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
442 page_length
= PAGE_SIZE
- shmem_page_offset
;
443 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
444 page_length
= PAGE_SIZE
- data_page_offset
;
446 if (do_bit17_swizzling
) {
447 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
449 user_pages
[data_page_index
],
454 ret
= slow_shmem_copy(user_pages
[data_page_index
],
456 obj_priv
->pages
[shmem_page_index
],
463 remain
-= page_length
;
464 data_ptr
+= page_length
;
465 offset
+= page_length
;
469 i915_gem_object_put_pages(obj
);
471 mutex_unlock(&dev
->struct_mutex
);
473 for (i
= 0; i
< pinned_pages
; i
++) {
474 SetPageDirty(user_pages
[i
]);
475 page_cache_release(user_pages
[i
]);
477 drm_free_large(user_pages
);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
489 struct drm_file
*file_priv
)
491 struct drm_i915_gem_pread
*args
= data
;
492 struct drm_gem_object
*obj
;
493 struct drm_i915_gem_object
*obj_priv
;
496 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
499 obj_priv
= obj
->driver_private
;
501 /* Bounds check source.
503 * XXX: This could use review for overflow issues...
505 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
506 args
->offset
+ args
->size
> obj
->size
) {
507 drm_gem_object_unreference(obj
);
511 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
512 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
514 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
516 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
520 drm_gem_object_unreference(obj
);
525 /* This is the fast write path which cannot handle
526 * page faults in the source data
530 fast_user_write(struct io_mapping
*mapping
,
531 loff_t page_base
, int page_offset
,
532 char __user
*user_data
,
536 unsigned long unwritten
;
538 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
539 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
541 io_mapping_unmap_atomic(vaddr_atomic
);
547 /* Here's the write path which can sleep for
552 slow_kernel_write(struct io_mapping
*mapping
,
553 loff_t gtt_base
, int gtt_offset
,
554 struct page
*user_page
, int user_offset
,
557 char *src_vaddr
, *dst_vaddr
;
558 unsigned long unwritten
;
560 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
561 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
562 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
563 src_vaddr
+ user_offset
,
565 kunmap_atomic(src_vaddr
, KM_USER1
);
566 io_mapping_unmap_atomic(dst_vaddr
);
573 fast_shmem_write(struct page
**pages
,
574 loff_t page_base
, int page_offset
,
579 unsigned long unwritten
;
581 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
584 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
585 kunmap_atomic(vaddr
, KM_USER0
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
598 struct drm_i915_gem_pwrite
*args
,
599 struct drm_file
*file_priv
)
601 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
;
609 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
611 if (!access_ok(VERIFY_READ
, user_data
, remain
))
615 mutex_lock(&dev
->struct_mutex
);
616 ret
= i915_gem_object_pin(obj
, 0);
618 mutex_unlock(&dev
->struct_mutex
);
621 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
625 obj_priv
= obj
->driver_private
;
626 offset
= obj_priv
->gtt_offset
+ args
->offset
;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base
= (offset
& ~(PAGE_SIZE
-1));
636 page_offset
= offset
& (PAGE_SIZE
-1);
637 page_length
= remain
;
638 if ((page_offset
+ remain
) > PAGE_SIZE
)
639 page_length
= PAGE_SIZE
- page_offset
;
641 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
642 page_offset
, user_data
, page_length
);
644 /* If we get a fault while copying data, then (presumably) our
645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
651 remain
-= page_length
;
652 user_data
+= page_length
;
653 offset
+= page_length
;
657 i915_gem_object_unpin(obj
);
658 mutex_unlock(&dev
->struct_mutex
);
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
671 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
672 struct drm_i915_gem_pwrite
*args
,
673 struct drm_file
*file_priv
)
675 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
676 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
678 loff_t gtt_page_base
, offset
;
679 loff_t first_data_page
, last_data_page
, num_pages
;
680 loff_t pinned_pages
, i
;
681 struct page
**user_pages
;
682 struct mm_struct
*mm
= current
->mm
;
683 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
685 uint64_t data_ptr
= args
->data_ptr
;
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
693 first_data_page
= data_ptr
/ PAGE_SIZE
;
694 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
695 num_pages
= last_data_page
- first_data_page
+ 1;
697 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
698 if (user_pages
== NULL
)
701 down_read(&mm
->mmap_sem
);
702 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
703 num_pages
, 0, 0, user_pages
, NULL
);
704 up_read(&mm
->mmap_sem
);
705 if (pinned_pages
< num_pages
) {
707 goto out_unpin_pages
;
710 mutex_lock(&dev
->struct_mutex
);
711 ret
= i915_gem_object_pin(obj
, 0);
715 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
717 goto out_unpin_object
;
719 obj_priv
= obj
->driver_private
;
720 offset
= obj_priv
->gtt_offset
+ args
->offset
;
723 /* Operation in this page
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
731 gtt_page_base
= offset
& PAGE_MASK
;
732 gtt_page_offset
= offset
& ~PAGE_MASK
;
733 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
734 data_page_offset
= data_ptr
& ~PAGE_MASK
;
736 page_length
= remain
;
737 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
738 page_length
= PAGE_SIZE
- gtt_page_offset
;
739 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
740 page_length
= PAGE_SIZE
- data_page_offset
;
742 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
743 gtt_page_base
, gtt_page_offset
,
744 user_pages
[data_page_index
],
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
753 goto out_unpin_object
;
755 remain
-= page_length
;
756 offset
+= page_length
;
757 data_ptr
+= page_length
;
761 i915_gem_object_unpin(obj
);
763 mutex_unlock(&dev
->struct_mutex
);
765 for (i
= 0; i
< pinned_pages
; i
++)
766 page_cache_release(user_pages
[i
]);
767 drm_free_large(user_pages
);
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
777 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
778 struct drm_i915_gem_pwrite
*args
,
779 struct drm_file
*file_priv
)
781 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
783 loff_t offset
, page_base
;
784 char __user
*user_data
;
785 int page_offset
, page_length
;
788 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
791 mutex_lock(&dev
->struct_mutex
);
793 ret
= i915_gem_object_get_pages(obj
);
797 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
801 obj_priv
= obj
->driver_private
;
802 offset
= args
->offset
;
806 /* Operation in this page
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
812 page_base
= (offset
& ~(PAGE_SIZE
-1));
813 page_offset
= offset
& (PAGE_SIZE
-1);
814 page_length
= remain
;
815 if ((page_offset
+ remain
) > PAGE_SIZE
)
816 page_length
= PAGE_SIZE
- page_offset
;
818 ret
= fast_shmem_write(obj_priv
->pages
,
819 page_base
, page_offset
,
820 user_data
, page_length
);
824 remain
-= page_length
;
825 user_data
+= page_length
;
826 offset
+= page_length
;
830 i915_gem_object_put_pages(obj
);
832 mutex_unlock(&dev
->struct_mutex
);
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
845 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
846 struct drm_i915_gem_pwrite
*args
,
847 struct drm_file
*file_priv
)
849 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
850 struct mm_struct
*mm
= current
->mm
;
851 struct page
**user_pages
;
853 loff_t offset
, pinned_pages
, i
;
854 loff_t first_data_page
, last_data_page
, num_pages
;
855 int shmem_page_index
, shmem_page_offset
;
856 int data_page_index
, data_page_offset
;
859 uint64_t data_ptr
= args
->data_ptr
;
860 int do_bit17_swizzling
;
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
868 first_data_page
= data_ptr
/ PAGE_SIZE
;
869 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
870 num_pages
= last_data_page
- first_data_page
+ 1;
872 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
873 if (user_pages
== NULL
)
876 down_read(&mm
->mmap_sem
);
877 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
878 num_pages
, 0, 0, user_pages
, NULL
);
879 up_read(&mm
->mmap_sem
);
880 if (pinned_pages
< num_pages
) {
882 goto fail_put_user_pages
;
885 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
887 mutex_lock(&dev
->struct_mutex
);
889 ret
= i915_gem_object_get_pages_or_evict(obj
);
893 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
897 obj_priv
= obj
->driver_private
;
898 offset
= args
->offset
;
902 /* Operation in this page
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
910 shmem_page_index
= offset
/ PAGE_SIZE
;
911 shmem_page_offset
= offset
& ~PAGE_MASK
;
912 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
913 data_page_offset
= data_ptr
& ~PAGE_MASK
;
915 page_length
= remain
;
916 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
917 page_length
= PAGE_SIZE
- shmem_page_offset
;
918 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
919 page_length
= PAGE_SIZE
- data_page_offset
;
921 if (do_bit17_swizzling
) {
922 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
924 user_pages
[data_page_index
],
929 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
931 user_pages
[data_page_index
],
938 remain
-= page_length
;
939 data_ptr
+= page_length
;
940 offset
+= page_length
;
944 i915_gem_object_put_pages(obj
);
946 mutex_unlock(&dev
->struct_mutex
);
948 for (i
= 0; i
< pinned_pages
; i
++)
949 page_cache_release(user_pages
[i
]);
950 drm_free_large(user_pages
);
956 * Writes data to the object referenced by handle.
958 * On error, the contents of the buffer that were to be modified are undefined.
961 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
962 struct drm_file
*file_priv
)
964 struct drm_i915_gem_pwrite
*args
= data
;
965 struct drm_gem_object
*obj
;
966 struct drm_i915_gem_object
*obj_priv
;
969 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
972 obj_priv
= obj
->driver_private
;
974 /* Bounds check destination.
976 * XXX: This could use review for overflow issues...
978 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
979 args
->offset
+ args
->size
> obj
->size
) {
980 drm_gem_object_unreference(obj
);
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
990 if (obj_priv
->phys_obj
)
991 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
992 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
993 dev
->gtt_total
!= 0) {
994 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
995 if (ret
== -EFAULT
) {
996 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
999 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
1000 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
1002 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
1003 if (ret
== -EFAULT
) {
1004 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1011 DRM_INFO("pwrite failed %d\n", ret
);
1014 drm_gem_object_unreference(obj
);
1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
1024 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1025 struct drm_file
*file_priv
)
1027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1028 struct drm_i915_gem_set_domain
*args
= data
;
1029 struct drm_gem_object
*obj
;
1030 struct drm_i915_gem_object
*obj_priv
;
1031 uint32_t read_domains
= args
->read_domains
;
1032 uint32_t write_domain
= args
->write_domain
;
1035 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1038 /* Only handle setting domains to types used by the CPU. */
1039 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1042 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1048 if (write_domain
!= 0 && read_domains
!= write_domain
)
1051 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1054 obj_priv
= obj
->driver_private
;
1056 mutex_lock(&dev
->struct_mutex
);
1058 intel_mark_busy(dev
, obj
);
1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1062 obj
, obj
->size
, read_domains
, write_domain
);
1064 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1065 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1067 /* Update the LRU on the fence for the CPU access that's
1070 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1071 list_move_tail(&obj_priv
->fence_list
,
1072 &dev_priv
->mm
.fence_list
);
1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1082 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1085 drm_gem_object_unreference(obj
);
1086 mutex_unlock(&dev
->struct_mutex
);
1091 * Called when user space has done writes to this buffer
1094 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1095 struct drm_file
*file_priv
)
1097 struct drm_i915_gem_sw_finish
*args
= data
;
1098 struct drm_gem_object
*obj
;
1099 struct drm_i915_gem_object
*obj_priv
;
1102 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1105 mutex_lock(&dev
->struct_mutex
);
1106 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1108 mutex_unlock(&dev
->struct_mutex
);
1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1114 __func__
, args
->handle
, obj
, obj
->size
);
1116 obj_priv
= obj
->driver_private
;
1118 /* Pinned buffers may be scanout, so flush the cache */
1119 if (obj_priv
->pin_count
)
1120 i915_gem_object_flush_cpu_write_domain(obj
);
1122 drm_gem_object_unreference(obj
);
1123 mutex_unlock(&dev
->struct_mutex
);
1128 * Maps the contents of an object, returning the address it is mapped
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1135 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1136 struct drm_file
*file_priv
)
1138 struct drm_i915_gem_mmap
*args
= data
;
1139 struct drm_gem_object
*obj
;
1143 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1146 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1150 offset
= args
->offset
;
1152 down_write(¤t
->mm
->mmap_sem
);
1153 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1154 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1156 up_write(¤t
->mm
->mmap_sem
);
1157 mutex_lock(&dev
->struct_mutex
);
1158 drm_gem_object_unreference(obj
);
1159 mutex_unlock(&dev
->struct_mutex
);
1160 if (IS_ERR((void *)addr
))
1163 args
->addr_ptr
= (uint64_t) addr
;
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1184 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1186 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1187 struct drm_device
*dev
= obj
->dev
;
1188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1189 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1190 pgoff_t page_offset
;
1193 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev
->struct_mutex
);
1201 if (!obj_priv
->gtt_space
) {
1202 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1206 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1208 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1213 /* Need a new fence register? */
1214 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1215 ret
= i915_gem_object_get_fence_reg(obj
);
1220 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1223 /* Finally, remap it using the new GTT offset */
1224 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1226 mutex_unlock(&dev
->struct_mutex
);
1231 return VM_FAULT_NOPAGE
;
1234 return VM_FAULT_OOM
;
1236 return VM_FAULT_SIGBUS
;
1241 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1242 * @obj: obj in question
1244 * GEM memory mapping works by handing back to userspace a fake mmap offset
1245 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1246 * up the object based on the offset and sets up the various memory mapping
1249 * This routine allocates and attaches a fake offset for @obj.
1252 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1254 struct drm_device
*dev
= obj
->dev
;
1255 struct drm_gem_mm
*mm
= dev
->mm_private
;
1256 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1257 struct drm_map_list
*list
;
1258 struct drm_local_map
*map
;
1261 /* Set the object up for mmap'ing */
1262 list
= &obj
->map_list
;
1263 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1268 map
->type
= _DRM_GEM
;
1269 map
->size
= obj
->size
;
1272 /* Get a DRM GEM mmap offset allocated... */
1273 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1274 obj
->size
/ PAGE_SIZE
, 0, 0);
1275 if (!list
->file_offset_node
) {
1276 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1281 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1282 obj
->size
/ PAGE_SIZE
, 0);
1283 if (!list
->file_offset_node
) {
1288 list
->hash
.key
= list
->file_offset_node
->start
;
1289 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1290 DRM_ERROR("failed to add to map hash\n");
1294 /* By now we should be all set, any drm_mmap request on the offset
1295 * below will get to our mmap & fault handler */
1296 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1301 drm_mm_put_block(list
->file_offset_node
);
1309 * i915_gem_release_mmap - remove physical page mappings
1310 * @obj: obj in question
1312 * Preserve the reservation of the mmaping with the DRM core code, but
1313 * relinquish ownership of the pages back to the system.
1315 * It is vital that we remove the page mapping if we have mapped a tiled
1316 * object through the GTT and then lose the fence register due to
1317 * resource pressure. Similarly if the object has been moved out of the
1318 * aperture, than pages mapped into userspace must be revoked. Removing the
1319 * mapping will then trigger a page fault on the next user access, allowing
1320 * fixup by i915_gem_fault().
1323 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1325 struct drm_device
*dev
= obj
->dev
;
1326 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1328 if (dev
->dev_mapping
)
1329 unmap_mapping_range(dev
->dev_mapping
,
1330 obj_priv
->mmap_offset
, obj
->size
, 1);
1334 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1336 struct drm_device
*dev
= obj
->dev
;
1337 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1338 struct drm_gem_mm
*mm
= dev
->mm_private
;
1339 struct drm_map_list
*list
;
1341 list
= &obj
->map_list
;
1342 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1344 if (list
->file_offset_node
) {
1345 drm_mm_put_block(list
->file_offset_node
);
1346 list
->file_offset_node
= NULL
;
1354 obj_priv
->mmap_offset
= 0;
1358 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1359 * @obj: object to check
1361 * Return the required GTT alignment for an object, taking into account
1362 * potential fence register mapping if needed.
1365 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1367 struct drm_device
*dev
= obj
->dev
;
1368 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1372 * Minimum alignment is 4k (GTT page size), but might be greater
1373 * if a fence register is needed for the object.
1375 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1379 * Previous chips need to be aligned to the size of the smallest
1380 * fence register that can contain the object.
1387 for (i
= start
; i
< obj
->size
; i
<<= 1)
1394 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1396 * @data: GTT mapping ioctl data
1397 * @file_priv: GEM object info
1399 * Simply returns the fake offset to userspace so it can mmap it.
1400 * The mmap call will end up in drm_gem_mmap(), which will set things
1401 * up so we can get faults in the handler above.
1403 * The fault handler will take care of binding the object into the GTT
1404 * (since it may have been evicted to make room for something), allocating
1405 * a fence register, and mapping the appropriate aperture address into
1409 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1410 struct drm_file
*file_priv
)
1412 struct drm_i915_gem_mmap_gtt
*args
= data
;
1413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1414 struct drm_gem_object
*obj
;
1415 struct drm_i915_gem_object
*obj_priv
;
1418 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1421 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1425 mutex_lock(&dev
->struct_mutex
);
1427 obj_priv
= obj
->driver_private
;
1429 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1430 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1431 drm_gem_object_unreference(obj
);
1432 mutex_unlock(&dev
->struct_mutex
);
1437 if (!obj_priv
->mmap_offset
) {
1438 ret
= i915_gem_create_mmap_offset(obj
);
1440 drm_gem_object_unreference(obj
);
1441 mutex_unlock(&dev
->struct_mutex
);
1446 args
->offset
= obj_priv
->mmap_offset
;
1449 * Pull it into the GTT so that we have a page list (makes the
1450 * initial fault faster and any subsequent flushing possible).
1452 if (!obj_priv
->agp_mem
) {
1453 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1455 drm_gem_object_unreference(obj
);
1456 mutex_unlock(&dev
->struct_mutex
);
1459 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1462 drm_gem_object_unreference(obj
);
1463 mutex_unlock(&dev
->struct_mutex
);
1469 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1471 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1472 int page_count
= obj
->size
/ PAGE_SIZE
;
1475 BUG_ON(obj_priv
->pages_refcount
== 0);
1476 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1478 if (--obj_priv
->pages_refcount
!= 0)
1481 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1482 i915_gem_object_save_bit_17_swizzle(obj
);
1484 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1485 obj_priv
->dirty
= 0;
1487 for (i
= 0; i
< page_count
; i
++) {
1488 if (obj_priv
->pages
[i
] == NULL
)
1491 if (obj_priv
->dirty
)
1492 set_page_dirty(obj_priv
->pages
[i
]);
1494 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1495 mark_page_accessed(obj_priv
->pages
[i
]);
1497 page_cache_release(obj_priv
->pages
[i
]);
1499 obj_priv
->dirty
= 0;
1501 drm_free_large(obj_priv
->pages
);
1502 obj_priv
->pages
= NULL
;
1506 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1508 struct drm_device
*dev
= obj
->dev
;
1509 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1510 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1512 /* Add a reference if we're newly entering the active list. */
1513 if (!obj_priv
->active
) {
1514 drm_gem_object_reference(obj
);
1515 obj_priv
->active
= 1;
1517 /* Move from whatever list we were on to the tail of execution. */
1518 spin_lock(&dev_priv
->mm
.active_list_lock
);
1519 list_move_tail(&obj_priv
->list
,
1520 &dev_priv
->mm
.active_list
);
1521 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1522 obj_priv
->last_rendering_seqno
= seqno
;
1526 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1528 struct drm_device
*dev
= obj
->dev
;
1529 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1530 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1532 BUG_ON(!obj_priv
->active
);
1533 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1534 obj_priv
->last_rendering_seqno
= 0;
1537 /* Immediately discard the backing storage */
1539 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1541 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1542 struct inode
*inode
;
1544 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1545 if (inode
->i_op
->truncate
)
1546 inode
->i_op
->truncate (inode
);
1548 obj_priv
->madv
= __I915_MADV_PURGED
;
1552 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1554 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1558 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1560 struct drm_device
*dev
= obj
->dev
;
1561 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1562 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1564 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1565 if (obj_priv
->pin_count
!= 0)
1566 list_del_init(&obj_priv
->list
);
1568 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1570 obj_priv
->last_rendering_seqno
= 0;
1571 if (obj_priv
->active
) {
1572 obj_priv
->active
= 0;
1573 drm_gem_object_unreference(obj
);
1575 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1579 * Creates a new sequence number, emitting a write of it to the status page
1580 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1582 * Must be called with struct_lock held.
1584 * Returned sequence numbers are nonzero on success.
1587 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1588 uint32_t flush_domains
)
1590 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1591 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1592 struct drm_i915_gem_request
*request
;
1597 if (file_priv
!= NULL
)
1598 i915_file_priv
= file_priv
->driver_priv
;
1600 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1601 if (request
== NULL
)
1604 /* Grab the seqno we're going to make this request be, and bump the
1605 * next (skipping 0 so it can be the reserved no-seqno value).
1607 seqno
= dev_priv
->mm
.next_gem_seqno
;
1608 dev_priv
->mm
.next_gem_seqno
++;
1609 if (dev_priv
->mm
.next_gem_seqno
== 0)
1610 dev_priv
->mm
.next_gem_seqno
++;
1613 OUT_RING(MI_STORE_DWORD_INDEX
);
1614 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1617 OUT_RING(MI_USER_INTERRUPT
);
1620 DRM_DEBUG_DRIVER("%d\n", seqno
);
1622 request
->seqno
= seqno
;
1623 request
->emitted_jiffies
= jiffies
;
1624 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1625 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1626 if (i915_file_priv
) {
1627 list_add_tail(&request
->client_list
,
1628 &i915_file_priv
->mm
.request_list
);
1630 INIT_LIST_HEAD(&request
->client_list
);
1633 /* Associate any objects on the flushing list matching the write
1634 * domain we're flushing with our flush.
1636 if (flush_domains
!= 0) {
1637 struct drm_i915_gem_object
*obj_priv
, *next
;
1639 list_for_each_entry_safe(obj_priv
, next
,
1640 &dev_priv
->mm
.flushing_list
, list
) {
1641 struct drm_gem_object
*obj
= obj_priv
->obj
;
1643 if ((obj
->write_domain
& flush_domains
) ==
1644 obj
->write_domain
) {
1645 uint32_t old_write_domain
= obj
->write_domain
;
1647 obj
->write_domain
= 0;
1648 i915_gem_object_move_to_active(obj
, seqno
);
1650 trace_i915_gem_object_change_domain(obj
,
1658 if (!dev_priv
->mm
.suspended
) {
1659 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1661 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1667 * Command execution barrier
1669 * Ensures that all commands in the ring are finished
1670 * before signalling the CPU
1673 i915_retire_commands(struct drm_device
*dev
)
1675 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1676 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1677 uint32_t flush_domains
= 0;
1680 /* The sampler always gets flushed on i965 (sigh) */
1682 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1685 OUT_RING(0); /* noop */
1687 return flush_domains
;
1691 * Moves buffers associated only with the given active seqno from the active
1692 * to inactive list, potentially freeing them.
1695 i915_gem_retire_request(struct drm_device
*dev
,
1696 struct drm_i915_gem_request
*request
)
1698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1700 trace_i915_gem_request_retire(dev
, request
->seqno
);
1702 /* Move any buffers on the active list that are no longer referenced
1703 * by the ringbuffer to the flushing/inactive lists as appropriate.
1705 spin_lock(&dev_priv
->mm
.active_list_lock
);
1706 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1707 struct drm_gem_object
*obj
;
1708 struct drm_i915_gem_object
*obj_priv
;
1710 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1711 struct drm_i915_gem_object
,
1713 obj
= obj_priv
->obj
;
1715 /* If the seqno being retired doesn't match the oldest in the
1716 * list, then the oldest in the list must still be newer than
1719 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1723 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1724 __func__
, request
->seqno
, obj
);
1727 if (obj
->write_domain
!= 0)
1728 i915_gem_object_move_to_flushing(obj
);
1730 /* Take a reference on the object so it won't be
1731 * freed while the spinlock is held. The list
1732 * protection for this spinlock is safe when breaking
1733 * the lock like this since the next thing we do
1734 * is just get the head of the list again.
1736 drm_gem_object_reference(obj
);
1737 i915_gem_object_move_to_inactive(obj
);
1738 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1739 drm_gem_object_unreference(obj
);
1740 spin_lock(&dev_priv
->mm
.active_list_lock
);
1744 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1748 * Returns true if seq1 is later than seq2.
1751 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1753 return (int32_t)(seq1
- seq2
) >= 0;
1757 i915_get_gem_seqno(struct drm_device
*dev
)
1759 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1761 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1765 * This function clears the request list as sequence numbers are passed.
1768 i915_gem_retire_requests(struct drm_device
*dev
)
1770 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1773 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1776 seqno
= i915_get_gem_seqno(dev
);
1778 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1779 struct drm_i915_gem_request
*request
;
1780 uint32_t retiring_seqno
;
1782 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1783 struct drm_i915_gem_request
,
1785 retiring_seqno
= request
->seqno
;
1787 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1788 atomic_read(&dev_priv
->mm
.wedged
)) {
1789 i915_gem_retire_request(dev
, request
);
1791 list_del(&request
->list
);
1792 list_del(&request
->client_list
);
1798 if (unlikely (dev_priv
->trace_irq_seqno
&&
1799 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1800 i915_user_irq_put(dev
);
1801 dev_priv
->trace_irq_seqno
= 0;
1806 i915_gem_retire_work_handler(struct work_struct
*work
)
1808 drm_i915_private_t
*dev_priv
;
1809 struct drm_device
*dev
;
1811 dev_priv
= container_of(work
, drm_i915_private_t
,
1812 mm
.retire_work
.work
);
1813 dev
= dev_priv
->dev
;
1815 mutex_lock(&dev
->struct_mutex
);
1816 i915_gem_retire_requests(dev
);
1817 if (!dev_priv
->mm
.suspended
&&
1818 !list_empty(&dev_priv
->mm
.request_list
))
1819 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1820 mutex_unlock(&dev
->struct_mutex
);
1824 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1826 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1832 if (atomic_read(&dev_priv
->mm
.wedged
))
1835 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1837 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1839 ier
= I915_READ(IER
);
1841 DRM_ERROR("something (likely vbetool) disabled "
1842 "interrupts, re-enabling\n");
1843 i915_driver_irq_preinstall(dev
);
1844 i915_driver_irq_postinstall(dev
);
1847 trace_i915_gem_request_wait_begin(dev
, seqno
);
1849 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1850 i915_user_irq_get(dev
);
1852 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1853 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1854 atomic_read(&dev_priv
->mm
.wedged
));
1856 wait_event(dev_priv
->irq_queue
,
1857 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1858 atomic_read(&dev_priv
->mm
.wedged
));
1860 i915_user_irq_put(dev
);
1861 dev_priv
->mm
.waiting_gem_seqno
= 0;
1863 trace_i915_gem_request_wait_end(dev
, seqno
);
1865 if (atomic_read(&dev_priv
->mm
.wedged
))
1868 if (ret
&& ret
!= -ERESTARTSYS
)
1869 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1870 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1872 /* Directly dispatch request retiring. While we have the work queue
1873 * to handle this, the waiter on a request often wants an associated
1874 * buffer to have made it to the inactive list, and we would need
1875 * a separate wait queue to handle that.
1878 i915_gem_retire_requests(dev
);
1884 * Waits for a sequence number to be signaled, and cleans up the
1885 * request and object lists appropriately for that event.
1888 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1890 return i915_do_wait_request(dev
, seqno
, 1);
1894 i915_gem_flush(struct drm_device
*dev
,
1895 uint32_t invalidate_domains
,
1896 uint32_t flush_domains
)
1898 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1903 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1904 invalidate_domains
, flush_domains
);
1906 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1907 invalidate_domains
, flush_domains
);
1909 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1910 drm_agp_chipset_flush(dev
);
1912 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1914 * read/write caches:
1916 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1917 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1918 * also flushed at 2d versus 3d pipeline switches.
1922 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1923 * MI_READ_FLUSH is set, and is always flushed on 965.
1925 * I915_GEM_DOMAIN_COMMAND may not exist?
1927 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1928 * invalidated when MI_EXE_FLUSH is set.
1930 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1931 * invalidated with every MI_FLUSH.
1935 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1936 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1937 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1938 * are flushed at any MI_FLUSH.
1941 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1942 if ((invalidate_domains
|flush_domains
) &
1943 I915_GEM_DOMAIN_RENDER
)
1944 cmd
&= ~MI_NO_WRITE_FLUSH
;
1945 if (!IS_I965G(dev
)) {
1947 * On the 965, the sampler cache always gets flushed
1948 * and this bit is reserved.
1950 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1951 cmd
|= MI_READ_FLUSH
;
1953 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1954 cmd
|= MI_EXE_FLUSH
;
1957 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1967 * Ensures that all rendering to the object has completed and the object is
1968 * safe to unbind from the GTT or access from the CPU.
1971 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1973 struct drm_device
*dev
= obj
->dev
;
1974 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1977 /* This function only exists to support waiting for existing rendering,
1978 * not for emitting required flushes.
1980 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1982 /* If there is rendering queued on the buffer being evicted, wait for
1985 if (obj_priv
->active
) {
1987 DRM_INFO("%s: object %p wait for seqno %08x\n",
1988 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1990 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1999 * Unbinds an object from the GTT aperture.
2002 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2004 struct drm_device
*dev
= obj
->dev
;
2005 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2009 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
2010 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
2012 if (obj_priv
->gtt_space
== NULL
)
2015 if (obj_priv
->pin_count
!= 0) {
2016 DRM_ERROR("Attempting to unbind pinned buffer\n");
2020 /* blow away mappings if mapped through GTT */
2021 i915_gem_release_mmap(obj
);
2023 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2024 i915_gem_clear_fence_reg(obj
);
2026 /* Move the object to the CPU domain to ensure that
2027 * any possible CPU writes while it's not in the GTT
2028 * are flushed when we go to remap it. This will
2029 * also ensure that all pending GPU writes are finished
2032 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2034 if (ret
!= -ERESTARTSYS
)
2035 DRM_ERROR("set_domain failed: %d\n", ret
);
2039 BUG_ON(obj_priv
->active
);
2041 if (obj_priv
->agp_mem
!= NULL
) {
2042 drm_unbind_agp(obj_priv
->agp_mem
);
2043 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2044 obj_priv
->agp_mem
= NULL
;
2047 i915_gem_object_put_pages(obj
);
2048 BUG_ON(obj_priv
->pages_refcount
);
2050 if (obj_priv
->gtt_space
) {
2051 atomic_dec(&dev
->gtt_count
);
2052 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2054 drm_mm_put_block(obj_priv
->gtt_space
);
2055 obj_priv
->gtt_space
= NULL
;
2058 /* Remove ourselves from the LRU list if present. */
2059 if (!list_empty(&obj_priv
->list
))
2060 list_del_init(&obj_priv
->list
);
2062 if (i915_gem_object_is_purgeable(obj_priv
))
2063 i915_gem_object_truncate(obj
);
2065 trace_i915_gem_object_unbind(obj
);
2070 static struct drm_gem_object
*
2071 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2073 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2074 struct drm_i915_gem_object
*obj_priv
;
2075 struct drm_gem_object
*best
= NULL
;
2076 struct drm_gem_object
*first
= NULL
;
2078 /* Try to find the smallest clean object */
2079 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2080 struct drm_gem_object
*obj
= obj_priv
->obj
;
2081 if (obj
->size
>= min_size
) {
2082 if ((!obj_priv
->dirty
||
2083 i915_gem_object_is_purgeable(obj_priv
)) &&
2084 (!best
|| obj
->size
< best
->size
)) {
2086 if (best
->size
== min_size
)
2094 return best
? best
: first
;
2098 i915_gem_evict_everything(struct drm_device
*dev
)
2100 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2105 spin_lock(&dev_priv
->mm
.active_list_lock
);
2106 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2107 list_empty(&dev_priv
->mm
.flushing_list
) &&
2108 list_empty(&dev_priv
->mm
.active_list
));
2109 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2114 /* Flush everything (on to the inactive lists) and evict */
2115 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2116 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2120 ret
= i915_wait_request(dev
, seqno
);
2124 ret
= i915_gem_evict_from_inactive_list(dev
);
2128 spin_lock(&dev_priv
->mm
.active_list_lock
);
2129 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2130 list_empty(&dev_priv
->mm
.flushing_list
) &&
2131 list_empty(&dev_priv
->mm
.active_list
));
2132 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2133 BUG_ON(!lists_empty
);
2139 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2141 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2142 struct drm_gem_object
*obj
;
2146 i915_gem_retire_requests(dev
);
2148 /* If there's an inactive buffer available now, grab it
2151 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2153 struct drm_i915_gem_object
*obj_priv
;
2156 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2158 obj_priv
= obj
->driver_private
;
2159 BUG_ON(obj_priv
->pin_count
!= 0);
2160 BUG_ON(obj_priv
->active
);
2162 /* Wait on the rendering and unbind the buffer. */
2163 return i915_gem_object_unbind(obj
);
2166 /* If we didn't get anything, but the ring is still processing
2167 * things, wait for the next to finish and hopefully leave us
2168 * a buffer to evict.
2170 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2171 struct drm_i915_gem_request
*request
;
2173 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2174 struct drm_i915_gem_request
,
2177 ret
= i915_wait_request(dev
, request
->seqno
);
2184 /* If we didn't have anything on the request list but there
2185 * are buffers awaiting a flush, emit one and try again.
2186 * When we wait on it, those buffers waiting for that flush
2187 * will get moved to inactive.
2189 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2190 struct drm_i915_gem_object
*obj_priv
;
2192 /* Find an object that we can immediately reuse */
2193 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2194 obj
= obj_priv
->obj
;
2195 if (obj
->size
>= min_size
)
2207 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2211 ret
= i915_wait_request(dev
, seqno
);
2219 /* If we didn't do any of the above, there's no single buffer
2220 * large enough to swap out for the new one, so just evict
2221 * everything and start again. (This should be rare.)
2223 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2224 return i915_gem_evict_from_inactive_list(dev
);
2226 return i915_gem_evict_everything(dev
);
2231 i915_gem_object_get_pages(struct drm_gem_object
*obj
)
2233 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2235 struct address_space
*mapping
;
2236 struct inode
*inode
;
2240 if (obj_priv
->pages_refcount
++ != 0)
2243 /* Get the list of pages out of our struct file. They'll be pinned
2244 * at this point until we release them.
2246 page_count
= obj
->size
/ PAGE_SIZE
;
2247 BUG_ON(obj_priv
->pages
!= NULL
);
2248 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2249 if (obj_priv
->pages
== NULL
) {
2250 obj_priv
->pages_refcount
--;
2254 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2255 mapping
= inode
->i_mapping
;
2256 for (i
= 0; i
< page_count
; i
++) {
2257 page
= read_mapping_page(mapping
, i
, NULL
);
2259 ret
= PTR_ERR(page
);
2260 i915_gem_object_put_pages(obj
);
2263 obj_priv
->pages
[i
] = page
;
2266 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2267 i915_gem_object_do_bit_17_swizzle(obj
);
2272 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2274 struct drm_gem_object
*obj
= reg
->obj
;
2275 struct drm_device
*dev
= obj
->dev
;
2276 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2277 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2278 int regnum
= obj_priv
->fence_reg
;
2281 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2283 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2284 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2285 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2286 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2287 val
|= I965_FENCE_REG_VALID
;
2289 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2292 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2294 struct drm_gem_object
*obj
= reg
->obj
;
2295 struct drm_device
*dev
= obj
->dev
;
2296 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2297 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2298 int regnum
= obj_priv
->fence_reg
;
2300 uint32_t fence_reg
, val
;
2303 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2304 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2305 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2306 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2310 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2311 HAS_128_BYTE_Y_TILING(dev
))
2316 /* Note: pitch better be a power of two tile widths */
2317 pitch_val
= obj_priv
->stride
/ tile_width
;
2318 pitch_val
= ffs(pitch_val
) - 1;
2320 val
= obj_priv
->gtt_offset
;
2321 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2322 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2323 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2324 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2325 val
|= I830_FENCE_REG_VALID
;
2328 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2330 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2331 I915_WRITE(fence_reg
, val
);
2334 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2336 struct drm_gem_object
*obj
= reg
->obj
;
2337 struct drm_device
*dev
= obj
->dev
;
2338 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2339 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2340 int regnum
= obj_priv
->fence_reg
;
2343 uint32_t fence_size_bits
;
2345 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2346 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2347 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2348 __func__
, obj_priv
->gtt_offset
);
2352 pitch_val
= obj_priv
->stride
/ 128;
2353 pitch_val
= ffs(pitch_val
) - 1;
2354 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2356 val
= obj_priv
->gtt_offset
;
2357 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2358 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2359 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2360 WARN_ON(fence_size_bits
& ~0x00000f00);
2361 val
|= fence_size_bits
;
2362 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2363 val
|= I830_FENCE_REG_VALID
;
2365 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2369 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2370 * @obj: object to map through a fence reg
2372 * When mapping objects through the GTT, userspace wants to be able to write
2373 * to them without having to worry about swizzling if the object is tiled.
2375 * This function walks the fence regs looking for a free one for @obj,
2376 * stealing one if it can't find any.
2378 * It then sets up the reg based on the object's properties: address, pitch
2379 * and tiling format.
2382 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2384 struct drm_device
*dev
= obj
->dev
;
2385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2386 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2387 struct drm_i915_fence_reg
*reg
= NULL
;
2388 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2391 /* Just update our place in the LRU if our fence is getting used. */
2392 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2393 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2397 switch (obj_priv
->tiling_mode
) {
2398 case I915_TILING_NONE
:
2399 WARN(1, "allocating a fence for non-tiled object?\n");
2402 if (!obj_priv
->stride
)
2404 WARN((obj_priv
->stride
& (512 - 1)),
2405 "object 0x%08x is X tiled but has non-512B pitch\n",
2406 obj_priv
->gtt_offset
);
2409 if (!obj_priv
->stride
)
2411 WARN((obj_priv
->stride
& (128 - 1)),
2412 "object 0x%08x is Y tiled but has non-128B pitch\n",
2413 obj_priv
->gtt_offset
);
2417 /* First try to find a free reg */
2419 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2420 reg
= &dev_priv
->fence_regs
[i
];
2424 old_obj_priv
= reg
->obj
->driver_private
;
2425 if (!old_obj_priv
->pin_count
)
2429 /* None available, try to steal one or wait for a user to finish */
2430 if (i
== dev_priv
->num_fence_regs
) {
2431 struct drm_gem_object
*old_obj
= NULL
;
2436 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2438 old_obj
= old_obj_priv
->obj
;
2440 if (old_obj_priv
->pin_count
)
2443 /* Take a reference, as otherwise the wait_rendering
2444 * below may cause the object to get freed out from
2447 drm_gem_object_reference(old_obj
);
2449 /* i915 uses fences for GPU access to tiled buffers */
2450 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2453 /* This brings the object to the head of the LRU if it
2454 * had been written to. The only way this should
2455 * result in us waiting longer than the expected
2456 * optimal amount of time is if there was a
2457 * fence-using buffer later that was read-only.
2459 i915_gem_object_flush_gpu_write_domain(old_obj
);
2460 ret
= i915_gem_object_wait_rendering(old_obj
);
2462 drm_gem_object_unreference(old_obj
);
2470 * Zap this virtual mapping so we can set up a fence again
2471 * for this object next time we need it.
2473 i915_gem_release_mmap(old_obj
);
2475 i
= old_obj_priv
->fence_reg
;
2476 reg
= &dev_priv
->fence_regs
[i
];
2478 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2479 list_del_init(&old_obj_priv
->fence_list
);
2481 drm_gem_object_unreference(old_obj
);
2484 obj_priv
->fence_reg
= i
;
2485 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2490 i965_write_fence_reg(reg
);
2491 else if (IS_I9XX(dev
))
2492 i915_write_fence_reg(reg
);
2494 i830_write_fence_reg(reg
);
2496 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2502 * i915_gem_clear_fence_reg - clear out fence register info
2503 * @obj: object to clear
2505 * Zeroes out the fence register itself and clears out the associated
2506 * data structures in dev_priv and obj_priv.
2509 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2511 struct drm_device
*dev
= obj
->dev
;
2512 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2513 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2516 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2520 if (obj_priv
->fence_reg
< 8)
2521 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2523 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2526 I915_WRITE(fence_reg
, 0);
2529 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2530 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2531 list_del_init(&obj_priv
->fence_list
);
2535 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2536 * to the buffer to finish, and then resets the fence register.
2537 * @obj: tiled object holding a fence register.
2539 * Zeroes out the fence register itself and clears out the associated
2540 * data structures in dev_priv and obj_priv.
2543 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2545 struct drm_device
*dev
= obj
->dev
;
2546 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2548 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2551 /* On the i915, GPU access to tiled buffers is via a fence,
2552 * therefore we must wait for any outstanding access to complete
2553 * before clearing the fence.
2555 if (!IS_I965G(dev
)) {
2558 i915_gem_object_flush_gpu_write_domain(obj
);
2559 i915_gem_object_flush_gtt_write_domain(obj
);
2560 ret
= i915_gem_object_wait_rendering(obj
);
2565 i915_gem_clear_fence_reg (obj
);
2571 * Finds free space in the GTT aperture and binds the object there.
2574 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2576 struct drm_device
*dev
= obj
->dev
;
2577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2578 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2579 struct drm_mm_node
*free_space
;
2580 bool retry_alloc
= false;
2583 if (dev_priv
->mm
.suspended
)
2586 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2587 DRM_ERROR("Attempting to bind a purgeable object\n");
2592 alignment
= i915_gem_get_gtt_alignment(obj
);
2593 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2594 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2599 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2600 obj
->size
, alignment
, 0);
2601 if (free_space
!= NULL
) {
2602 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2604 if (obj_priv
->gtt_space
!= NULL
) {
2605 obj_priv
->gtt_space
->private = obj
;
2606 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2609 if (obj_priv
->gtt_space
== NULL
) {
2610 /* If the gtt is empty and we're still having trouble
2611 * fitting our object in, we're out of memory.
2614 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2616 ret
= i915_gem_evict_something(dev
, obj
->size
);
2624 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2625 obj
->size
, obj_priv
->gtt_offset
);
2628 i915_gem_object_set_page_gfp_mask (obj
,
2629 i915_gem_object_get_page_gfp_mask (obj
) & ~__GFP_NORETRY
);
2631 ret
= i915_gem_object_get_pages(obj
);
2633 i915_gem_object_set_page_gfp_mask (obj
,
2634 i915_gem_object_get_page_gfp_mask (obj
) | __GFP_NORETRY
);
2637 drm_mm_put_block(obj_priv
->gtt_space
);
2638 obj_priv
->gtt_space
= NULL
;
2640 if (ret
== -ENOMEM
) {
2641 /* first try to clear up some space from the GTT */
2642 ret
= i915_gem_evict_something(dev
, obj
->size
);
2644 /* now try to shrink everyone else */
2645 if (! retry_alloc
) {
2659 /* Create an AGP memory structure pointing at our pages, and bind it
2662 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2664 obj
->size
>> PAGE_SHIFT
,
2665 obj_priv
->gtt_offset
,
2666 obj_priv
->agp_type
);
2667 if (obj_priv
->agp_mem
== NULL
) {
2668 i915_gem_object_put_pages(obj
);
2669 drm_mm_put_block(obj_priv
->gtt_space
);
2670 obj_priv
->gtt_space
= NULL
;
2672 ret
= i915_gem_evict_something(dev
, obj
->size
);
2678 atomic_inc(&dev
->gtt_count
);
2679 atomic_add(obj
->size
, &dev
->gtt_memory
);
2681 /* Assert that the object is not currently in any GPU domain. As it
2682 * wasn't in the GTT, there shouldn't be any way it could have been in
2685 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2686 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2688 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2694 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2696 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2698 /* If we don't have a page list set up, then we're not pinned
2699 * to GPU, and we can ignore the cache flush because it'll happen
2700 * again at bind time.
2702 if (obj_priv
->pages
== NULL
)
2705 trace_i915_gem_object_clflush(obj
);
2707 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2710 /** Flushes any GPU write domain for the object if it's dirty. */
2712 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2714 struct drm_device
*dev
= obj
->dev
;
2716 uint32_t old_write_domain
;
2718 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2721 /* Queue the GPU write cache flushing we need. */
2722 old_write_domain
= obj
->write_domain
;
2723 i915_gem_flush(dev
, 0, obj
->write_domain
);
2724 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2725 obj
->write_domain
= 0;
2726 i915_gem_object_move_to_active(obj
, seqno
);
2728 trace_i915_gem_object_change_domain(obj
,
2733 /** Flushes the GTT write domain for the object if it's dirty. */
2735 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2737 uint32_t old_write_domain
;
2739 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2742 /* No actual flushing is required for the GTT write domain. Writes
2743 * to it immediately go to main memory as far as we know, so there's
2744 * no chipset flush. It also doesn't land in render cache.
2746 old_write_domain
= obj
->write_domain
;
2747 obj
->write_domain
= 0;
2749 trace_i915_gem_object_change_domain(obj
,
2754 /** Flushes the CPU write domain for the object if it's dirty. */
2756 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2758 struct drm_device
*dev
= obj
->dev
;
2759 uint32_t old_write_domain
;
2761 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2764 i915_gem_clflush_object(obj
);
2765 drm_agp_chipset_flush(dev
);
2766 old_write_domain
= obj
->write_domain
;
2767 obj
->write_domain
= 0;
2769 trace_i915_gem_object_change_domain(obj
,
2775 * Moves a single object to the GTT read, and possibly write domain.
2777 * This function returns when the move is complete, including waiting on
2781 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2783 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2784 uint32_t old_write_domain
, old_read_domains
;
2787 /* Not valid to be called on unbound objects. */
2788 if (obj_priv
->gtt_space
== NULL
)
2791 i915_gem_object_flush_gpu_write_domain(obj
);
2792 /* Wait on any GPU rendering and flushing to occur. */
2793 ret
= i915_gem_object_wait_rendering(obj
);
2797 old_write_domain
= obj
->write_domain
;
2798 old_read_domains
= obj
->read_domains
;
2800 /* If we're writing through the GTT domain, then CPU and GPU caches
2801 * will need to be invalidated at next use.
2804 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2806 i915_gem_object_flush_cpu_write_domain(obj
);
2808 /* It should now be out of any other write domains, and we can update
2809 * the domain values for our changes.
2811 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2812 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2814 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2815 obj_priv
->dirty
= 1;
2818 trace_i915_gem_object_change_domain(obj
,
2826 * Moves a single object to the CPU read, and possibly write domain.
2828 * This function returns when the move is complete, including waiting on
2832 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2834 uint32_t old_write_domain
, old_read_domains
;
2837 i915_gem_object_flush_gpu_write_domain(obj
);
2838 /* Wait on any GPU rendering and flushing to occur. */
2839 ret
= i915_gem_object_wait_rendering(obj
);
2843 i915_gem_object_flush_gtt_write_domain(obj
);
2845 /* If we have a partially-valid cache of the object in the CPU,
2846 * finish invalidating it and free the per-page flags.
2848 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2850 old_write_domain
= obj
->write_domain
;
2851 old_read_domains
= obj
->read_domains
;
2853 /* Flush the CPU cache if it's still invalid. */
2854 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2855 i915_gem_clflush_object(obj
);
2857 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2860 /* It should now be out of any other write domains, and we can update
2861 * the domain values for our changes.
2863 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2865 /* If we're writing through the CPU, then the GPU read domains will
2866 * need to be invalidated at next use.
2869 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2870 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2873 trace_i915_gem_object_change_domain(obj
,
2881 * Set the next domain for the specified object. This
2882 * may not actually perform the necessary flushing/invaliding though,
2883 * as that may want to be batched with other set_domain operations
2885 * This is (we hope) the only really tricky part of gem. The goal
2886 * is fairly simple -- track which caches hold bits of the object
2887 * and make sure they remain coherent. A few concrete examples may
2888 * help to explain how it works. For shorthand, we use the notation
2889 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2890 * a pair of read and write domain masks.
2892 * Case 1: the batch buffer
2898 * 5. Unmapped from GTT
2901 * Let's take these a step at a time
2904 * Pages allocated from the kernel may still have
2905 * cache contents, so we set them to (CPU, CPU) always.
2906 * 2. Written by CPU (using pwrite)
2907 * The pwrite function calls set_domain (CPU, CPU) and
2908 * this function does nothing (as nothing changes)
2910 * This function asserts that the object is not
2911 * currently in any GPU-based read or write domains
2913 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2914 * As write_domain is zero, this function adds in the
2915 * current read domains (CPU+COMMAND, 0).
2916 * flush_domains is set to CPU.
2917 * invalidate_domains is set to COMMAND
2918 * clflush is run to get data out of the CPU caches
2919 * then i915_dev_set_domain calls i915_gem_flush to
2920 * emit an MI_FLUSH and drm_agp_chipset_flush
2921 * 5. Unmapped from GTT
2922 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2923 * flush_domains and invalidate_domains end up both zero
2924 * so no flushing/invalidating happens
2928 * Case 2: The shared render buffer
2932 * 3. Read/written by GPU
2933 * 4. set_domain to (CPU,CPU)
2934 * 5. Read/written by CPU
2935 * 6. Read/written by GPU
2938 * Same as last example, (CPU, CPU)
2940 * Nothing changes (assertions find that it is not in the GPU)
2941 * 3. Read/written by GPU
2942 * execbuffer calls set_domain (RENDER, RENDER)
2943 * flush_domains gets CPU
2944 * invalidate_domains gets GPU
2946 * MI_FLUSH and drm_agp_chipset_flush
2947 * 4. set_domain (CPU, CPU)
2948 * flush_domains gets GPU
2949 * invalidate_domains gets CPU
2950 * wait_rendering (obj) to make sure all drawing is complete.
2951 * This will include an MI_FLUSH to get the data from GPU
2953 * clflush (obj) to invalidate the CPU cache
2954 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2955 * 5. Read/written by CPU
2956 * cache lines are loaded and dirtied
2957 * 6. Read written by GPU
2958 * Same as last GPU access
2960 * Case 3: The constant buffer
2965 * 4. Updated (written) by CPU again
2974 * flush_domains = CPU
2975 * invalidate_domains = RENDER
2978 * drm_agp_chipset_flush
2979 * 4. Updated (written) by CPU again
2981 * flush_domains = 0 (no previous write domain)
2982 * invalidate_domains = 0 (no new read domains)
2985 * flush_domains = CPU
2986 * invalidate_domains = RENDER
2989 * drm_agp_chipset_flush
2992 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2994 struct drm_device
*dev
= obj
->dev
;
2995 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2996 uint32_t invalidate_domains
= 0;
2997 uint32_t flush_domains
= 0;
2998 uint32_t old_read_domains
;
3000 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3001 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3003 intel_mark_busy(dev
, obj
);
3006 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3008 obj
->read_domains
, obj
->pending_read_domains
,
3009 obj
->write_domain
, obj
->pending_write_domain
);
3012 * If the object isn't moving to a new write domain,
3013 * let the object stay in multiple read domains
3015 if (obj
->pending_write_domain
== 0)
3016 obj
->pending_read_domains
|= obj
->read_domains
;
3018 obj_priv
->dirty
= 1;
3021 * Flush the current write domain if
3022 * the new read domains don't match. Invalidate
3023 * any read domains which differ from the old
3026 if (obj
->write_domain
&&
3027 obj
->write_domain
!= obj
->pending_read_domains
) {
3028 flush_domains
|= obj
->write_domain
;
3029 invalidate_domains
|=
3030 obj
->pending_read_domains
& ~obj
->write_domain
;
3033 * Invalidate any read caches which may have
3034 * stale data. That is, any new read domains.
3036 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3037 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3039 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3040 __func__
, flush_domains
, invalidate_domains
);
3042 i915_gem_clflush_object(obj
);
3045 old_read_domains
= obj
->read_domains
;
3047 /* The actual obj->write_domain will be updated with
3048 * pending_write_domain after we emit the accumulated flush for all
3049 * of our domain changes in execbuffers (which clears objects'
3050 * write_domains). So if we have a current write domain that we
3051 * aren't changing, set pending_write_domain to that.
3053 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3054 obj
->pending_write_domain
= obj
->write_domain
;
3055 obj
->read_domains
= obj
->pending_read_domains
;
3057 dev
->invalidate_domains
|= invalidate_domains
;
3058 dev
->flush_domains
|= flush_domains
;
3060 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3062 obj
->read_domains
, obj
->write_domain
,
3063 dev
->invalidate_domains
, dev
->flush_domains
);
3066 trace_i915_gem_object_change_domain(obj
,
3072 * Moves the object from a partially CPU read to a full one.
3074 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3075 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3078 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3080 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3082 if (!obj_priv
->page_cpu_valid
)
3085 /* If we're partially in the CPU read domain, finish moving it in.
3087 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3090 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3091 if (obj_priv
->page_cpu_valid
[i
])
3093 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3097 /* Free the page_cpu_valid mappings which are now stale, whether
3098 * or not we've got I915_GEM_DOMAIN_CPU.
3100 kfree(obj_priv
->page_cpu_valid
);
3101 obj_priv
->page_cpu_valid
= NULL
;
3105 * Set the CPU read domain on a range of the object.
3107 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3108 * not entirely valid. The page_cpu_valid member of the object flags which
3109 * pages have been flushed, and will be respected by
3110 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3111 * of the whole object.
3113 * This function returns when the move is complete, including waiting on
3117 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3118 uint64_t offset
, uint64_t size
)
3120 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3121 uint32_t old_read_domains
;
3124 if (offset
== 0 && size
== obj
->size
)
3125 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3127 i915_gem_object_flush_gpu_write_domain(obj
);
3128 /* Wait on any GPU rendering and flushing to occur. */
3129 ret
= i915_gem_object_wait_rendering(obj
);
3132 i915_gem_object_flush_gtt_write_domain(obj
);
3134 /* If we're already fully in the CPU read domain, we're done. */
3135 if (obj_priv
->page_cpu_valid
== NULL
&&
3136 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3139 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3140 * newly adding I915_GEM_DOMAIN_CPU
3142 if (obj_priv
->page_cpu_valid
== NULL
) {
3143 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3145 if (obj_priv
->page_cpu_valid
== NULL
)
3147 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3148 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3150 /* Flush the cache on any pages that are still invalid from the CPU's
3153 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3155 if (obj_priv
->page_cpu_valid
[i
])
3158 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3160 obj_priv
->page_cpu_valid
[i
] = 1;
3163 /* It should now be out of any other write domains, and we can update
3164 * the domain values for our changes.
3166 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3168 old_read_domains
= obj
->read_domains
;
3169 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3171 trace_i915_gem_object_change_domain(obj
,
3179 * Pin an object to the GTT and evaluate the relocations landing in it.
3182 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3183 struct drm_file
*file_priv
,
3184 struct drm_i915_gem_exec_object
*entry
,
3185 struct drm_i915_gem_relocation_entry
*relocs
)
3187 struct drm_device
*dev
= obj
->dev
;
3188 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3189 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3191 void __iomem
*reloc_page
;
3193 /* Choose the GTT offset for our buffer and put it there. */
3194 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3198 entry
->offset
= obj_priv
->gtt_offset
;
3200 /* Apply the relocations, using the GTT aperture to avoid cache
3201 * flushing requirements.
3203 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3204 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3205 struct drm_gem_object
*target_obj
;
3206 struct drm_i915_gem_object
*target_obj_priv
;
3207 uint32_t reloc_val
, reloc_offset
;
3208 uint32_t __iomem
*reloc_entry
;
3210 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3211 reloc
->target_handle
);
3212 if (target_obj
== NULL
) {
3213 i915_gem_object_unpin(obj
);
3216 target_obj_priv
= target_obj
->driver_private
;
3219 DRM_INFO("%s: obj %p offset %08x target %d "
3220 "read %08x write %08x gtt %08x "
3221 "presumed %08x delta %08x\n",
3224 (int) reloc
->offset
,
3225 (int) reloc
->target_handle
,
3226 (int) reloc
->read_domains
,
3227 (int) reloc
->write_domain
,
3228 (int) target_obj_priv
->gtt_offset
,
3229 (int) reloc
->presumed_offset
,
3233 /* The target buffer should have appeared before us in the
3234 * exec_object list, so it should have a GTT space bound by now.
3236 if (target_obj_priv
->gtt_space
== NULL
) {
3237 DRM_ERROR("No GTT space found for object %d\n",
3238 reloc
->target_handle
);
3239 drm_gem_object_unreference(target_obj
);
3240 i915_gem_object_unpin(obj
);
3244 /* Validate that the target is in a valid r/w GPU domain */
3245 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3246 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3247 DRM_ERROR("reloc with read/write CPU domains: "
3248 "obj %p target %d offset %d "
3249 "read %08x write %08x",
3250 obj
, reloc
->target_handle
,
3251 (int) reloc
->offset
,
3252 reloc
->read_domains
,
3253 reloc
->write_domain
);
3254 drm_gem_object_unreference(target_obj
);
3255 i915_gem_object_unpin(obj
);
3258 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3259 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3260 DRM_ERROR("Write domain conflict: "
3261 "obj %p target %d offset %d "
3262 "new %08x old %08x\n",
3263 obj
, reloc
->target_handle
,
3264 (int) reloc
->offset
,
3265 reloc
->write_domain
,
3266 target_obj
->pending_write_domain
);
3267 drm_gem_object_unreference(target_obj
);
3268 i915_gem_object_unpin(obj
);
3272 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3273 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3275 /* If the relocation already has the right value in it, no
3276 * more work needs to be done.
3278 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3279 drm_gem_object_unreference(target_obj
);
3283 /* Check that the relocation address is valid... */
3284 if (reloc
->offset
> obj
->size
- 4) {
3285 DRM_ERROR("Relocation beyond object bounds: "
3286 "obj %p target %d offset %d size %d.\n",
3287 obj
, reloc
->target_handle
,
3288 (int) reloc
->offset
, (int) obj
->size
);
3289 drm_gem_object_unreference(target_obj
);
3290 i915_gem_object_unpin(obj
);
3293 if (reloc
->offset
& 3) {
3294 DRM_ERROR("Relocation not 4-byte aligned: "
3295 "obj %p target %d offset %d.\n",
3296 obj
, reloc
->target_handle
,
3297 (int) reloc
->offset
);
3298 drm_gem_object_unreference(target_obj
);
3299 i915_gem_object_unpin(obj
);
3303 /* and points to somewhere within the target object. */
3304 if (reloc
->delta
>= target_obj
->size
) {
3305 DRM_ERROR("Relocation beyond target object bounds: "
3306 "obj %p target %d delta %d size %d.\n",
3307 obj
, reloc
->target_handle
,
3308 (int) reloc
->delta
, (int) target_obj
->size
);
3309 drm_gem_object_unreference(target_obj
);
3310 i915_gem_object_unpin(obj
);
3314 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3316 drm_gem_object_unreference(target_obj
);
3317 i915_gem_object_unpin(obj
);
3321 /* Map the page containing the relocation we're going to
3324 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3325 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3328 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3329 (reloc_offset
& (PAGE_SIZE
- 1)));
3330 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3333 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3334 obj
, (unsigned int) reloc
->offset
,
3335 readl(reloc_entry
), reloc_val
);
3337 writel(reloc_val
, reloc_entry
);
3338 io_mapping_unmap_atomic(reloc_page
);
3340 /* The updated presumed offset for this entry will be
3341 * copied back out to the user.
3343 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3345 drm_gem_object_unreference(target_obj
);
3350 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3355 /** Dispatch a batchbuffer to the ring
3358 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3359 struct drm_i915_gem_execbuffer
*exec
,
3360 struct drm_clip_rect
*cliprects
,
3361 uint64_t exec_offset
)
3363 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3364 int nbox
= exec
->num_cliprects
;
3366 uint32_t exec_start
, exec_len
;
3369 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3370 exec_len
= (uint32_t) exec
->batch_len
;
3372 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3374 count
= nbox
? nbox
: 1;
3376 for (i
= 0; i
< count
; i
++) {
3378 int ret
= i915_emit_box(dev
, cliprects
, i
,
3379 exec
->DR1
, exec
->DR4
);
3384 if (IS_I830(dev
) || IS_845G(dev
)) {
3386 OUT_RING(MI_BATCH_BUFFER
);
3387 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3388 OUT_RING(exec_start
+ exec_len
- 4);
3393 if (IS_I965G(dev
)) {
3394 OUT_RING(MI_BATCH_BUFFER_START
|
3396 MI_BATCH_NON_SECURE_I965
);
3397 OUT_RING(exec_start
);
3399 OUT_RING(MI_BATCH_BUFFER_START
|
3401 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3407 /* XXX breadcrumb */
3411 /* Throttle our rendering by waiting until the ring has completed our requests
3412 * emitted over 20 msec ago.
3414 * Note that if we were to use the current jiffies each time around the loop,
3415 * we wouldn't escape the function with any frames outstanding if the time to
3416 * render a frame was over 20ms.
3418 * This should get us reasonable parallelism between CPU and GPU but also
3419 * relatively low latency when blocking on a particular request to finish.
3422 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3424 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3426 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3428 mutex_lock(&dev
->struct_mutex
);
3429 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3430 struct drm_i915_gem_request
*request
;
3432 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3433 struct drm_i915_gem_request
,
3436 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3439 ret
= i915_wait_request(dev
, request
->seqno
);
3443 mutex_unlock(&dev
->struct_mutex
);
3449 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object
*exec_list
,
3450 uint32_t buffer_count
,
3451 struct drm_i915_gem_relocation_entry
**relocs
)
3453 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3457 for (i
= 0; i
< buffer_count
; i
++) {
3458 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3460 reloc_count
+= exec_list
[i
].relocation_count
;
3463 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3464 if (*relocs
== NULL
)
3467 for (i
= 0; i
< buffer_count
; i
++) {
3468 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3470 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3472 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3474 exec_list
[i
].relocation_count
*
3477 drm_free_large(*relocs
);
3482 reloc_index
+= exec_list
[i
].relocation_count
;
3489 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object
*exec_list
,
3490 uint32_t buffer_count
,
3491 struct drm_i915_gem_relocation_entry
*relocs
)
3493 uint32_t reloc_count
= 0, i
;
3496 for (i
= 0; i
< buffer_count
; i
++) {
3497 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3500 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3502 unwritten
= copy_to_user(user_relocs
,
3503 &relocs
[reloc_count
],
3504 exec_list
[i
].relocation_count
*
3512 reloc_count
+= exec_list
[i
].relocation_count
;
3516 drm_free_large(relocs
);
3522 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer
*exec
,
3523 uint64_t exec_offset
)
3525 uint32_t exec_start
, exec_len
;
3527 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3528 exec_len
= (uint32_t) exec
->batch_len
;
3530 if ((exec_start
| exec_len
) & 0x7)
3540 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3541 struct drm_file
*file_priv
)
3543 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3544 struct drm_i915_gem_execbuffer
*args
= data
;
3545 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3546 struct drm_gem_object
**object_list
= NULL
;
3547 struct drm_gem_object
*batch_obj
;
3548 struct drm_i915_gem_object
*obj_priv
;
3549 struct drm_clip_rect
*cliprects
= NULL
;
3550 struct drm_i915_gem_relocation_entry
*relocs
;
3551 int ret
, ret2
, i
, pinned
= 0;
3552 uint64_t exec_offset
;
3553 uint32_t seqno
, flush_domains
, reloc_index
;
3557 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3558 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3561 if (args
->buffer_count
< 1) {
3562 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3565 /* Copy in the exec list from userland */
3566 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3567 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3568 if (exec_list
== NULL
|| object_list
== NULL
) {
3569 DRM_ERROR("Failed to allocate exec or object list "
3571 args
->buffer_count
);
3575 ret
= copy_from_user(exec_list
,
3576 (struct drm_i915_relocation_entry __user
*)
3577 (uintptr_t) args
->buffers_ptr
,
3578 sizeof(*exec_list
) * args
->buffer_count
);
3580 DRM_ERROR("copy %d exec entries failed %d\n",
3581 args
->buffer_count
, ret
);
3585 if (args
->num_cliprects
!= 0) {
3586 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3588 if (cliprects
== NULL
)
3591 ret
= copy_from_user(cliprects
,
3592 (struct drm_clip_rect __user
*)
3593 (uintptr_t) args
->cliprects_ptr
,
3594 sizeof(*cliprects
) * args
->num_cliprects
);
3596 DRM_ERROR("copy %d cliprects failed: %d\n",
3597 args
->num_cliprects
, ret
);
3602 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3607 mutex_lock(&dev
->struct_mutex
);
3609 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3611 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3612 DRM_ERROR("Execbuf while wedged\n");
3613 mutex_unlock(&dev
->struct_mutex
);
3618 if (dev_priv
->mm
.suspended
) {
3619 DRM_ERROR("Execbuf while VT-switched.\n");
3620 mutex_unlock(&dev
->struct_mutex
);
3625 /* Look up object handles */
3626 for (i
= 0; i
< args
->buffer_count
; i
++) {
3627 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3628 exec_list
[i
].handle
);
3629 if (object_list
[i
] == NULL
) {
3630 DRM_ERROR("Invalid object handle %d at index %d\n",
3631 exec_list
[i
].handle
, i
);
3636 obj_priv
= object_list
[i
]->driver_private
;
3637 if (obj_priv
->in_execbuffer
) {
3638 DRM_ERROR("Object %p appears more than once in object list\n",
3643 obj_priv
->in_execbuffer
= true;
3646 /* Pin and relocate */
3647 for (pin_tries
= 0; ; pin_tries
++) {
3651 for (i
= 0; i
< args
->buffer_count
; i
++) {
3652 object_list
[i
]->pending_read_domains
= 0;
3653 object_list
[i
]->pending_write_domain
= 0;
3654 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3657 &relocs
[reloc_index
]);
3661 reloc_index
+= exec_list
[i
].relocation_count
;
3667 /* error other than GTT full, or we've already tried again */
3668 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3669 if (ret
!= -ERESTARTSYS
) {
3670 unsigned long long total_size
= 0;
3671 for (i
= 0; i
< args
->buffer_count
; i
++)
3672 total_size
+= object_list
[i
]->size
;
3673 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3674 pinned
+1, args
->buffer_count
,
3676 DRM_ERROR("%d objects [%d pinned], "
3677 "%d object bytes [%d pinned], "
3678 "%d/%d gtt bytes\n",
3679 atomic_read(&dev
->object_count
),
3680 atomic_read(&dev
->pin_count
),
3681 atomic_read(&dev
->object_memory
),
3682 atomic_read(&dev
->pin_memory
),
3683 atomic_read(&dev
->gtt_memory
),
3689 /* unpin all of our buffers */
3690 for (i
= 0; i
< pinned
; i
++)
3691 i915_gem_object_unpin(object_list
[i
]);
3694 /* evict everyone we can from the aperture */
3695 ret
= i915_gem_evict_everything(dev
);
3696 if (ret
&& ret
!= -ENOSPC
)
3700 /* Set the pending read domains for the batch buffer to COMMAND */
3701 batch_obj
= object_list
[args
->buffer_count
-1];
3702 if (batch_obj
->pending_write_domain
) {
3703 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3707 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3709 /* Sanity check the batch buffer, prior to moving objects */
3710 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3711 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3713 DRM_ERROR("execbuf with invalid offset/length\n");
3717 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3719 /* Zero the global flush/invalidate flags. These
3720 * will be modified as new domains are computed
3723 dev
->invalidate_domains
= 0;
3724 dev
->flush_domains
= 0;
3726 for (i
= 0; i
< args
->buffer_count
; i
++) {
3727 struct drm_gem_object
*obj
= object_list
[i
];
3729 /* Compute new gpu domains and update invalidate/flush */
3730 i915_gem_object_set_to_gpu_domain(obj
);
3733 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3735 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3737 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3739 dev
->invalidate_domains
,
3740 dev
->flush_domains
);
3743 dev
->invalidate_domains
,
3744 dev
->flush_domains
);
3745 if (dev
->flush_domains
)
3746 (void)i915_add_request(dev
, file_priv
,
3747 dev
->flush_domains
);
3750 for (i
= 0; i
< args
->buffer_count
; i
++) {
3751 struct drm_gem_object
*obj
= object_list
[i
];
3752 uint32_t old_write_domain
= obj
->write_domain
;
3754 obj
->write_domain
= obj
->pending_write_domain
;
3755 trace_i915_gem_object_change_domain(obj
,
3760 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3763 for (i
= 0; i
< args
->buffer_count
; i
++) {
3764 i915_gem_object_check_coherency(object_list
[i
],
3765 exec_list
[i
].handle
);
3770 i915_gem_dump_object(batch_obj
,
3776 /* Exec the batchbuffer */
3777 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3779 DRM_ERROR("dispatch failed %d\n", ret
);
3784 * Ensure that the commands in the batch buffer are
3785 * finished before the interrupt fires
3787 flush_domains
= i915_retire_commands(dev
);
3789 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3792 * Get a seqno representing the execution of the current buffer,
3793 * which we can wait on. We would like to mitigate these interrupts,
3794 * likely by only creating seqnos occasionally (so that we have
3795 * *some* interrupts representing completion of buffers that we can
3796 * wait on when trying to clear up gtt space).
3798 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3800 for (i
= 0; i
< args
->buffer_count
; i
++) {
3801 struct drm_gem_object
*obj
= object_list
[i
];
3803 i915_gem_object_move_to_active(obj
, seqno
);
3805 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3809 i915_dump_lru(dev
, __func__
);
3812 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3815 for (i
= 0; i
< pinned
; i
++)
3816 i915_gem_object_unpin(object_list
[i
]);
3818 for (i
= 0; i
< args
->buffer_count
; i
++) {
3819 if (object_list
[i
]) {
3820 obj_priv
= object_list
[i
]->driver_private
;
3821 obj_priv
->in_execbuffer
= false;
3823 drm_gem_object_unreference(object_list
[i
]);
3826 mutex_unlock(&dev
->struct_mutex
);
3829 /* Copy the new buffer offsets back to the user's exec list. */
3830 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3831 (uintptr_t) args
->buffers_ptr
,
3833 sizeof(*exec_list
) * args
->buffer_count
);
3836 DRM_ERROR("failed to copy %d exec entries "
3837 "back to user (%d)\n",
3838 args
->buffer_count
, ret
);
3842 /* Copy the updated relocations out regardless of current error
3843 * state. Failure to update the relocs would mean that the next
3844 * time userland calls execbuf, it would do so with presumed offset
3845 * state that didn't match the actual object state.
3847 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3850 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3857 drm_free_large(object_list
);
3858 drm_free_large(exec_list
);
3865 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3867 struct drm_device
*dev
= obj
->dev
;
3868 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3871 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3872 if (obj_priv
->gtt_space
== NULL
) {
3873 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
3878 * Pre-965 chips need a fence register set up in order to
3879 * properly handle tiled surfaces.
3881 if (!IS_I965G(dev
) && obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
3882 ret
= i915_gem_object_get_fence_reg(obj
);
3884 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3885 DRM_ERROR("Failure to install fence: %d\n",
3890 obj_priv
->pin_count
++;
3892 /* If the object is not active and not pending a flush,
3893 * remove it from the inactive list
3895 if (obj_priv
->pin_count
== 1) {
3896 atomic_inc(&dev
->pin_count
);
3897 atomic_add(obj
->size
, &dev
->pin_memory
);
3898 if (!obj_priv
->active
&&
3899 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
3900 !list_empty(&obj_priv
->list
))
3901 list_del_init(&obj_priv
->list
);
3903 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3909 i915_gem_object_unpin(struct drm_gem_object
*obj
)
3911 struct drm_device
*dev
= obj
->dev
;
3912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3913 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3915 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3916 obj_priv
->pin_count
--;
3917 BUG_ON(obj_priv
->pin_count
< 0);
3918 BUG_ON(obj_priv
->gtt_space
== NULL
);
3920 /* If the object is no longer pinned, and is
3921 * neither active nor being flushed, then stick it on
3924 if (obj_priv
->pin_count
== 0) {
3925 if (!obj_priv
->active
&&
3926 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
3927 list_move_tail(&obj_priv
->list
,
3928 &dev_priv
->mm
.inactive_list
);
3929 atomic_dec(&dev
->pin_count
);
3930 atomic_sub(obj
->size
, &dev
->pin_memory
);
3932 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3936 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3937 struct drm_file
*file_priv
)
3939 struct drm_i915_gem_pin
*args
= data
;
3940 struct drm_gem_object
*obj
;
3941 struct drm_i915_gem_object
*obj_priv
;
3944 mutex_lock(&dev
->struct_mutex
);
3946 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
3948 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3950 mutex_unlock(&dev
->struct_mutex
);
3953 obj_priv
= obj
->driver_private
;
3955 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
3956 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3957 drm_gem_object_unreference(obj
);
3958 mutex_unlock(&dev
->struct_mutex
);
3962 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
3963 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3965 drm_gem_object_unreference(obj
);
3966 mutex_unlock(&dev
->struct_mutex
);
3970 obj_priv
->user_pin_count
++;
3971 obj_priv
->pin_filp
= file_priv
;
3972 if (obj_priv
->user_pin_count
== 1) {
3973 ret
= i915_gem_object_pin(obj
, args
->alignment
);
3975 drm_gem_object_unreference(obj
);
3976 mutex_unlock(&dev
->struct_mutex
);
3981 /* XXX - flush the CPU caches for pinned objects
3982 * as the X server doesn't manage domains yet
3984 i915_gem_object_flush_cpu_write_domain(obj
);
3985 args
->offset
= obj_priv
->gtt_offset
;
3986 drm_gem_object_unreference(obj
);
3987 mutex_unlock(&dev
->struct_mutex
);
3993 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3994 struct drm_file
*file_priv
)
3996 struct drm_i915_gem_pin
*args
= data
;
3997 struct drm_gem_object
*obj
;
3998 struct drm_i915_gem_object
*obj_priv
;
4000 mutex_lock(&dev
->struct_mutex
);
4002 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4004 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4006 mutex_unlock(&dev
->struct_mutex
);
4010 obj_priv
= obj
->driver_private
;
4011 if (obj_priv
->pin_filp
!= file_priv
) {
4012 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4014 drm_gem_object_unreference(obj
);
4015 mutex_unlock(&dev
->struct_mutex
);
4018 obj_priv
->user_pin_count
--;
4019 if (obj_priv
->user_pin_count
== 0) {
4020 obj_priv
->pin_filp
= NULL
;
4021 i915_gem_object_unpin(obj
);
4024 drm_gem_object_unreference(obj
);
4025 mutex_unlock(&dev
->struct_mutex
);
4030 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4031 struct drm_file
*file_priv
)
4033 struct drm_i915_gem_busy
*args
= data
;
4034 struct drm_gem_object
*obj
;
4035 struct drm_i915_gem_object
*obj_priv
;
4037 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4039 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4044 mutex_lock(&dev
->struct_mutex
);
4045 /* Update the active list for the hardware's current position.
4046 * Otherwise this only updates on a delayed timer or when irqs are
4047 * actually unmasked, and our working set ends up being larger than
4050 i915_gem_retire_requests(dev
);
4052 obj_priv
= obj
->driver_private
;
4053 /* Don't count being on the flushing list against the object being
4054 * done. Otherwise, a buffer left on the flushing list but not getting
4055 * flushed (because nobody's flushing that domain) won't ever return
4056 * unbusy and get reused by libdrm's bo cache. The other expected
4057 * consumer of this interface, OpenGL's occlusion queries, also specs
4058 * that the objects get unbusy "eventually" without any interference.
4060 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4062 drm_gem_object_unreference(obj
);
4063 mutex_unlock(&dev
->struct_mutex
);
4068 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4069 struct drm_file
*file_priv
)
4071 return i915_gem_ring_throttle(dev
, file_priv
);
4075 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4076 struct drm_file
*file_priv
)
4078 struct drm_i915_gem_madvise
*args
= data
;
4079 struct drm_gem_object
*obj
;
4080 struct drm_i915_gem_object
*obj_priv
;
4082 switch (args
->madv
) {
4083 case I915_MADV_DONTNEED
:
4084 case I915_MADV_WILLNEED
:
4090 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4092 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4097 mutex_lock(&dev
->struct_mutex
);
4098 obj_priv
= obj
->driver_private
;
4100 if (obj_priv
->pin_count
) {
4101 drm_gem_object_unreference(obj
);
4102 mutex_unlock(&dev
->struct_mutex
);
4104 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4108 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4109 obj_priv
->madv
= args
->madv
;
4111 /* if the object is no longer bound, discard its backing storage */
4112 if (i915_gem_object_is_purgeable(obj_priv
) &&
4113 obj_priv
->gtt_space
== NULL
)
4114 i915_gem_object_truncate(obj
);
4116 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4118 drm_gem_object_unreference(obj
);
4119 mutex_unlock(&dev
->struct_mutex
);
4124 int i915_gem_init_object(struct drm_gem_object
*obj
)
4126 struct drm_i915_gem_object
*obj_priv
;
4128 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4129 if (obj_priv
== NULL
)
4133 * We've just allocated pages from the kernel,
4134 * so they've just been written by the CPU with
4135 * zeros. They'll need to be clflushed before we
4136 * use them with the GPU.
4138 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4139 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4141 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4143 obj
->driver_private
= obj_priv
;
4144 obj_priv
->obj
= obj
;
4145 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4146 INIT_LIST_HEAD(&obj_priv
->list
);
4147 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4148 obj_priv
->madv
= I915_MADV_WILLNEED
;
4150 trace_i915_gem_object_create(obj
);
4155 void i915_gem_free_object(struct drm_gem_object
*obj
)
4157 struct drm_device
*dev
= obj
->dev
;
4158 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4160 trace_i915_gem_object_destroy(obj
);
4162 while (obj_priv
->pin_count
> 0)
4163 i915_gem_object_unpin(obj
);
4165 if (obj_priv
->phys_obj
)
4166 i915_gem_detach_phys_object(dev
, obj
);
4168 i915_gem_object_unbind(obj
);
4170 if (obj_priv
->mmap_offset
)
4171 i915_gem_free_mmap_offset(obj
);
4173 kfree(obj_priv
->page_cpu_valid
);
4174 kfree(obj_priv
->bit_17
);
4175 kfree(obj
->driver_private
);
4178 /** Unbinds all inactive objects. */
4180 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4182 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4184 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4185 struct drm_gem_object
*obj
;
4188 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4189 struct drm_i915_gem_object
,
4192 ret
= i915_gem_object_unbind(obj
);
4194 DRM_ERROR("Error unbinding object: %d\n", ret
);
4203 i915_gem_idle(struct drm_device
*dev
)
4205 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4206 uint32_t seqno
, cur_seqno
, last_seqno
;
4209 mutex_lock(&dev
->struct_mutex
);
4211 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4212 mutex_unlock(&dev
->struct_mutex
);
4216 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4217 * We need to replace this with a semaphore, or something.
4219 dev_priv
->mm
.suspended
= 1;
4220 del_timer(&dev_priv
->hangcheck_timer
);
4222 /* Cancel the retire work handler, wait for it to finish if running
4224 mutex_unlock(&dev
->struct_mutex
);
4225 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4226 mutex_lock(&dev
->struct_mutex
);
4228 i915_kernel_lost_context(dev
);
4230 /* Flush the GPU along with all non-CPU write domains
4232 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4233 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4236 mutex_unlock(&dev
->struct_mutex
);
4240 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4244 cur_seqno
= i915_get_gem_seqno(dev
);
4245 if (i915_seqno_passed(cur_seqno
, seqno
))
4247 if (last_seqno
== cur_seqno
) {
4248 if (stuck
++ > 100) {
4249 DRM_ERROR("hardware wedged\n");
4250 atomic_set(&dev_priv
->mm
.wedged
, 1);
4251 DRM_WAKEUP(&dev_priv
->irq_queue
);
4256 last_seqno
= cur_seqno
;
4258 dev_priv
->mm
.waiting_gem_seqno
= 0;
4260 i915_gem_retire_requests(dev
);
4262 spin_lock(&dev_priv
->mm
.active_list_lock
);
4263 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4264 /* Active and flushing should now be empty as we've
4265 * waited for a sequence higher than any pending execbuffer
4267 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4268 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4269 /* Request should now be empty as we've also waited
4270 * for the last request in the list
4272 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4275 /* Empty the active and flushing lists to inactive. If there's
4276 * anything left at this point, it means that we're wedged and
4277 * nothing good's going to happen by leaving them there. So strip
4278 * the GPU domains and just stuff them onto inactive.
4280 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4281 struct drm_gem_object
*obj
;
4282 uint32_t old_write_domain
;
4284 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4285 struct drm_i915_gem_object
,
4287 old_write_domain
= obj
->write_domain
;
4288 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4289 i915_gem_object_move_to_inactive(obj
);
4291 trace_i915_gem_object_change_domain(obj
,
4295 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4297 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4298 struct drm_gem_object
*obj
;
4299 uint32_t old_write_domain
;
4301 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4302 struct drm_i915_gem_object
,
4304 old_write_domain
= obj
->write_domain
;
4305 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4306 i915_gem_object_move_to_inactive(obj
);
4308 trace_i915_gem_object_change_domain(obj
,
4314 /* Move all inactive buffers out of the GTT. */
4315 ret
= i915_gem_evict_from_inactive_list(dev
);
4316 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4318 mutex_unlock(&dev
->struct_mutex
);
4322 i915_gem_cleanup_ringbuffer(dev
);
4323 mutex_unlock(&dev
->struct_mutex
);
4329 i915_gem_init_hws(struct drm_device
*dev
)
4331 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4332 struct drm_gem_object
*obj
;
4333 struct drm_i915_gem_object
*obj_priv
;
4336 /* If we need a physical address for the status page, it's already
4337 * initialized at driver load time.
4339 if (!I915_NEED_GFX_HWS(dev
))
4342 obj
= drm_gem_object_alloc(dev
, 4096);
4344 DRM_ERROR("Failed to allocate status page\n");
4347 obj_priv
= obj
->driver_private
;
4348 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4350 ret
= i915_gem_object_pin(obj
, 4096);
4352 drm_gem_object_unreference(obj
);
4356 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4358 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4359 if (dev_priv
->hw_status_page
== NULL
) {
4360 DRM_ERROR("Failed to map status page.\n");
4361 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4362 i915_gem_object_unpin(obj
);
4363 drm_gem_object_unreference(obj
);
4366 dev_priv
->hws_obj
= obj
;
4367 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4368 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4369 I915_READ(HWS_PGA
); /* posting read */
4370 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4376 i915_gem_cleanup_hws(struct drm_device
*dev
)
4378 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4379 struct drm_gem_object
*obj
;
4380 struct drm_i915_gem_object
*obj_priv
;
4382 if (dev_priv
->hws_obj
== NULL
)
4385 obj
= dev_priv
->hws_obj
;
4386 obj_priv
= obj
->driver_private
;
4388 kunmap(obj_priv
->pages
[0]);
4389 i915_gem_object_unpin(obj
);
4390 drm_gem_object_unreference(obj
);
4391 dev_priv
->hws_obj
= NULL
;
4393 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4394 dev_priv
->hw_status_page
= NULL
;
4396 /* Write high address into HWS_PGA when disabling. */
4397 I915_WRITE(HWS_PGA
, 0x1ffff000);
4401 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4403 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4404 struct drm_gem_object
*obj
;
4405 struct drm_i915_gem_object
*obj_priv
;
4406 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4410 ret
= i915_gem_init_hws(dev
);
4414 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4416 DRM_ERROR("Failed to allocate ringbuffer\n");
4417 i915_gem_cleanup_hws(dev
);
4420 obj_priv
= obj
->driver_private
;
4422 ret
= i915_gem_object_pin(obj
, 4096);
4424 drm_gem_object_unreference(obj
);
4425 i915_gem_cleanup_hws(dev
);
4429 /* Set up the kernel mapping for the ring. */
4430 ring
->Size
= obj
->size
;
4432 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4433 ring
->map
.size
= obj
->size
;
4435 ring
->map
.flags
= 0;
4438 drm_core_ioremap_wc(&ring
->map
, dev
);
4439 if (ring
->map
.handle
== NULL
) {
4440 DRM_ERROR("Failed to map ringbuffer.\n");
4441 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4442 i915_gem_object_unpin(obj
);
4443 drm_gem_object_unreference(obj
);
4444 i915_gem_cleanup_hws(dev
);
4447 ring
->ring_obj
= obj
;
4448 ring
->virtual_start
= ring
->map
.handle
;
4450 /* Stop the ring if it's running. */
4451 I915_WRITE(PRB0_CTL
, 0);
4452 I915_WRITE(PRB0_TAIL
, 0);
4453 I915_WRITE(PRB0_HEAD
, 0);
4455 /* Initialize the ring. */
4456 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4457 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4459 /* G45 ring initialization fails to reset head to zero */
4461 DRM_ERROR("Ring head not reset to zero "
4462 "ctl %08x head %08x tail %08x start %08x\n",
4463 I915_READ(PRB0_CTL
),
4464 I915_READ(PRB0_HEAD
),
4465 I915_READ(PRB0_TAIL
),
4466 I915_READ(PRB0_START
));
4467 I915_WRITE(PRB0_HEAD
, 0);
4469 DRM_ERROR("Ring head forced to zero "
4470 "ctl %08x head %08x tail %08x start %08x\n",
4471 I915_READ(PRB0_CTL
),
4472 I915_READ(PRB0_HEAD
),
4473 I915_READ(PRB0_TAIL
),
4474 I915_READ(PRB0_START
));
4477 I915_WRITE(PRB0_CTL
,
4478 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4482 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4484 /* If the head is still not zero, the ring is dead */
4486 DRM_ERROR("Ring initialization failed "
4487 "ctl %08x head %08x tail %08x start %08x\n",
4488 I915_READ(PRB0_CTL
),
4489 I915_READ(PRB0_HEAD
),
4490 I915_READ(PRB0_TAIL
),
4491 I915_READ(PRB0_START
));
4495 /* Update our cache of the ring state */
4496 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4497 i915_kernel_lost_context(dev
);
4499 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4500 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4501 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4502 if (ring
->space
< 0)
4503 ring
->space
+= ring
->Size
;
4510 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4512 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4514 if (dev_priv
->ring
.ring_obj
== NULL
)
4517 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4519 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4520 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4521 dev_priv
->ring
.ring_obj
= NULL
;
4522 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4524 i915_gem_cleanup_hws(dev
);
4528 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4529 struct drm_file
*file_priv
)
4531 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4534 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4537 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4538 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4539 atomic_set(&dev_priv
->mm
.wedged
, 0);
4542 mutex_lock(&dev
->struct_mutex
);
4543 dev_priv
->mm
.suspended
= 0;
4545 ret
= i915_gem_init_ringbuffer(dev
);
4547 mutex_unlock(&dev
->struct_mutex
);
4551 spin_lock(&dev_priv
->mm
.active_list_lock
);
4552 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4553 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4555 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4556 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4557 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4558 mutex_unlock(&dev
->struct_mutex
);
4560 drm_irq_install(dev
);
4566 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4567 struct drm_file
*file_priv
)
4569 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4572 drm_irq_uninstall(dev
);
4573 return i915_gem_idle(dev
);
4577 i915_gem_lastclose(struct drm_device
*dev
)
4581 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4584 ret
= i915_gem_idle(dev
);
4586 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4590 i915_gem_load(struct drm_device
*dev
)
4593 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4595 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4596 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4597 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4598 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4599 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4600 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4601 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4602 i915_gem_retire_work_handler
);
4603 dev_priv
->mm
.next_gem_seqno
= 1;
4605 spin_lock(&shrink_list_lock
);
4606 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4607 spin_unlock(&shrink_list_lock
);
4609 /* Old X drivers will take 0-2 for front, back, depth buffers */
4610 dev_priv
->fence_reg_start
= 3;
4612 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4613 dev_priv
->num_fence_regs
= 16;
4615 dev_priv
->num_fence_regs
= 8;
4617 /* Initialize fence registers to zero */
4618 if (IS_I965G(dev
)) {
4619 for (i
= 0; i
< 16; i
++)
4620 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4622 for (i
= 0; i
< 8; i
++)
4623 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4624 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4625 for (i
= 0; i
< 8; i
++)
4626 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4629 i915_gem_detect_bit_6_swizzle(dev
);
4633 * Create a physically contiguous memory object for this object
4634 * e.g. for cursor + overlay regs
4636 int i915_gem_init_phys_object(struct drm_device
*dev
,
4639 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4640 struct drm_i915_gem_phys_object
*phys_obj
;
4643 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4646 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4652 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0, 0xffffffff);
4653 if (!phys_obj
->handle
) {
4658 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4661 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4669 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4671 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4672 struct drm_i915_gem_phys_object
*phys_obj
;
4674 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4677 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4678 if (phys_obj
->cur_obj
) {
4679 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4683 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4685 drm_pci_free(dev
, phys_obj
->handle
);
4687 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4690 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4694 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4695 i915_gem_free_phys_object(dev
, i
);
4698 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4699 struct drm_gem_object
*obj
)
4701 struct drm_i915_gem_object
*obj_priv
;
4706 obj_priv
= obj
->driver_private
;
4707 if (!obj_priv
->phys_obj
)
4710 ret
= i915_gem_object_get_pages(obj
);
4714 page_count
= obj
->size
/ PAGE_SIZE
;
4716 for (i
= 0; i
< page_count
; i
++) {
4717 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4718 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4720 memcpy(dst
, src
, PAGE_SIZE
);
4721 kunmap_atomic(dst
, KM_USER0
);
4723 drm_clflush_pages(obj_priv
->pages
, page_count
);
4724 drm_agp_chipset_flush(dev
);
4726 i915_gem_object_put_pages(obj
);
4728 obj_priv
->phys_obj
->cur_obj
= NULL
;
4729 obj_priv
->phys_obj
= NULL
;
4733 i915_gem_attach_phys_object(struct drm_device
*dev
,
4734 struct drm_gem_object
*obj
, int id
)
4736 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4737 struct drm_i915_gem_object
*obj_priv
;
4742 if (id
> I915_MAX_PHYS_OBJECT
)
4745 obj_priv
= obj
->driver_private
;
4747 if (obj_priv
->phys_obj
) {
4748 if (obj_priv
->phys_obj
->id
== id
)
4750 i915_gem_detach_phys_object(dev
, obj
);
4754 /* create a new object */
4755 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4756 ret
= i915_gem_init_phys_object(dev
, id
,
4759 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4764 /* bind to the object */
4765 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4766 obj_priv
->phys_obj
->cur_obj
= obj
;
4768 ret
= i915_gem_object_get_pages(obj
);
4770 DRM_ERROR("failed to get page list\n");
4774 page_count
= obj
->size
/ PAGE_SIZE
;
4776 for (i
= 0; i
< page_count
; i
++) {
4777 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4778 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4780 memcpy(dst
, src
, PAGE_SIZE
);
4781 kunmap_atomic(src
, KM_USER0
);
4784 i915_gem_object_put_pages(obj
);
4792 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4793 struct drm_i915_gem_pwrite
*args
,
4794 struct drm_file
*file_priv
)
4796 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4799 char __user
*user_data
;
4801 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4802 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4804 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4805 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4809 drm_agp_chipset_flush(dev
);
4813 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4815 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4817 /* Clean up our request list when the client is going away, so that
4818 * later retire_requests won't dereference our soon-to-be-gone
4821 mutex_lock(&dev
->struct_mutex
);
4822 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4823 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4824 mutex_unlock(&dev
->struct_mutex
);
4828 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
4830 drm_i915_private_t
*dev_priv
, *next_dev
;
4831 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4833 int would_deadlock
= 1;
4835 /* "fast-path" to count number of available objects */
4836 if (nr_to_scan
== 0) {
4837 spin_lock(&shrink_list_lock
);
4838 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4839 struct drm_device
*dev
= dev_priv
->dev
;
4841 if (mutex_trylock(&dev
->struct_mutex
)) {
4842 list_for_each_entry(obj_priv
,
4843 &dev_priv
->mm
.inactive_list
,
4846 mutex_unlock(&dev
->struct_mutex
);
4849 spin_unlock(&shrink_list_lock
);
4851 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4854 spin_lock(&shrink_list_lock
);
4856 /* first scan for clean buffers */
4857 list_for_each_entry_safe(dev_priv
, next_dev
,
4858 &shrink_list
, mm
.shrink_list
) {
4859 struct drm_device
*dev
= dev_priv
->dev
;
4861 if (! mutex_trylock(&dev
->struct_mutex
))
4864 spin_unlock(&shrink_list_lock
);
4866 i915_gem_retire_requests(dev
);
4868 list_for_each_entry_safe(obj_priv
, next_obj
,
4869 &dev_priv
->mm
.inactive_list
,
4871 if (i915_gem_object_is_purgeable(obj_priv
)) {
4872 i915_gem_object_unbind(obj_priv
->obj
);
4873 if (--nr_to_scan
<= 0)
4878 spin_lock(&shrink_list_lock
);
4879 mutex_unlock(&dev
->struct_mutex
);
4883 if (nr_to_scan
<= 0)
4887 /* second pass, evict/count anything still on the inactive list */
4888 list_for_each_entry_safe(dev_priv
, next_dev
,
4889 &shrink_list
, mm
.shrink_list
) {
4890 struct drm_device
*dev
= dev_priv
->dev
;
4892 if (! mutex_trylock(&dev
->struct_mutex
))
4895 spin_unlock(&shrink_list_lock
);
4897 list_for_each_entry_safe(obj_priv
, next_obj
,
4898 &dev_priv
->mm
.inactive_list
,
4900 if (nr_to_scan
> 0) {
4901 i915_gem_object_unbind(obj_priv
->obj
);
4907 spin_lock(&shrink_list_lock
);
4908 mutex_unlock(&dev
->struct_mutex
);
4913 spin_unlock(&shrink_list_lock
);
4918 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4923 static struct shrinker shrinker
= {
4924 .shrink
= i915_gem_shrink
,
4925 .seeks
= DEFAULT_SEEKS
,
4929 i915_gem_shrinker_init(void)
4931 register_shrinker(&shrinker
);
4935 i915_gem_shrinker_exit(void)
4937 unregister_shrinker(&shrinker
);