2 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
3 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2007,2009 MontaVista Software, Inc. <source@mvista.com>
13 #include <linux/module.h>
14 #include <linux/types.h>
15 #include <linux/pci.h>
16 #include <linux/ide.h>
17 #include <linux/init.h>
21 #define DRV_NAME "cmd64x"
24 * CMD64x specific registers definition.
27 #define CFR_INTR_CH0 0x04
35 #define ARTTIM23_DIS_RA2 0x04
36 #define ARTTIM23_DIS_RA3 0x08
37 #define ARTTIM23_INTR_CH1 0x10
44 #define MRDMODE_INTR_CH0 0x04
45 #define MRDMODE_INTR_CH1 0x08
46 #define UDIDETCR0 0x73
50 #define UDIDETCR1 0x7B
53 static u8
quantize_timing(int timing
, int quant
)
55 return (timing
+ quant
- 1) / quant
;
59 * This routine calculates active/recovery counts and then writes them into
60 * the chipset registers.
62 static void program_cycle_times (ide_drive_t
*drive
, int cycle_time
, int active_time
)
64 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
65 int clock_time
= 1000 / (ide_pci_clk
? ide_pci_clk
: 33);
66 u8 cycle_count
, active_count
, recovery_count
, drwtim
;
67 static const u8 recovery_values
[] =
68 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
69 static const u8 drwtim_regs
[4] = {DRWTIM0
, DRWTIM1
, DRWTIM2
, DRWTIM3
};
71 cycle_count
= quantize_timing( cycle_time
, clock_time
);
72 active_count
= quantize_timing(active_time
, clock_time
);
73 recovery_count
= cycle_count
- active_count
;
76 * In case we've got too long recovery phase, try to lengthen
79 if (recovery_count
> 16) {
80 active_count
+= recovery_count
- 16;
83 if (active_count
> 16) /* shouldn't actually happen... */
87 * Convert values to internal chipset representation
89 recovery_count
= recovery_values
[recovery_count
];
92 /* Program the active/recovery counts into the DRWTIM register */
93 drwtim
= (active_count
<< 4) | recovery_count
;
94 (void) pci_write_config_byte(dev
, drwtim_regs
[drive
->dn
], drwtim
);
98 * This routine writes into the chipset registers
99 * PIO setup/active/recovery timings.
101 static void cmd64x_tune_pio(ide_drive_t
*drive
, const u8 pio
)
103 ide_hwif_t
*hwif
= drive
->hwif
;
104 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
105 struct ide_timing
*t
= ide_timing_find_mode(XFER_PIO_0
+ pio
);
106 unsigned long setup_count
;
107 unsigned int cycle_time
;
110 static const u8 setup_values
[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
111 static const u8 arttim_regs
[4] = {ARTTIM0
, ARTTIM1
, ARTTIM23
, ARTTIM23
};
113 cycle_time
= ide_pio_cycle_time(drive
, pio
);
115 program_cycle_times(drive
, cycle_time
, t
->active
);
117 setup_count
= quantize_timing(t
->setup
,
118 1000 / (ide_pci_clk
? ide_pci_clk
: 33));
121 * The primary channel has individual address setup timing registers
122 * for each drive and the hardware selects the slowest timing itself.
123 * The secondary channel has one common register and we have to select
124 * the slowest address setup timing ourselves.
127 ide_drive_t
*pair
= ide_get_pair_dev(drive
);
129 ide_set_drivedata(drive
, (void *)setup_count
);
132 setup_count
= max_t(u8
, setup_count
,
133 (unsigned long)ide_get_drivedata(pair
));
136 if (setup_count
> 5) /* shouldn't actually happen... */
140 * Program the address setup clocks into the ARTTIM registers.
141 * Avoid clearing the secondary channel's interrupt bit.
143 (void) pci_read_config_byte (dev
, arttim_regs
[drive
->dn
], &arttim
);
145 arttim
&= ~ARTTIM23_INTR_CH1
;
147 arttim
|= setup_values
[setup_count
];
148 (void) pci_write_config_byte(dev
, arttim_regs
[drive
->dn
], arttim
);
152 * Attempts to set drive's PIO mode.
153 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
156 static void cmd64x_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
159 * Filter out the prefetch control values
160 * to prevent PIO5 from being programmed
162 if (pio
== 8 || pio
== 9)
165 cmd64x_tune_pio(drive
, pio
);
168 static void cmd64x_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
170 ide_hwif_t
*hwif
= drive
->hwif
;
171 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
172 u8 unit
= drive
->dn
& 0x01;
173 u8 regU
= 0, pciU
= hwif
->channel
? UDIDETCR1
: UDIDETCR0
;
175 if (speed
>= XFER_SW_DMA_0
) {
176 (void) pci_read_config_byte(dev
, pciU
, ®U
);
177 regU
&= ~(unit
? 0xCA : 0x35);
182 regU
|= unit
? 0x0A : 0x05;
185 regU
|= unit
? 0x4A : 0x15;
188 regU
|= unit
? 0x8A : 0x25;
191 regU
|= unit
? 0x42 : 0x11;
194 regU
|= unit
? 0x82 : 0x21;
197 regU
|= unit
? 0xC2 : 0x31;
200 program_cycle_times(drive
, 120, 70);
203 program_cycle_times(drive
, 150, 80);
206 program_cycle_times(drive
, 480, 215);
210 if (speed
>= XFER_SW_DMA_0
)
211 (void) pci_write_config_byte(dev
, pciU
, regU
);
214 static void cmd648_clear_irq(ide_drive_t
*drive
)
216 ide_hwif_t
*hwif
= drive
->hwif
;
217 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
218 unsigned long base
= pci_resource_start(dev
, 4);
219 u8 irq_mask
= hwif
->channel
? MRDMODE_INTR_CH1
:
221 u8 mrdmode
= inb(base
+ 1);
223 /* clear the interrupt bit */
224 outb((mrdmode
& ~(MRDMODE_INTR_CH0
| MRDMODE_INTR_CH1
)) | irq_mask
,
228 static void cmd64x_clear_irq(ide_drive_t
*drive
)
230 ide_hwif_t
*hwif
= drive
->hwif
;
231 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
232 int irq_reg
= hwif
->channel
? ARTTIM23
: CFR
;
233 u8 irq_mask
= hwif
->channel
? ARTTIM23_INTR_CH1
:
237 (void) pci_read_config_byte(dev
, irq_reg
, &irq_stat
);
238 /* clear the interrupt bit */
239 (void) pci_write_config_byte(dev
, irq_reg
, irq_stat
| irq_mask
);
242 static int cmd648_test_irq(ide_hwif_t
*hwif
)
244 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
245 unsigned long base
= pci_resource_start(dev
, 4);
246 u8 irq_mask
= hwif
->channel
? MRDMODE_INTR_CH1
:
248 u8 mrdmode
= inb(base
+ 1);
250 pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n",
251 hwif
->name
, mrdmode
, irq_mask
);
253 return (mrdmode
& irq_mask
) ? 1 : 0;
256 static int cmd64x_test_irq(ide_hwif_t
*hwif
)
258 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
259 int irq_reg
= hwif
->channel
? ARTTIM23
: CFR
;
260 u8 irq_mask
= hwif
->channel
? ARTTIM23_INTR_CH1
:
264 (void) pci_read_config_byte(dev
, irq_reg
, &irq_stat
);
266 pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n",
267 hwif
->name
, irq_stat
, irq_mask
);
269 return (irq_stat
& irq_mask
) ? 1 : 0;
273 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
274 * event order for DMA transfers.
277 static int cmd646_1_dma_end(ide_drive_t
*drive
)
279 ide_hwif_t
*hwif
= drive
->hwif
;
280 u8 dma_stat
= 0, dma_cmd
= 0;
283 dma_stat
= inb(hwif
->dma_base
+ ATA_DMA_STATUS
);
284 /* read DMA command state */
285 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
287 outb(dma_cmd
& ~1, hwif
->dma_base
+ ATA_DMA_CMD
);
288 /* clear the INTR & ERROR bits */
289 outb(dma_stat
| 6, hwif
->dma_base
+ ATA_DMA_STATUS
);
290 /* verify good DMA status */
291 return (dma_stat
& 7) != 4;
294 static int init_chipset_cmd64x(struct pci_dev
*dev
)
298 /* Set a good latency timer and cache line size value. */
299 (void) pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
300 /* FIXME: pci_set_master() to ensure a good latency timer value */
303 * Enable interrupts, select MEMORY READ LINE for reads.
305 * NOTE: although not mentioned in the PCI0646U specs,
306 * bits 0-1 are write only and won't be read back as
307 * set or not -- PCI0646U2 specs clarify this point.
309 (void) pci_read_config_byte (dev
, MRDMODE
, &mrdmode
);
311 (void) pci_write_config_byte(dev
, MRDMODE
, (mrdmode
| 0x02));
316 static u8
cmd64x_cable_detect(ide_hwif_t
*hwif
)
318 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
319 u8 bmidecsr
= 0, mask
= hwif
->channel
? 0x02 : 0x01;
321 switch (dev
->device
) {
322 case PCI_DEVICE_ID_CMD_648
:
323 case PCI_DEVICE_ID_CMD_649
:
324 pci_read_config_byte(dev
, BMIDECSR
, &bmidecsr
);
325 return (bmidecsr
& mask
) ? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
327 return ATA_CBL_PATA40
;
331 static const struct ide_port_ops cmd64x_port_ops
= {
332 .set_pio_mode
= cmd64x_set_pio_mode
,
333 .set_dma_mode
= cmd64x_set_dma_mode
,
334 .clear_irq
= cmd64x_clear_irq
,
335 .test_irq
= cmd64x_test_irq
,
336 .cable_detect
= cmd64x_cable_detect
,
339 static const struct ide_port_ops cmd648_port_ops
= {
340 .set_pio_mode
= cmd64x_set_pio_mode
,
341 .set_dma_mode
= cmd64x_set_dma_mode
,
342 .clear_irq
= cmd648_clear_irq
,
343 .test_irq
= cmd648_test_irq
,
344 .cable_detect
= cmd64x_cable_detect
,
347 static const struct ide_dma_ops cmd646_rev1_dma_ops
= {
348 .dma_host_set
= ide_dma_host_set
,
349 .dma_setup
= ide_dma_setup
,
350 .dma_start
= ide_dma_start
,
351 .dma_end
= cmd646_1_dma_end
,
352 .dma_test_irq
= ide_dma_test_irq
,
353 .dma_lost_irq
= ide_dma_lost_irq
,
354 .dma_timer_expiry
= ide_dma_sff_timer_expiry
,
355 .dma_sff_read_status
= ide_dma_sff_read_status
,
358 static const struct ide_port_info cmd64x_chipsets
[] __devinitdata
= {
361 .init_chipset
= init_chipset_cmd64x
,
362 .enablebits
= {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
363 .port_ops
= &cmd64x_port_ops
,
364 .host_flags
= IDE_HFLAG_CLEAR_SIMPLEX
|
365 IDE_HFLAG_ABUSE_PREFETCH
|
367 .pio_mask
= ATA_PIO5
,
368 .mwdma_mask
= ATA_MWDMA2
,
369 .udma_mask
= 0x00, /* no udma */
373 .init_chipset
= init_chipset_cmd64x
,
374 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
375 .port_ops
= &cmd648_port_ops
,
376 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
|
378 .pio_mask
= ATA_PIO5
,
379 .mwdma_mask
= ATA_MWDMA2
,
380 .udma_mask
= ATA_UDMA2
,
384 .init_chipset
= init_chipset_cmd64x
,
385 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
386 .port_ops
= &cmd648_port_ops
,
387 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
,
388 .pio_mask
= ATA_PIO5
,
389 .mwdma_mask
= ATA_MWDMA2
,
390 .udma_mask
= ATA_UDMA4
,
394 .init_chipset
= init_chipset_cmd64x
,
395 .enablebits
= {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
396 .port_ops
= &cmd648_port_ops
,
397 .host_flags
= IDE_HFLAG_ABUSE_PREFETCH
,
398 .pio_mask
= ATA_PIO5
,
399 .mwdma_mask
= ATA_MWDMA2
,
400 .udma_mask
= ATA_UDMA5
,
404 static int __devinit
cmd64x_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
406 struct ide_port_info d
;
407 u8 idx
= id
->driver_data
;
409 d
= cmd64x_chipsets
[idx
];
413 * UltraDMA only supported on PCI646U and PCI646U2, which
414 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
415 * Actually, although the CMD tech support people won't
416 * tell me the details, the 0x03 revision cannot support
417 * UDMA correctly without hardware modifications, and even
418 * then it only works with Quantum disks due to some
419 * hold time assumptions in the 646U part which are fixed
422 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
424 if (dev
->revision
< 5) {
427 * The original PCI0646 didn't have the primary
428 * channel enable bit, it appeared starting with
429 * PCI0646U (i.e. revision ID 3).
431 if (dev
->revision
< 3) {
432 d
.enablebits
[0].reg
= 0;
433 d
.port_ops
= &cmd64x_port_ops
;
434 if (dev
->revision
== 1)
435 d
.dma_ops
= &cmd646_rev1_dma_ops
;
440 return ide_pci_init_one(dev
, &d
, NULL
);
443 static const struct pci_device_id cmd64x_pci_tbl
[] = {
444 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_643
), 0 },
445 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_646
), 1 },
446 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_648
), 2 },
447 { PCI_VDEVICE(CMD
, PCI_DEVICE_ID_CMD_649
), 3 },
450 MODULE_DEVICE_TABLE(pci
, cmd64x_pci_tbl
);
452 static struct pci_driver cmd64x_pci_driver
= {
453 .name
= "CMD64x_IDE",
454 .id_table
= cmd64x_pci_tbl
,
455 .probe
= cmd64x_init_one
,
456 .remove
= ide_pci_remove
,
457 .suspend
= ide_pci_suspend
,
458 .resume
= ide_pci_resume
,
461 static int __init
cmd64x_ide_init(void)
463 return ide_pci_register_driver(&cmd64x_pci_driver
);
466 static void __exit
cmd64x_ide_exit(void)
468 pci_unregister_driver(&cmd64x_pci_driver
);
471 module_init(cmd64x_ide_init
);
472 module_exit(cmd64x_ide_exit
);
474 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
475 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
476 MODULE_LICENSE("GPL");