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[libata] sata_nv: add PCI IDs
[linux-2.6/linux-2.6-openrd.git] / drivers / scsi / sata_nv.c
blobd18e7e0932effc420c3fd0a21483dd1044bc4fdc
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 */
33
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.9"
48
49 enum {
50 NV_PORTS = 2,
51 NV_PIO_MASK = 0x1f,
52 NV_MWDMA_MASK = 0x07,
53 NV_UDMA_MASK = 0x7f,
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
56
57 /* INT_STATUS/ENABLE */
58 NV_INT_STATUS = 0x10,
59 NV_INT_ENABLE = 0x11,
60 NV_INT_STATUS_CK804 = 0x440,
61 NV_INT_ENABLE_CK804 = 0x441,
62
63 /* INT_STATUS/ENABLE bits */
64 NV_INT_DEV = 0x01,
65 NV_INT_PM = 0x02,
66 NV_INT_ADDED = 0x04,
67 NV_INT_REMOVED = 0x08,
68
69 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
70
71 NV_INT_ALL = 0x0f,
72 NV_INT_MASK = NV_INT_DEV |
73 NV_INT_ADDED | NV_INT_REMOVED,
74
75 /* INT_CONFIG */
76 NV_INT_CONFIG = 0x12,
77 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
78
79 // For PCI config register 20
80 NV_MCP_SATA_CFG_20 = 0x50,
81 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
82 };
83
84 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void nv_ck804_host_stop(struct ata_host_set *host_set);
86 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
87 struct pt_regs *regs);
88 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
89 struct pt_regs *regs);
90 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
91 struct pt_regs *regs);
92 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
93 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
94
95 static void nv_nf2_freeze(struct ata_port *ap);
96 static void nv_nf2_thaw(struct ata_port *ap);
97 static void nv_ck804_freeze(struct ata_port *ap);
98 static void nv_ck804_thaw(struct ata_port *ap);
99 static void nv_error_handler(struct ata_port *ap);
100
101 enum nv_host_type
102 {
103 GENERIC,
104 NFORCE2,
105 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
106 CK804
107 };
108
109 static const struct pci_device_id nv_pci_tbl[] = {
110 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
112 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
138 { PCI_VENDOR_ID_NVIDIA, 0x045c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
139 { PCI_VENDOR_ID_NVIDIA, 0x045d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
140 { PCI_VENDOR_ID_NVIDIA, 0x045e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
141 { PCI_VENDOR_ID_NVIDIA, 0x045f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
142 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
143 PCI_ANY_ID, PCI_ANY_ID,
144 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
145 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
146 PCI_ANY_ID, PCI_ANY_ID,
147 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
148 { 0, } /* terminate list */
149 };
150
151 static struct pci_driver nv_pci_driver = {
152 .name = DRV_NAME,
153 .id_table = nv_pci_tbl,
154 .probe = nv_init_one,
155 .remove = ata_pci_remove_one,
156 };
157
158 static struct scsi_host_template nv_sht = {
159 .module = THIS_MODULE,
160 .name = DRV_NAME,
161 .ioctl = ata_scsi_ioctl,
162 .queuecommand = ata_scsi_queuecmd,
163 .can_queue = ATA_DEF_QUEUE,
164 .this_id = ATA_SHT_THIS_ID,
165 .sg_tablesize = LIBATA_MAX_PRD,
166 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
167 .emulated = ATA_SHT_EMULATED,
168 .use_clustering = ATA_SHT_USE_CLUSTERING,
169 .proc_name = DRV_NAME,
170 .dma_boundary = ATA_DMA_BOUNDARY,
171 .slave_configure = ata_scsi_slave_config,
172 .slave_destroy = ata_scsi_slave_destroy,
173 .bios_param = ata_std_bios_param,
174 };
175
176 static const struct ata_port_operations nv_generic_ops = {
177 .port_disable = ata_port_disable,
178 .tf_load = ata_tf_load,
179 .tf_read = ata_tf_read,
180 .exec_command = ata_exec_command,
181 .check_status = ata_check_status,
182 .dev_select = ata_std_dev_select,
183 .bmdma_setup = ata_bmdma_setup,
184 .bmdma_start = ata_bmdma_start,
185 .bmdma_stop = ata_bmdma_stop,
186 .bmdma_status = ata_bmdma_status,
187 .qc_prep = ata_qc_prep,
188 .qc_issue = ata_qc_issue_prot,
189 .freeze = ata_bmdma_freeze,
190 .thaw = ata_bmdma_thaw,
191 .error_handler = nv_error_handler,
192 .post_internal_cmd = ata_bmdma_post_internal_cmd,
193 .data_xfer = ata_pio_data_xfer,
194 .irq_handler = nv_generic_interrupt,
195 .irq_clear = ata_bmdma_irq_clear,
196 .scr_read = nv_scr_read,
197 .scr_write = nv_scr_write,
198 .port_start = ata_port_start,
199 .port_stop = ata_port_stop,
200 .host_stop = ata_pci_host_stop,
201 };
202
203 static const struct ata_port_operations nv_nf2_ops = {
204 .port_disable = ata_port_disable,
205 .tf_load = ata_tf_load,
206 .tf_read = ata_tf_read,
207 .exec_command = ata_exec_command,
208 .check_status = ata_check_status,
209 .dev_select = ata_std_dev_select,
210 .bmdma_setup = ata_bmdma_setup,
211 .bmdma_start = ata_bmdma_start,
212 .bmdma_stop = ata_bmdma_stop,
213 .bmdma_status = ata_bmdma_status,
214 .qc_prep = ata_qc_prep,
215 .qc_issue = ata_qc_issue_prot,
216 .freeze = nv_nf2_freeze,
217 .thaw = nv_nf2_thaw,
218 .error_handler = nv_error_handler,
219 .post_internal_cmd = ata_bmdma_post_internal_cmd,
220 .data_xfer = ata_pio_data_xfer,
221 .irq_handler = nv_nf2_interrupt,
222 .irq_clear = ata_bmdma_irq_clear,
223 .scr_read = nv_scr_read,
224 .scr_write = nv_scr_write,
225 .port_start = ata_port_start,
226 .port_stop = ata_port_stop,
227 .host_stop = ata_pci_host_stop,
228 };
229
230 static const struct ata_port_operations nv_ck804_ops = {
231 .port_disable = ata_port_disable,
232 .tf_load = ata_tf_load,
233 .tf_read = ata_tf_read,
234 .exec_command = ata_exec_command,
235 .check_status = ata_check_status,
236 .dev_select = ata_std_dev_select,
237 .bmdma_setup = ata_bmdma_setup,
238 .bmdma_start = ata_bmdma_start,
239 .bmdma_stop = ata_bmdma_stop,
240 .bmdma_status = ata_bmdma_status,
241 .qc_prep = ata_qc_prep,
242 .qc_issue = ata_qc_issue_prot,
243 .freeze = nv_ck804_freeze,
244 .thaw = nv_ck804_thaw,
245 .error_handler = nv_error_handler,
246 .post_internal_cmd = ata_bmdma_post_internal_cmd,
247 .data_xfer = ata_pio_data_xfer,
248 .irq_handler = nv_ck804_interrupt,
249 .irq_clear = ata_bmdma_irq_clear,
250 .scr_read = nv_scr_read,
251 .scr_write = nv_scr_write,
252 .port_start = ata_port_start,
253 .port_stop = ata_port_stop,
254 .host_stop = nv_ck804_host_stop,
255 };
256
257 static struct ata_port_info nv_port_info[] = {
258 /* generic */
259 {
260 .sht = &nv_sht,
261 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
262 .pio_mask = NV_PIO_MASK,
263 .mwdma_mask = NV_MWDMA_MASK,
264 .udma_mask = NV_UDMA_MASK,
265 .port_ops = &nv_generic_ops,
266 },
267 /* nforce2/3 */
268 {
269 .sht = &nv_sht,
270 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
271 .pio_mask = NV_PIO_MASK,
272 .mwdma_mask = NV_MWDMA_MASK,
273 .udma_mask = NV_UDMA_MASK,
274 .port_ops = &nv_nf2_ops,
275 },
276 /* ck804 */
277 {
278 .sht = &nv_sht,
279 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
280 .pio_mask = NV_PIO_MASK,
281 .mwdma_mask = NV_MWDMA_MASK,
282 .udma_mask = NV_UDMA_MASK,
283 .port_ops = &nv_ck804_ops,
284 },
285 };
286
287 MODULE_AUTHOR("NVIDIA");
288 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
289 MODULE_LICENSE("GPL");
290 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
291 MODULE_VERSION(DRV_VERSION);
292
293 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
294 struct pt_regs *regs)
295 {
296 struct ata_host_set *host_set = dev_instance;
297 unsigned int i;
298 unsigned int handled = 0;
299 unsigned long flags;
300
301 spin_lock_irqsave(&host_set->lock, flags);
302
303 for (i = 0; i < host_set->n_ports; i++) {
304 struct ata_port *ap;
305
306 ap = host_set->ports[i];
307 if (ap &&
308 !(ap->flags & ATA_FLAG_DISABLED)) {
309 struct ata_queued_cmd *qc;
310
311 qc = ata_qc_from_tag(ap, ap->active_tag);
312 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
313 handled += ata_host_intr(ap, qc);
314 else
315 // No request pending? Clear interrupt status
316 // anyway, in case there's one pending.
317 ap->ops->check_status(ap);
318 }
319
320 }
321
322 spin_unlock_irqrestore(&host_set->lock, flags);
323
324 return IRQ_RETVAL(handled);
325 }
326
327 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
328 {
329 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
330 int handled;
331
332 /* freeze if hotplugged */
333 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
334 ata_port_freeze(ap);
335 return 1;
336 }
337
338 /* bail out if not our interrupt */
339 if (!(irq_stat & NV_INT_DEV))
340 return 0;
341
342 /* DEV interrupt w/ no active qc? */
343 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
344 ata_check_status(ap);
345 return 1;
346 }
347
348 /* handle interrupt */
349 handled = ata_host_intr(ap, qc);
350 if (unlikely(!handled)) {
351 /* spurious, clear it */
352 ata_check_status(ap);
353 }
354
355 return 1;
356 }
357
358 static irqreturn_t nv_do_interrupt(struct ata_host_set *host_set, u8 irq_stat)
359 {
360 int i, handled = 0;
361
362 for (i = 0; i < host_set->n_ports; i++) {
363 struct ata_port *ap = host_set->ports[i];
364
365 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
366 handled += nv_host_intr(ap, irq_stat);
367
368 irq_stat >>= NV_INT_PORT_SHIFT;
369 }
370
371 return IRQ_RETVAL(handled);
372 }
373
374 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
375 struct pt_regs *regs)
376 {
377 struct ata_host_set *host_set = dev_instance;
378 u8 irq_stat;
379 irqreturn_t ret;
380
381 spin_lock(&host_set->lock);
382 irq_stat = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
383 ret = nv_do_interrupt(host_set, irq_stat);
384 spin_unlock(&host_set->lock);
385
386 return ret;
387 }
388
389 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
390 struct pt_regs *regs)
391 {
392 struct ata_host_set *host_set = dev_instance;
393 u8 irq_stat;
394 irqreturn_t ret;
395
396 spin_lock(&host_set->lock);
397 irq_stat = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
398 ret = nv_do_interrupt(host_set, irq_stat);
399 spin_unlock(&host_set->lock);
400
401 return ret;
402 }
403
404 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
405 {
406 if (sc_reg > SCR_CONTROL)
407 return 0xffffffffU;
408
409 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
410 }
411
412 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
413 {
414 if (sc_reg > SCR_CONTROL)
415 return;
416
417 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
418 }
419
420 static void nv_nf2_freeze(struct ata_port *ap)
421 {
422 unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
423 int shift = ap->port_no * NV_INT_PORT_SHIFT;
424 u8 mask;
425
426 mask = inb(scr_addr + NV_INT_ENABLE);
427 mask &= ~(NV_INT_ALL << shift);
428 outb(mask, scr_addr + NV_INT_ENABLE);
429 }
430
431 static void nv_nf2_thaw(struct ata_port *ap)
432 {
433 unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
434 int shift = ap->port_no * NV_INT_PORT_SHIFT;
435 u8 mask;
436
437 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
438
439 mask = inb(scr_addr + NV_INT_ENABLE);
440 mask |= (NV_INT_MASK << shift);
441 outb(mask, scr_addr + NV_INT_ENABLE);
442 }
443
444 static void nv_ck804_freeze(struct ata_port *ap)
445 {
446 void __iomem *mmio_base = ap->host_set->mmio_base;
447 int shift = ap->port_no * NV_INT_PORT_SHIFT;
448 u8 mask;
449
450 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
451 mask &= ~(NV_INT_ALL << shift);
452 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
453 }
454
455 static void nv_ck804_thaw(struct ata_port *ap)
456 {
457 void __iomem *mmio_base = ap->host_set->mmio_base;
458 int shift = ap->port_no * NV_INT_PORT_SHIFT;
459 u8 mask;
460
461 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
462
463 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
464 mask |= (NV_INT_MASK << shift);
465 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
466 }
467
468 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
469 {
470 unsigned int dummy;
471
472 /* SATA hardreset fails to retrieve proper device signature on
473 * some controllers. Don't classify on hardreset. For more
474 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
475 */
476 return sata_std_hardreset(ap, &dummy);
477 }
478
479 static void nv_error_handler(struct ata_port *ap)
480 {
481 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
482 nv_hardreset, ata_std_postreset);
483 }
484
485 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
486 {
487 static int printed_version = 0;
488 struct ata_port_info *ppi;
489 struct ata_probe_ent *probe_ent;
490 int pci_dev_busy = 0;
491 int rc;
492 u32 bar;
493 unsigned long base;
494
495 // Make sure this is a SATA controller by counting the number of bars
496 // (NVIDIA SATA controllers will always have six bars). Otherwise,
497 // it's an IDE controller and we ignore it.
498 for (bar=0; bar<6; bar++)
499 if (pci_resource_start(pdev, bar) == 0)
500 return -ENODEV;
501
502 if (!printed_version++)
503 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
504
505 rc = pci_enable_device(pdev);
506 if (rc)
507 goto err_out;
508
509 rc = pci_request_regions(pdev, DRV_NAME);
510 if (rc) {
511 pci_dev_busy = 1;
512 goto err_out_disable;
513 }
514
515 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
516 if (rc)
517 goto err_out_regions;
518 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
519 if (rc)
520 goto err_out_regions;
521
522 rc = -ENOMEM;
523
524 ppi = &nv_port_info[ent->driver_data];
525 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
526 if (!probe_ent)
527 goto err_out_regions;
528
529 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
530 if (!probe_ent->mmio_base) {
531 rc = -EIO;
532 goto err_out_free_ent;
533 }
534
535 base = (unsigned long)probe_ent->mmio_base;
536
537 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
538 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
539
540 /* enable SATA space for CK804 */
541 if (ent->driver_data == CK804) {
542 u8 regval;
543
544 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
545 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
546 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
547 }
548
549 pci_set_master(pdev);
550
551 rc = ata_device_add(probe_ent);
552 if (rc != NV_PORTS)
553 goto err_out_iounmap;
554
555 kfree(probe_ent);
556
557 return 0;
558
559 err_out_iounmap:
560 pci_iounmap(pdev, probe_ent->mmio_base);
561 err_out_free_ent:
562 kfree(probe_ent);
563 err_out_regions:
564 pci_release_regions(pdev);
565 err_out_disable:
566 if (!pci_dev_busy)
567 pci_disable_device(pdev);
568 err_out:
569 return rc;
570 }
571
572 static void nv_ck804_host_stop(struct ata_host_set *host_set)
573 {
574 struct pci_dev *pdev = to_pci_dev(host_set->dev);
575 u8 regval;
576
577 /* disable SATA space for CK804 */
578 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
579 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
580 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
581
582 ata_pci_host_stop(host_set);
583 }
584
585 static int __init nv_init(void)
586 {
587 return pci_module_init(&nv_pci_driver);
588 }
589
590 static void __exit nv_exit(void)
591 {
592 pci_unregister_driver(&nv_pci_driver);
593 }
594
595 module_init(nv_init);
596 module_exit(nv_exit);
linux 2.6 git repository for openrd