arch/x86/kernel/setup_64.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  */
   4
   5 /*
   6  * This file handles the architecture-dependent parts of initialization
   7  */
   8
   9 #include <linux/errno.h>
  10 #include <linux/sched.h>
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/stddef.h>
  14 #include <linux/unistd.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/slab.h>
  17 #include <linux/user.h>
  18 #include <linux/screen_info.h>
  19 #include <linux/ioport.h>
  20 #include <linux/delay.h>
  21 #include <linux/init.h>
  22 #include <linux/initrd.h>
  23 #include <linux/highmem.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/module.h>
  26 #include <asm/processor.h>
  27 #include <linux/console.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/crash_dump.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/pci.h>
  32 #include <asm/pci-direct.h>
  33 #include <linux/efi.h>
  34 #include <linux/acpi.h>
  35 #include <linux/kallsyms.h>
  36 #include <linux/edd.h>
  37 #include <linux/iscsi_ibft.h>
  38 #include <linux/mmzone.h>
  39 #include <linux/kexec.h>
  40 #include <linux/cpufreq.h>
  41 #include <linux/dmi.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/ctype.h>
  44 #include <linux/sort.h>
  45 #include <linux/uaccess.h>
  46 #include <linux/init_ohci1394_dma.h>
  47 #include <linux/kvm_para.h>
  48
  49 #include <asm/mtrr.h>
  50 #include <asm/uaccess.h>
  51 #include <asm/system.h>
  52 #include <asm/vsyscall.h>
  53 #include <asm/io.h>
  54 #include <asm/smp.h>
  55 #include <asm/msr.h>
  56 #include <asm/desc.h>
  57 #include <video/edid.h>
  58 #include <asm/e820.h>
  59 #include <asm/mpspec.h>
  60 #include <asm/dma.h>
  61 #include <asm/gart.h>
  62 #include <asm/mpspec.h>
  63 #include <asm/mmu_context.h>
  64 #include <asm/proto.h>
  65 #include <asm/setup.h>
  66 #include <asm/numa.h>
  67 #include <asm/sections.h>
  68 #include <asm/dmi.h>
  69 #include <asm/cacheflush.h>
  70 #include <asm/mce.h>
  71 #include <asm/ds.h>
  72 #include <asm/topology.h>
  73 #include <asm/trampoline.h>
  74 #include <asm/pat.h>
  75
  76 #include <mach_apic.h>
  77 #ifdef CONFIG_PARAVIRT
  78 #include <asm/paravirt.h>
  79 #else
  80 #define ARCH_SETUP
  81 #endif
  82
  83 /*
  84  * Machine setup..
  85  */
  86
  87 struct cpuinfo_x86 boot_cpu_data __read_mostly;
  88 EXPORT_SYMBOL(boot_cpu_data);
  89
  90 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  91
  92 unsigned long mmu_cr4_features;
  93
  94 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  95 int bootloader_type;
  96
  97 unsigned long saved_video_mode;
  98
  99 int force_mwait __cpuinitdata;
 100
 101 /*
 102  * Early DMI memory
 103  */
 104 int dmi_alloc_index;
 105 char dmi_alloc_data[DMI_MAX_DATA];
 106
 107 /*
 108  * Setup options
 109  */
 110 struct screen_info screen_info;
 111 EXPORT_SYMBOL(screen_info);
 112 struct sys_desc_table_struct {
 113         unsigned short length;
 114         unsigned char table[0];
 115 };
 116
 117 struct edid_info edid_info;
 118 EXPORT_SYMBOL_GPL(edid_info);
 119
 120 extern int root_mountflags;
 121
 122 char __initdata command_line[COMMAND_LINE_SIZE];
 123
 124 static struct resource standard_io_resources[] = {
 125         { .name = "dma1", .start = 0x00, .end = 0x1f,
 126                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 127         { .name = "pic1", .start = 0x20, .end = 0x21,
 128                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 129         { .name = "timer0", .start = 0x40, .end = 0x43,
 130                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 131         { .name = "timer1", .start = 0x50, .end = 0x53,
 132                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 133         { .name = "keyboard", .start = 0x60, .end = 0x60,
 134                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 135         { .name = "keyboard", .start = 0x64, .end = 0x64,
 136                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 137         { .name = "dma page reg", .start = 0x80, .end = 0x8f,
 138                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 139         { .name = "pic2", .start = 0xa0, .end = 0xa1,
 140                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 141         { .name = "dma2", .start = 0xc0, .end = 0xdf,
 142                 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
 143         { .name = "fpu", .start = 0xf0, .end = 0xff,
 144                 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
 145 };
 146
 147 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
 148
 149 static struct resource data_resource = {
 150         .name = "Kernel data",
 151         .start = 0,
 152         .end = 0,
 153         .flags = IORESOURCE_RAM,
 154 };
 155 static struct resource code_resource = {
 156         .name = "Kernel code",
 157         .start = 0,
 158         .end = 0,
 159         .flags = IORESOURCE_RAM,
 160 };
 161 static struct resource bss_resource = {
 162         .name = "Kernel bss",
 163         .start = 0,
 164         .end = 0,
 165         .flags = IORESOURCE_RAM,
 166 };
 167
 168 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
 169
 170 #ifdef CONFIG_PROC_VMCORE
 171 /* elfcorehdr= specifies the location of elf core header
 172  * stored by the crashed kernel. This option will be passed
 173  * by kexec loader to the capture kernel.
 174  */
 175 static int __init setup_elfcorehdr(char *arg)
 176 {
 177         char *end;
 178         if (!arg)
 179                 return -EINVAL;
 180         elfcorehdr_addr = memparse(arg, &end);
 181         return end > arg ? 0 : -EINVAL;
 182 }
 183 early_param("elfcorehdr", setup_elfcorehdr);
 184 #endif
 185
 186 #ifndef CONFIG_NUMA
 187 static void __init
 188 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
 189 {
 190         unsigned long bootmap_size, bootmap;
 191
 192         bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
 193         bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
 194                                  PAGE_SIZE);
 195         if (bootmap == -1L)
 196                 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
 197         bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
 198         e820_register_active_regions(0, start_pfn, end_pfn);
 199         free_bootmem_with_active_regions(0, end_pfn);
 200         early_res_to_bootmem(0, end_pfn<<PAGE_SHIFT);
 201         reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
 202 }
 203 #endif
 204
 205 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
 206 struct edd edd;
 207 #ifdef CONFIG_EDD_MODULE
 208 EXPORT_SYMBOL(edd);
 209 #endif
 210 /**
 211  * copy_edd() - Copy the BIOS EDD information
 212  *              from boot_params into a safe place.
 213  *
 214  */
 215 static inline void copy_edd(void)
 216 {
 217      memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
 218             sizeof(edd.mbr_signature));
 219      memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
 220      edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
 221      edd.edd_info_nr = boot_params.eddbuf_entries;
 222 }
 223 #else
 224 static inline void copy_edd(void)
 225 {
 226 }
 227 #endif
 228
 229 #ifdef CONFIG_KEXEC
 230 static void __init reserve_crashkernel(void)
 231 {
 232         unsigned long long total_mem;
 233         unsigned long long crash_size, crash_base;
 234         int ret;
 235
 236         total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
 237
 238         ret = parse_crashkernel(boot_command_line, total_mem,
 239                         &crash_size, &crash_base);
 240         if (ret == 0 && crash_size) {
 241                 if (crash_base <= 0) {
 242                         printk(KERN_INFO "crashkernel reservation failed - "
 243                                         "you have to specify a base address\n");
 244                         return;
 245                 }
 246
 247                 if (reserve_bootmem(crash_base, crash_size,
 248                                         BOOTMEM_EXCLUSIVE) < 0) {
 249                         printk(KERN_INFO "crashkernel reservation failed - "
 250                                         "memory is in use\n");
 251                         return;
 252                 }
 253
 254                 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
 255                                 "for crashkernel (System RAM: %ldMB)\n",
 256                                 (unsigned long)(crash_size >> 20),
 257                                 (unsigned long)(crash_base >> 20),
 258                                 (unsigned long)(total_mem >> 20));
 259                 crashk_res.start = crash_base;
 260                 crashk_res.end   = crash_base + crash_size - 1;
 261                 insert_resource(&iomem_resource, &crashk_res);
 262         }
 263 }
 264 #else
 265 static inline void __init reserve_crashkernel(void)
 266 {}
 267 #endif
 268
 269 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
 270 void __attribute__((weak)) __init memory_setup(void)
 271 {
 272        machine_specific_memory_setup();
 273 }
 274
 275 #ifdef CONFIG_PCI_MMCONFIG
 276 extern void __cpuinit fam10h_check_enable_mmcfg(void);
 277 extern void __init check_enable_amd_mmconf_dmi(void);
 278 #else
 279 void __cpuinit fam10h_check_enable_mmcfg(void)
 280 {
 281 }
 282 void __init check_enable_amd_mmconf_dmi(void)
 283 {
 284 }
 285 #endif
 286
 287 /*
 288  * setup_arch - architecture-specific boot-time initializations
 289  *
 290  * Note: On x86_64, fixmaps are ready for use even before this is called.
 291  */
 292 void __init setup_arch(char **cmdline_p)
 293 {
 294         unsigned i;
 295
 296         printk(KERN_INFO "Command line: %s\n", boot_command_line);
 297
 298         ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
 299         screen_info = boot_params.screen_info;
 300         edid_info = boot_params.edid_info;
 301         saved_video_mode = boot_params.hdr.vid_mode;
 302         bootloader_type = boot_params.hdr.type_of_loader;
 303
 304 #ifdef CONFIG_BLK_DEV_RAM
 305         rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
 306         rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
 307         rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
 308 #endif
 309 #ifdef CONFIG_EFI
 310         if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
 311                      "EL64", 4)) {
 312                 efi_enabled = 1;
 313                 efi_reserve_early();
 314         }
 315 #endif
 316
 317         ARCH_SETUP
 318
 319         memory_setup();
 320         copy_edd();
 321
 322         if (!boot_params.hdr.root_flags)
 323                 root_mountflags &= ~MS_RDONLY;
 324         init_mm.start_code = (unsigned long) &_text;
 325         init_mm.end_code = (unsigned long) &_etext;
 326         init_mm.end_data = (unsigned long) &_edata;
 327         init_mm.brk = (unsigned long) &_end;
 328
 329         code_resource.start = virt_to_phys(&_text);
 330         code_resource.end = virt_to_phys(&_etext)-1;
 331         data_resource.start = virt_to_phys(&_etext);
 332         data_resource.end = virt_to_phys(&_edata)-1;
 333         bss_resource.start = virt_to_phys(&__bss_start);
 334         bss_resource.end = virt_to_phys(&__bss_stop)-1;
 335
 336         early_identify_cpu(&boot_cpu_data);
 337
 338         strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 339         *cmdline_p = command_line;
 340
 341         parse_setup_data();
 342
 343         parse_early_param();
 344
 345 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
 346         if (init_ohci1394_dma_early)
 347                 init_ohci1394_dma_on_all_controllers();
 348 #endif
 349
 350         finish_e820_parsing();
 351
 352         /* after parse_early_param, so could debug it */
 353         insert_resource(&iomem_resource, &code_resource);
 354         insert_resource(&iomem_resource, &data_resource);
 355         insert_resource(&iomem_resource, &bss_resource);
 356
 357         early_gart_iommu_check();
 358
 359         e820_register_active_regions(0, 0, -1UL);
 360         /*
 361          * partially used pages are not usable - thus
 362          * we are rounding upwards:
 363          */
 364         end_pfn = e820_end_of_ram();
 365
 366         /* pre allocte 4k for mptable mpc */
 367         early_reserve_e820_mpc_new();
 368         /* update e820 for memory not covered by WB MTRRs */
 369         mtrr_bp_init();
 370         if (mtrr_trim_uncached_memory(end_pfn)) {
 371                 e820_register_active_regions(0, 0, -1UL);
 372                 end_pfn = e820_end_of_ram();
 373         }
 374
 375         num_physpages = end_pfn;
 376
 377         check_efer();
 378
 379         max_pfn_mapped = init_memory_mapping(0, (end_pfn << PAGE_SHIFT));
 380         if (efi_enabled)
 381                 efi_init();
 382
 383         vsmp_init();
 384
 385         dmi_scan_machine();
 386
 387         io_delay_init();
 388
 389 #ifdef CONFIG_KVM_CLOCK
 390         kvmclock_init();
 391 #endif
 392
 393 #ifdef CONFIG_SMP
 394         /* setup to use the early static init tables during kernel startup */
 395         x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
 396         x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
 397 #ifdef CONFIG_NUMA
 398         x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
 399 #endif
 400 #endif
 401
 402 #ifdef CONFIG_ACPI
 403         /*
 404          * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
 405          * Call this early for SRAT node setup.
 406          */
 407         acpi_boot_table_init();
 408 #endif
 409
 410         /* How many end-of-memory variables you have, grandma! */
 411         max_low_pfn = end_pfn;
 412         max_pfn = end_pfn;
 413         high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
 414
 415         /* Remove active ranges so rediscovery with NUMA-awareness happens */
 416         remove_all_active_ranges();
 417
 418 #ifdef CONFIG_ACPI_NUMA
 419         /*
 420          * Parse SRAT to discover nodes.
 421          */
 422         acpi_numa_init();
 423 #endif
 424
 425 #ifdef CONFIG_NUMA
 426         numa_initmem_init(0, end_pfn);
 427 #else
 428         contig_initmem_init(0, end_pfn);
 429 #endif
 430
 431         dma32_reserve_bootmem();
 432
 433 #ifdef CONFIG_ACPI_SLEEP
 434         /*
 435          * Reserve low memory region for sleep support.
 436          */
 437        acpi_reserve_bootmem();
 438 #endif
 439
 440 #ifdef CONFIG_X86_MPPARSE
 441        /*
 442         * Find and reserve possible boot-time SMP configuration:
 443         */
 444         find_smp_config();
 445 #endif
 446 #ifdef CONFIG_BLK_DEV_INITRD
 447         if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
 448                 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
 449                 unsigned long ramdisk_size  = boot_params.hdr.ramdisk_size;
 450                 unsigned long ramdisk_end   = ramdisk_image + ramdisk_size;
 451                 unsigned long end_of_mem    = end_pfn << PAGE_SHIFT;
 452
 453                 if (ramdisk_end <= end_of_mem) {
 454                         /*
 455                          * don't need to reserve again, already reserved early
 456                          * in x86_64_start_kernel, and early_res_to_bootmem
 457                          * convert that to reserved in bootmem
 458                          */
 459                         initrd_start = ramdisk_image + PAGE_OFFSET;
 460                         initrd_end = initrd_start+ramdisk_size;
 461                 } else {
 462                         free_bootmem(ramdisk_image, ramdisk_size);
 463                         printk(KERN_ERR "initrd extends beyond end of memory "
 464                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 465                                ramdisk_end, end_of_mem);
 466                         initrd_start = 0;
 467                 }
 468         }
 469 #endif
 470         reserve_crashkernel();
 471
 472         reserve_ibft_region();
 473
 474         paging_init();
 475         map_vsyscall();
 476
 477         early_quirks();
 478
 479 #ifdef CONFIG_ACPI
 480         /*
 481          * Read APIC and some other early information from ACPI tables.
 482          */
 483         acpi_boot_init();
 484 #endif
 485
 486         init_cpu_to_node();
 487
 488 #ifdef CONFIG_X86_MPPARSE
 489         /*
 490          * get boot-time SMP configuration:
 491          */
 492         if (smp_found_config)
 493                 get_smp_config();
 494 #endif
 495         init_apic_mappings();
 496         ioapic_init_mappings();
 497
 498         kvm_guest_init();
 499
 500         /*
 501          * We trust e820 completely. No explicit ROM probing in memory.
 502          */
 503         e820_reserve_resources();
 504         e820_mark_nosave_regions(end_pfn);
 505
 506         /* request I/O space for devices used on all i[345]86 PCs */
 507         for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
 508                 request_resource(&ioport_resource, &standard_io_resources[i]);
 509
 510         e820_setup_gap();
 511
 512 #ifdef CONFIG_VT
 513 #if defined(CONFIG_VGA_CONSOLE)
 514         if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
 515                 conswitchp = &vga_con;
 516 #elif defined(CONFIG_DUMMY_CONSOLE)
 517         conswitchp = &dummy_con;
 518 #endif
 519 #endif
 520
 521         /* do this before identify_cpu for boot cpu */
 522         check_enable_amd_mmconf_dmi();
 523 }
 524
 525 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 526 {
 527         unsigned int *v;
 528
 529         if (c->extended_cpuid_level < 0x80000004)
 530                 return 0;
 531
 532         v = (unsigned int *) c->x86_model_id;
 533         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 534         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 535         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 536         c->x86_model_id[48] = 0;
 537         return 1;
 538 }
 539
 540
 541 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 542 {
 543         unsigned int n, dummy, eax, ebx, ecx, edx;
 544
 545         n = c->extended_cpuid_level;
 546
 547         if (n >= 0x80000005) {
 548                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 549                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
 550                        "D cache %dK (%d bytes/line)\n",
 551                        edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 552                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 553                 /* On K8 L1 TLB is inclusive, so don't count it */
 554                 c->x86_tlbsize = 0;
 555         }
 556
 557         if (n >= 0x80000006) {
 558                 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 559                 ecx = cpuid_ecx(0x80000006);
 560                 c->x86_cache_size = ecx >> 16;
 561                 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 562
 563                 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 564                 c->x86_cache_size, ecx & 0xFF);
 565         }
 566         if (n >= 0x80000008) {
 567                 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
 568                 c->x86_virt_bits = (eax >> 8) & 0xff;
 569                 c->x86_phys_bits = eax & 0xff;
 570         }
 571 }
 572
 573 #ifdef CONFIG_NUMA
 574 static int __cpuinit nearby_node(int apicid)
 575 {
 576         int i, node;
 577
 578         for (i = apicid - 1; i >= 0; i--) {
 579                 node = apicid_to_node[i];
 580                 if (node != NUMA_NO_NODE && node_online(node))
 581                         return node;
 582         }
 583         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 584                 node = apicid_to_node[i];
 585                 if (node != NUMA_NO_NODE && node_online(node))
 586                         return node;
 587         }
 588         return first_node(node_online_map); /* Shouldn't happen */
 589 }
 590 #endif
 591
 592 /*
 593  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 594  * Assumes number of cores is a power of two.
 595  */
 596 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 597 {
 598 #ifdef CONFIG_SMP
 599         unsigned bits;
 600 #ifdef CONFIG_NUMA
 601         int cpu = smp_processor_id();
 602         int node = 0;
 603         unsigned apicid = hard_smp_processor_id();
 604 #endif
 605         bits = c->x86_coreid_bits;
 606
 607         /* Low order bits define the core id (index of core in socket) */
 608         c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 609         /* Convert the initial APIC ID into the socket ID */
 610         c->phys_proc_id = c->initial_apicid >> bits;
 611
 612 #ifdef CONFIG_NUMA
 613         node = c->phys_proc_id;
 614         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 615                 node = apicid_to_node[apicid];
 616         if (!node_online(node)) {
 617                 /* Two possibilities here:
 618                    - The CPU is missing memory and no node was created.
 619                    In that case try picking one from a nearby CPU
 620                    - The APIC IDs differ from the HyperTransport node IDs
 621                    which the K8 northbridge parsing fills in.
 622                    Assume they are all increased by a constant offset,
 623                    but in the same order as the HT nodeids.
 624                    If that doesn't result in a usable node fall back to the
 625                    path for the previous case.  */
 626
 627                 int ht_nodeid = c->initial_apicid;
 628
 629                 if (ht_nodeid >= 0 &&
 630                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 631                         node = apicid_to_node[ht_nodeid];
 632                 /* Pick a nearby node */
 633                 if (!node_online(node))
 634                         node = nearby_node(apicid);
 635         }
 636         numa_set_node(cpu, node);
 637
 638         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 639 #endif
 640 #endif
 641 }
 642
 643 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 644 {
 645 #ifdef CONFIG_SMP
 646         unsigned bits, ecx;
 647
 648         /* Multi core CPU? */
 649         if (c->extended_cpuid_level < 0x80000008)
 650                 return;
 651
 652         ecx = cpuid_ecx(0x80000008);
 653
 654         c->x86_max_cores = (ecx & 0xff) + 1;
 655
 656         /* CPU telling us the core id bits shift? */
 657         bits = (ecx >> 12) & 0xF;
 658
 659         /* Otherwise recompute */
 660         if (bits == 0) {
 661                 while ((1 << bits) < c->x86_max_cores)
 662                         bits++;
 663         }
 664
 665         c->x86_coreid_bits = bits;
 666
 667 #endif
 668 }
 669
 670 #define ENABLE_C1E_MASK         0x18000000
 671 #define CPUID_PROCESSOR_SIGNATURE       1
 672 #define CPUID_XFAM              0x0ff00000
 673 #define CPUID_XFAM_K8           0x00000000
 674 #define CPUID_XFAM_10H          0x00100000
 675 #define CPUID_XFAM_11H          0x00200000
 676 #define CPUID_XMOD              0x000f0000
 677 #define CPUID_XMOD_REV_F        0x00040000
 678
 679 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
 680 static __cpuinit int amd_apic_timer_broken(void)
 681 {
 682         u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
 683
 684         switch (eax & CPUID_XFAM) {
 685         case CPUID_XFAM_K8:
 686                 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
 687                         break;
 688         case CPUID_XFAM_10H:
 689         case CPUID_XFAM_11H:
 690                 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
 691                 if (lo & ENABLE_C1E_MASK)
 692                         return 1;
 693                 break;
 694         default:
 695                 /* err on the side of caution */
 696                 return 1;
 697         }
 698         return 0;
 699 }
 700
 701 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 702 {
 703         early_init_amd_mc(c);
 704
 705         /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
 706         if (c->x86_power & (1<<8))
 707                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 708 }
 709
 710 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 711 {
 712         unsigned level;
 713
 714 #ifdef CONFIG_SMP
 715         unsigned long value;
 716
 717         /*
 718          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 719          * bit 6 of msr C001_0015
 720          *
 721          * Errata 63 for SH-B3 steppings
 722          * Errata 122 for all steppings (F+ have it disabled by default)
 723          */
 724         if (c->x86 == 15) {
 725                 rdmsrl(MSR_K8_HWCR, value);
 726                 value |= 1 << 6;
 727                 wrmsrl(MSR_K8_HWCR, value);
 728         }
 729 #endif
 730
 731         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 732            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 733         clear_cpu_cap(c, 0*32+31);
 734
 735         /* On C+ stepping K8 rep microcode works well for copy/memset */
 736         level = cpuid_eax(1);
 737         if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
 738                              level >= 0x0f58))
 739                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 740         if (c->x86 == 0x10 || c->x86 == 0x11)
 741                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 742
 743         /* Enable workaround for FXSAVE leak */
 744         if (c->x86 >= 6)
 745                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 746
 747         level = get_model_name(c);
 748         if (!level) {
 749                 switch (c->x86) {
 750                 case 15:
 751                         /* Should distinguish Models here, but this is only
 752                            a fallback anyways. */
 753                         strcpy(c->x86_model_id, "Hammer");
 754                         break;
 755                 }
 756         }
 757         display_cacheinfo(c);
 758
 759         /* Multi core CPU? */
 760         if (c->extended_cpuid_level >= 0x80000008)
 761                 amd_detect_cmp(c);
 762
 763         if (c->extended_cpuid_level >= 0x80000006 &&
 764                 (cpuid_edx(0x80000006) & 0xf000))
 765                 num_cache_leaves = 4;
 766         else
 767                 num_cache_leaves = 3;
 768
 769         if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
 770                 set_cpu_cap(c, X86_FEATURE_K8);
 771
 772         /* MFENCE stops RDTSC speculation */
 773         set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 774
 775         if (c->x86 == 0x10)
 776                 fam10h_check_enable_mmcfg();
 777
 778         if (amd_apic_timer_broken())
 779                 disable_apic_timer = 1;
 780
 781         if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
 782                 unsigned long long tseg;
 783
 784                 /*
 785                  * Split up direct mapping around the TSEG SMM area.
 786                  * Don't do it for gbpages because there seems very little
 787                  * benefit in doing so.
 788                  */
 789                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg) &&
 790                 (tseg >> PMD_SHIFT) < (max_pfn_mapped >> (PMD_SHIFT-PAGE_SHIFT)))
 791                         set_memory_4k((unsigned long)__va(tseg), 1);
 792         }
 793 }
 794
 795 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 796 {
 797 #ifdef CONFIG_SMP
 798         u32 eax, ebx, ecx, edx;
 799         int index_msb, core_bits;
 800
 801         cpuid(1, &eax, &ebx, &ecx, &edx);
 802
 803
 804         if (!cpu_has(c, X86_FEATURE_HT))
 805                 return;
 806         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 807                 goto out;
 808
 809         smp_num_siblings = (ebx & 0xff0000) >> 16;
 810
 811         if (smp_num_siblings == 1) {
 812                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 813         } else if (smp_num_siblings > 1) {
 814
 815                 if (smp_num_siblings > NR_CPUS) {
 816                         printk(KERN_WARNING "CPU: Unsupported number of "
 817                                "siblings %d", smp_num_siblings);
 818                         smp_num_siblings = 1;
 819                         return;
 820                 }
 821
 822                 index_msb = get_count_order(smp_num_siblings);
 823                 c->phys_proc_id = phys_pkg_id(index_msb);
 824
 825                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 826
 827                 index_msb = get_count_order(smp_num_siblings);
 828
 829                 core_bits = get_count_order(c->x86_max_cores);
 830
 831                 c->cpu_core_id = phys_pkg_id(index_msb) &
 832                                                ((1 << core_bits) - 1);
 833         }
 834 out:
 835         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 836                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 837                        c->phys_proc_id);
 838                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 839                        c->cpu_core_id);
 840         }
 841
 842 #endif
 843 }
 844
 845 /*
 846  * find out the number of processor cores on the die
 847  */
 848 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 849 {
 850         unsigned int eax, t;
 851
 852         if (c->cpuid_level < 4)
 853                 return 1;
 854
 855         cpuid_count(4, 0, &eax, &t, &t, &t);
 856
 857         if (eax & 0x1f)
 858                 return ((eax >> 26) + 1);
 859         else
 860                 return 1;
 861 }
 862
 863 static void __cpuinit srat_detect_node(void)
 864 {
 865 #ifdef CONFIG_NUMA
 866         unsigned node;
 867         int cpu = smp_processor_id();
 868         int apicid = hard_smp_processor_id();
 869
 870         /* Don't do the funky fallback heuristics the AMD version employs
 871            for now. */
 872         node = apicid_to_node[apicid];
 873         if (node == NUMA_NO_NODE || !node_online(node))
 874                 node = first_node(node_online_map);
 875         numa_set_node(cpu, node);
 876
 877         printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
 878 #endif
 879 }
 880
 881 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 882 {
 883         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
 884             (c->x86 == 0x6 && c->x86_model >= 0x0e))
 885                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 886 }
 887
 888 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 889 {
 890         /* Cache sizes */
 891         unsigned n;
 892
 893         init_intel_cacheinfo(c);
 894         if (c->cpuid_level > 9) {
 895                 unsigned eax = cpuid_eax(10);
 896                 /* Check for version and the number of counters */
 897                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 898                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 899         }
 900
 901         if (cpu_has_ds) {
 902                 unsigned int l1, l2;
 903                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 904                 if (!(l1 & (1<<11)))
 905                         set_cpu_cap(c, X86_FEATURE_BTS);
 906                 if (!(l1 & (1<<12)))
 907                         set_cpu_cap(c, X86_FEATURE_PEBS);
 908         }
 909
 910
 911         if (cpu_has_bts)
 912                 ds_init_intel(c);
 913
 914         n = c->extended_cpuid_level;
 915         if (n >= 0x80000008) {
 916                 unsigned eax = cpuid_eax(0x80000008);
 917                 c->x86_virt_bits = (eax >> 8) & 0xff;
 918                 c->x86_phys_bits = eax & 0xff;
 919                 /* CPUID workaround for Intel 0F34 CPU */
 920                 if (c->x86_vendor == X86_VENDOR_INTEL &&
 921                     c->x86 == 0xF && c->x86_model == 0x3 &&
 922                     c->x86_mask == 0x4)
 923                         c->x86_phys_bits = 36;
 924         }
 925
 926         if (c->x86 == 15)
 927                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 928         if (c->x86 == 6)
 929                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 930         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 931         c->x86_max_cores = intel_num_cpu_cores(c);
 932
 933         srat_detect_node();
 934 }
 935
 936 static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
 937 {
 938         if (c->x86 == 0x6 && c->x86_model >= 0xf)
 939                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 940 }
 941
 942 static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
 943 {
 944         /* Cache sizes */
 945         unsigned n;
 946
 947         n = c->extended_cpuid_level;
 948         if (n >= 0x80000008) {
 949                 unsigned eax = cpuid_eax(0x80000008);
 950                 c->x86_virt_bits = (eax >> 8) & 0xff;
 951                 c->x86_phys_bits = eax & 0xff;
 952         }
 953
 954         if (c->x86 == 0x6 && c->x86_model >= 0xf) {
 955                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 956                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 957                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 958         }
 959         set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 960 }
 961
 962 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 963 {
 964         char *v = c->x86_vendor_id;
 965
 966         if (!strcmp(v, "AuthenticAMD"))
 967                 c->x86_vendor = X86_VENDOR_AMD;
 968         else if (!strcmp(v, "GenuineIntel"))
 969                 c->x86_vendor = X86_VENDOR_INTEL;
 970         else if (!strcmp(v, "CentaurHauls"))
 971                 c->x86_vendor = X86_VENDOR_CENTAUR;
 972         else
 973                 c->x86_vendor = X86_VENDOR_UNKNOWN;
 974 }
 975
 976 /* Do some early cpuid on the boot CPU to get some parameter that are
 977    needed before check_bugs. Everything advanced is in identify_cpu
 978    below. */
 979 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
 980 {
 981         u32 tfms, xlvl;
 982
 983         c->loops_per_jiffy = loops_per_jiffy;
 984         c->x86_cache_size = -1;
 985         c->x86_vendor = X86_VENDOR_UNKNOWN;
 986         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 987         c->x86_vendor_id[0] = '\0'; /* Unset */
 988         c->x86_model_id[0] = '\0';  /* Unset */
 989         c->x86_clflush_size = 64;
 990         c->x86_cache_alignment = c->x86_clflush_size;
 991         c->x86_max_cores = 1;
 992         c->x86_coreid_bits = 0;
 993         c->extended_cpuid_level = 0;
 994         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 995
 996         /* Get vendor name */
 997         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 998               (unsigned int *)&c->x86_vendor_id[0],
 999               (unsigned int *)&c->x86_vendor_id[8],
1000               (unsigned int *)&c->x86_vendor_id[4]);
1001
1002         get_cpu_vendor(c);
1003
1004         /* Initialize the standard set of capabilities */
1005         /* Note that the vendor-specific code below might override */
1006
1007         /* Intel-defined flags: level 0x00000001 */
1008         if (c->cpuid_level >= 0x00000001) {
1009                 __u32 misc;
1010                 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
1011                       &c->x86_capability[0]);
1012                 c->x86 = (tfms >> 8) & 0xf;
1013                 c->x86_model = (tfms >> 4) & 0xf;
1014                 c->x86_mask = tfms & 0xf;
1015                 if (c->x86 == 0xf)
1016                         c->x86 += (tfms >> 20) & 0xff;
1017                 if (c->x86 >= 0x6)
1018                         c->x86_model += ((tfms >> 16) & 0xF) << 4;
1019                 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
1020                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
1021         } else {
1022                 /* Have CPUID level 0 only - unheard of */
1023                 c->x86 = 4;
1024         }
1025
1026         c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xff;
1027 #ifdef CONFIG_SMP
1028         c->phys_proc_id = c->initial_apicid;
1029 #endif
1030         /* AMD-defined flags: level 0x80000001 */
1031         xlvl = cpuid_eax(0x80000000);
1032         c->extended_cpuid_level = xlvl;
1033         if ((xlvl & 0xffff0000) == 0x80000000) {
1034                 if (xlvl >= 0x80000001) {
1035                         c->x86_capability[1] = cpuid_edx(0x80000001);
1036                         c->x86_capability[6] = cpuid_ecx(0x80000001);
1037                 }
1038                 if (xlvl >= 0x80000004)
1039                         get_model_name(c); /* Default name */
1040         }
1041
1042         /* Transmeta-defined flags: level 0x80860001 */
1043         xlvl = cpuid_eax(0x80860000);
1044         if ((xlvl & 0xffff0000) == 0x80860000) {
1045                 /* Don't set x86_cpuid_level here for now to not confuse. */
1046                 if (xlvl >= 0x80860001)
1047                         c->x86_capability[2] = cpuid_edx(0x80860001);
1048         }
1049
1050         c->extended_cpuid_level = cpuid_eax(0x80000000);
1051         if (c->extended_cpuid_level >= 0x80000007)
1052                 c->x86_power = cpuid_edx(0x80000007);
1053
1054         switch (c->x86_vendor) {
1055         case X86_VENDOR_AMD:
1056                 early_init_amd(c);
1057                 break;
1058         case X86_VENDOR_INTEL:
1059                 early_init_intel(c);
1060                 break;
1061         case X86_VENDOR_CENTAUR:
1062                 early_init_centaur(c);
1063                 break;
1064         }
1065
1066         validate_pat_support(c);
1067 }
1068
1069 /*
1070  * This does the hard work of actually picking apart the CPU stuff...
1071  */
1072 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
1073 {
1074         int i;
1075
1076         early_identify_cpu(c);
1077
1078         init_scattered_cpuid_features(c);
1079
1080         c->apicid = phys_pkg_id(0);
1081
1082         /*
1083          * Vendor-specific initialization.  In this section we
1084          * canonicalize the feature flags, meaning if there are
1085          * features a certain CPU supports which CPUID doesn't
1086          * tell us, CPUID claiming incorrect flags, or other bugs,
1087          * we handle them here.
1088          *
1089          * At the end of this section, c->x86_capability better
1090          * indicate the features this CPU genuinely supports!
1091          */
1092         switch (c->x86_vendor) {
1093         case X86_VENDOR_AMD:
1094                 init_amd(c);
1095                 break;
1096
1097         case X86_VENDOR_INTEL:
1098                 init_intel(c);
1099                 break;
1100
1101         case X86_VENDOR_CENTAUR:
1102                 init_centaur(c);
1103                 break;
1104
1105         case X86_VENDOR_UNKNOWN:
1106         default:
1107                 display_cacheinfo(c);
1108                 break;
1109         }
1110
1111         detect_ht(c);
1112
1113         /*
1114          * On SMP, boot_cpu_data holds the common feature set between
1115          * all CPUs; so make sure that we indicate which features are
1116          * common between the CPUs.  The first time this routine gets
1117          * executed, c == &boot_cpu_data.
1118          */
1119         if (c != &boot_cpu_data) {
1120                 /* AND the already accumulated flags with these */
1121                 for (i = 0; i < NCAPINTS; i++)
1122                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1123         }
1124
1125         /* Clear all flags overriden by options */
1126         for (i = 0; i < NCAPINTS; i++)
1127                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
1128
1129 #ifdef CONFIG_X86_MCE
1130         mcheck_init(c);
1131 #endif
1132         select_idle_routine(c);
1133
1134 #ifdef CONFIG_NUMA
1135         numa_add_cpu(smp_processor_id());
1136 #endif
1137
1138 }
1139
1140 void __cpuinit identify_boot_cpu(void)
1141 {
1142         identify_cpu(&boot_cpu_data);
1143 }
1144
1145 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
1146 {
1147         BUG_ON(c == &boot_cpu_data);
1148         identify_cpu(c);
1149         mtrr_ap_init();
1150 }
1151
1152 static __init int setup_noclflush(char *arg)
1153 {
1154         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1155         return 1;
1156 }
1157 __setup("noclflush", setup_noclflush);
1158
1159 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1160 {
1161         if (c->x86_model_id[0])
1162                 printk(KERN_CONT "%s", c->x86_model_id);
1163
1164         if (c->x86_mask || c->cpuid_level >= 0)
1165                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1166         else
1167                 printk(KERN_CONT "\n");
1168 }
1169
1170 static __init int setup_disablecpuid(char *arg)
1171 {
1172         int bit;
1173         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1174                 setup_clear_cpu_cap(bit);
1175         else
1176                 return 0;
1177         return 1;
1178 }
1179 __setup("clearcpuid=", setup_disablecpuid);