1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 * Driver for SFP+ and XFP optical PHYs plus some support specific to the
11 * AMCC QT20xx adapters; see www.amcc.com for details
14 #include <linux/timer.h>
15 #include <linux/delay.h>
22 #define XFP_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PCS | \
23 MDIO_MMDREG_DEVS_PMAPMD | \
24 MDIO_MMDREG_DEVS_PHYXS)
26 #define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) | \
27 (1 << LOOPBACK_PMAPMD) | \
28 (1 << LOOPBACK_NETWORK))
30 /****************************************************************************/
31 /* Quake-specific MDIO registers */
32 #define MDIO_QUAKE_LED0_REG (0xD006)
35 #define PCS_FW_HEARTBEAT_REG 0xd7ee
36 #define PCS_FW_HEARTB_LBN 0
37 #define PCS_FW_HEARTB_WIDTH 8
38 #define PCS_UC8051_STATUS_REG 0xd7fd
39 #define PCS_UC_STATUS_LBN 0
40 #define PCS_UC_STATUS_WIDTH 8
41 #define PCS_UC_STATUS_FW_SAVE 0x20
42 #define PMA_PMD_FTX_CTRL2_REG 0xc309
43 #define PMA_PMD_FTX_STATIC_LBN 13
44 #define PMA_PMD_VEND1_REG 0xc001
45 #define PMA_PMD_VEND1_LBTXD_LBN 15
46 #define PCS_VEND1_REG 0xc000
47 #define PCS_VEND1_LBTXD_LBN 5
49 void xfp_set_led(struct efx_nic
*p
, int led
, int mode
)
51 int addr
= MDIO_QUAKE_LED0_REG
+ led
;
52 mdio_clause45_write(p
, p
->mii
.phy_id
, MDIO_MMD_PMAPMD
, addr
,
57 enum efx_phy_mode phy_mode
;
60 #define XFP_MAX_RESET_TIME 500
61 #define XFP_RESET_WAIT 10
63 static int qt2025c_wait_reset(struct efx_nic
*efx
)
65 unsigned long timeout
= jiffies
+ 10 * HZ
;
66 int phy_id
= efx
->mii
.phy_id
;
67 int reg
, old_counter
= 0;
69 /* Wait for firmware heartbeat to start */
72 reg
= mdio_clause45_read(efx
, phy_id
, MDIO_MMD_PCS
,
73 PCS_FW_HEARTBEAT_REG
);
76 counter
= ((reg
>> PCS_FW_HEARTB_LBN
) &
77 ((1 << PCS_FW_HEARTB_WIDTH
) - 1));
79 old_counter
= counter
;
80 else if (counter
!= old_counter
)
82 if (time_after(jiffies
, timeout
))
87 /* Wait for firmware status to look good */
89 reg
= mdio_clause45_read(efx
, phy_id
, MDIO_MMD_PCS
,
90 PCS_UC8051_STATUS_REG
);
94 ((1 << PCS_UC_STATUS_WIDTH
) - 1) << PCS_UC_STATUS_LBN
) >=
95 PCS_UC_STATUS_FW_SAVE
)
97 if (time_after(jiffies
, timeout
))
105 /* Reset the PHYXS MMD. This is documented (for the Quake PHYs) as doing
106 * a complete soft reset.
108 static int xfp_reset_phy(struct efx_nic
*efx
)
112 rc
= mdio_clause45_reset_mmd(efx
, MDIO_MMD_PHYXS
,
113 XFP_MAX_RESET_TIME
/ XFP_RESET_WAIT
,
118 if (efx
->phy_type
== PHY_TYPE_QT2025C
) {
119 rc
= qt2025c_wait_reset(efx
);
124 /* Wait 250ms for the PHY to complete bootup */
127 /* Check that all the MMDs we expect are present and responding. We
128 * expect faults on some if the link is down, but not on the PHY XS */
129 rc
= mdio_clause45_check_mmds(efx
, XFP_REQUIRED_DEVS
,
130 MDIO_MMDREG_DEVS_PHYXS
);
134 efx
->board_info
.init_leds(efx
);
139 EFX_ERR(efx
, "PHY reset timed out\n");
143 static int xfp_phy_init(struct efx_nic
*efx
)
145 struct xfp_phy_data
*phy_data
;
146 u32 devid
= mdio_clause45_read_id(efx
, MDIO_MMD_PHYXS
);
149 phy_data
= kzalloc(sizeof(struct xfp_phy_data
), GFP_KERNEL
);
152 efx
->phy_data
= phy_data
;
154 EFX_INFO(efx
, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
155 devid
, mdio_id_oui(devid
), mdio_id_model(devid
),
158 phy_data
->phy_mode
= efx
->phy_mode
;
160 rc
= xfp_reset_phy(efx
);
162 EFX_INFO(efx
, "PHY init %s.\n",
163 rc
? "failed" : "successful");
170 kfree(efx
->phy_data
);
171 efx
->phy_data
= NULL
;
175 static void xfp_phy_clear_interrupt(struct efx_nic
*efx
)
177 xenpack_clear_lasi_irqs(efx
);
180 static int xfp_link_ok(struct efx_nic
*efx
)
182 return mdio_clause45_links_ok(efx
, XFP_REQUIRED_DEVS
);
185 static void xfp_phy_poll(struct efx_nic
*efx
)
187 int link_up
= xfp_link_ok(efx
);
188 /* Simulate a PHY event if link state has changed */
189 if (link_up
!= efx
->link_up
)
190 falcon_sim_phy_event(efx
);
193 static void xfp_phy_reconfigure(struct efx_nic
*efx
)
195 struct xfp_phy_data
*phy_data
= efx
->phy_data
;
197 if (efx
->phy_type
== PHY_TYPE_QT2025C
) {
198 /* There are several different register bits which can
199 * disable TX (and save power) on direct-attach cables
200 * or optical transceivers, varying somewhat between
201 * firmware versions. Only 'static mode' appears to
202 * cover everything. */
203 mdio_clause45_set_flag(
204 efx
, efx
->mii
.phy_id
, MDIO_MMD_PMAPMD
,
205 PMA_PMD_FTX_CTRL2_REG
, PMA_PMD_FTX_STATIC_LBN
,
206 efx
->phy_mode
& PHY_MODE_TX_DISABLED
||
207 efx
->phy_mode
& PHY_MODE_LOW_POWER
||
208 efx
->loopback_mode
== LOOPBACK_PCS
||
209 efx
->loopback_mode
== LOOPBACK_PMAPMD
);
211 /* Reset the PHY when moving from tx off to tx on */
212 if (!(efx
->phy_mode
& PHY_MODE_TX_DISABLED
) &&
213 (phy_data
->phy_mode
& PHY_MODE_TX_DISABLED
))
216 mdio_clause45_transmit_disable(efx
);
219 mdio_clause45_phy_reconfigure(efx
);
221 phy_data
->phy_mode
= efx
->phy_mode
;
222 efx
->link_up
= xfp_link_ok(efx
);
223 efx
->link_speed
= 10000;
225 efx
->link_fc
= efx
->wanted_fc
;
229 static void xfp_phy_fini(struct efx_nic
*efx
)
231 /* Clobber the LED if it was blinking */
232 efx
->board_info
.blink(efx
, false);
234 /* Free the context block */
235 kfree(efx
->phy_data
);
236 efx
->phy_data
= NULL
;
239 struct efx_phy_operations falcon_xfp_phy_ops
= {
241 .init
= xfp_phy_init
,
242 .reconfigure
= xfp_phy_reconfigure
,
243 .poll
= xfp_phy_poll
,
244 .fini
= xfp_phy_fini
,
245 .clear_interrupt
= xfp_phy_clear_interrupt
,
246 .get_settings
= mdio_clause45_get_settings
,
247 .set_settings
= mdio_clause45_set_settings
,
248 .mmds
= XFP_REQUIRED_DEVS
,
249 .loopbacks
= XFP_LOOPBACKS
,