arch/x86/kernel/cpu/mcheck/p4.c

   1 /*
   2  * P4 specific Machine Check Exception Reporting
   3  */
   4 #include <linux/kernel.h>
   5 #include <linux/types.h>
   6 #include <linux/init.h>
   7 #include <linux/smp.h>
   8
   9 #include <asm/processor.h>
  10 #include <asm/mce.h>
  11 #include <asm/msr.h>
  12
  13 /* as supported by the P4/Xeon family */
  14 struct intel_mce_extended_msrs {
  15         u32 eax;
  16         u32 ebx;
  17         u32 ecx;
  18         u32 edx;
  19         u32 esi;
  20         u32 edi;
  21         u32 ebp;
  22         u32 esp;
  23         u32 eflags;
  24         u32 eip;
  25         /* u32 *reserved[]; */
  26 };
  27
  28 static int mce_num_extended_msrs;
  29
  30 /* P4/Xeon Extended MCE MSR retrieval, return 0 if unsupported */
  31 static void intel_get_extended_msrs(struct intel_mce_extended_msrs *r)
  32 {
  33         u32 h;
  34
  35         rdmsr(MSR_IA32_MCG_EAX, r->eax, h);
  36         rdmsr(MSR_IA32_MCG_EBX, r->ebx, h);
  37         rdmsr(MSR_IA32_MCG_ECX, r->ecx, h);
  38         rdmsr(MSR_IA32_MCG_EDX, r->edx, h);
  39         rdmsr(MSR_IA32_MCG_ESI, r->esi, h);
  40         rdmsr(MSR_IA32_MCG_EDI, r->edi, h);
  41         rdmsr(MSR_IA32_MCG_EBP, r->ebp, h);
  42         rdmsr(MSR_IA32_MCG_ESP, r->esp, h);
  43         rdmsr(MSR_IA32_MCG_EFLAGS, r->eflags, h);
  44         rdmsr(MSR_IA32_MCG_EIP, r->eip, h);
  45 }
  46
  47 static void intel_machine_check(struct pt_regs *regs, long error_code)
  48 {
  49         u32 alow, ahigh, high, low;
  50         u32 mcgstl, mcgsth;
  51         int recover = 1;
  52         int i;
  53
  54         rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  55         if (mcgstl & (1<<0))    /* Recoverable ? */
  56                 recover = 0;
  57
  58         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
  59                 smp_processor_id(), mcgsth, mcgstl);
  60
  61         if (mce_num_extended_msrs > 0) {
  62                 struct intel_mce_extended_msrs dbg;
  63
  64                 intel_get_extended_msrs(&dbg);
  65
  66                 printk(KERN_DEBUG "CPU %d: EIP: %08x EFLAGS: %08x\n"
  67                         "\teax: %08x ebx: %08x ecx: %08x edx: %08x\n"
  68                         "\tesi: %08x edi: %08x ebp: %08x esp: %08x\n",
  69                         smp_processor_id(), dbg.eip, dbg.eflags,
  70                         dbg.eax, dbg.ebx, dbg.ecx, dbg.edx,
  71                         dbg.esi, dbg.edi, dbg.ebp, dbg.esp);
  72         }
  73
  74         for (i = 0; i < nr_mce_banks; i++) {
  75                 rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
  76                 if (high & (1<<31)) {
  77                         char misc[20];
  78                         char addr[24];
  79
  80                         misc[0] = addr[0] = '\0';
  81                         if (high & (1<<29))
  82                                 recover |= 1;
  83                         if (high & (1<<25))
  84                                 recover |= 2;
  85                         high &= ~(1<<31);
  86                         if (high & (1<<27)) {
  87                                 rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
  88                                 snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
  89                         }
  90                         if (high & (1<<26)) {
  91                                 rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
  92                                 snprintf(addr, 24, " at %08x%08x", ahigh, alow);
  93                         }
  94                         printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
  95                                 smp_processor_id(), i, high, low, misc, addr);
  96                 }
  97         }
  98
  99         if (recover & 2)
 100                 panic("CPU context corrupt");
 101         if (recover & 1)
 102                 panic("Unable to continue");
 103
 104         printk(KERN_EMERG "Attempting to continue.\n");
 105
 106         /*
 107          * Do not clear the MSR_IA32_MCi_STATUS if the error is not
 108          * recoverable/continuable.This will allow BIOS to look at the MSRs
 109          * for errors if the OS could not log the error.
 110          */
 111         for (i = 0; i < nr_mce_banks; i++) {
 112                 u32 msr;
 113                 msr = MSR_IA32_MC0_STATUS+i*4;
 114                 rdmsr(msr, low, high);
 115                 if (high&(1<<31)) {
 116                         /* Clear it */
 117                         wrmsr(msr, 0UL, 0UL);
 118                         /* Serialize */
 119                         wmb();
 120                         add_taint(TAINT_MACHINE_CHECK);
 121                 }
 122         }
 123         mcgstl &= ~(1<<2);
 124         wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
 125 }
 126
 127 void intel_p4_mcheck_init(struct cpuinfo_x86 *c)
 128 {
 129         u32 l, h;
 130         int i;
 131
 132         machine_check_vector = intel_machine_check;
 133         wmb();
 134
 135         printk(KERN_INFO "Intel machine check architecture supported.\n");
 136         rdmsr(MSR_IA32_MCG_CAP, l, h);
 137         if (l & (1<<8)) /* Control register present ? */
 138                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 139         nr_mce_banks = l & 0xff;
 140
 141         for (i = 0; i < nr_mce_banks; i++) {
 142                 wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 143                 wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 144         }
 145
 146         set_in_cr4(X86_CR4_MCE);
 147         printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 148                 smp_processor_id());
 149
 150         /* Check for P4/Xeon extended MCE MSRs */
 151         rdmsr(MSR_IA32_MCG_CAP, l, h);
 152         if (l & (1<<9)) {/* MCG_EXT_P */
 153                 mce_num_extended_msrs = (l >> 16) & 0xff;
 154                 printk(KERN_INFO "CPU%d: Intel P4/Xeon Extended MCE MSRs (%d)"
 155                                 " available\n",
 156                         smp_processor_id(), mce_num_extended_msrs);
 157
 158 #ifdef CONFIG_X86_MCE_P4THERMAL
 159                 /* Check for P4/Xeon Thermal monitor */
 160                 intel_init_thermal(c);
 161 #endif
 162         }
 163 }