arch/x86/kernel/cpu/mcheck/k7.c

   1 /*
   2  * Athlon specific Machine Check Exception Reporting
   3  * (C) Copyright 2002 Dave Jones <davej@redhat.com>
   4  */
   5 #include <linux/interrupt.h>
   6 #include <linux/kernel.h>
   7 #include <linux/types.h>
   8 #include <linux/init.h>
   9 #include <linux/smp.h>
  10
  11 #include <asm/processor.h>
  12 #include <asm/system.h>
  13 #include <asm/mce.h>
  14 #include <asm/msr.h>
  15
  16 /* Machine Check Handler For AMD Athlon/Duron: */
  17 static void k7_machine_check(struct pt_regs *regs, long error_code)
  18 {
  19         u32 alow, ahigh, high, low;
  20         u32 mcgstl, mcgsth;
  21         int recover = 1;
  22         int i;
  23
  24         rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  25         if (mcgstl & (1<<0))    /* Recoverable ? */
  26                 recover = 0;
  27
  28         printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
  29                 smp_processor_id(), mcgsth, mcgstl);
  30
  31         for (i = 1; i < nr_mce_banks; i++) {
  32                 rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
  33                 if (high & (1<<31)) {
  34                         char misc[20];
  35                         char addr[24];
  36
  37                         misc[0] = '\0';
  38                         addr[0] = '\0';
  39
  40                         if (high & (1<<29))
  41                                 recover |= 1;
  42                         if (high & (1<<25))
  43                                 recover |= 2;
  44                         high &= ~(1<<31);
  45
  46                         if (high & (1<<27)) {
  47                                 rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
  48                                 snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
  49                         }
  50                         if (high & (1<<26)) {
  51                                 rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
  52                                 snprintf(addr, 24, " at %08x%08x", ahigh, alow);
  53                         }
  54
  55                         printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
  56                                 smp_processor_id(), i, high, low, misc, addr);
  57
  58                         /* Clear it: */
  59                         wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
  60                         /* Serialize: */
  61                         wmb();
  62                         add_taint(TAINT_MACHINE_CHECK);
  63                 }
  64         }
  65
  66         if (recover & 2)
  67                 panic("CPU context corrupt");
  68         if (recover & 1)
  69                 panic("Unable to continue");
  70
  71         printk(KERN_EMERG "Attempting to continue.\n");
  72
  73         mcgstl &= ~(1<<2);
  74         wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  75 }
  76
  77
  78 /* AMD K7 machine check is Intel like: */
  79 void amd_mcheck_init(struct cpuinfo_x86 *c)
  80 {
  81         u32 l, h;
  82         int i;
  83
  84         if (!cpu_has(c, X86_FEATURE_MCE))
  85                 return;
  86
  87         machine_check_vector = k7_machine_check;
  88         /* Make sure the vector pointer is visible before we enable MCEs: */
  89         wmb();
  90
  91         printk(KERN_INFO "Intel machine check architecture supported.\n");
  92
  93         rdmsr(MSR_IA32_MCG_CAP, l, h);
  94         if (l & (1<<8)) /* Control register present ? */
  95                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
  96         nr_mce_banks = l & 0xff;
  97
  98         /*
  99          * Clear status for MC index 0 separately, we don't touch CTL,
 100          * as some K7 Athlons cause spurious MCEs when its enabled:
 101          */
 102         if (boot_cpu_data.x86 == 6) {
 103                 wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
 104                 i = 1;
 105         } else
 106                 i = 0;
 107
 108         for (; i < nr_mce_banks; i++) {
 109                 wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 110                 wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 111         }
 112
 113         set_in_cr4(X86_CR4_MCE);
 114         printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 115                 smp_processor_id());
 116 }