2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
33 #include <linux/pci.h>
35 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
37 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
38 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
39 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
40 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
42 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
45 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
46 static int i915_gem_object_get_page_list(struct drm_gem_object
*obj
);
47 static void i915_gem_object_free_page_list(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
, bool write
);
52 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
53 static int i915_gem_evict_something(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
61 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
64 (start
& (PAGE_SIZE
- 1)) != 0 ||
65 (end
& (PAGE_SIZE
- 1)) != 0) {
69 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
72 dev
->gtt_total
= (uint32_t) (end
- start
);
78 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
79 struct drm_file
*file_priv
)
81 struct drm_i915_gem_init
*args
= data
;
84 mutex_lock(&dev
->struct_mutex
);
85 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
86 mutex_unlock(&dev
->struct_mutex
);
92 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
93 struct drm_file
*file_priv
)
95 struct drm_i915_gem_get_aperture
*args
= data
;
97 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
100 args
->aper_size
= dev
->gtt_total
;
101 args
->aper_available_size
= (args
->aper_size
-
102 atomic_read(&dev
->pin_memory
));
109 * Creates a new mm object and returns a handle to it.
112 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
113 struct drm_file
*file_priv
)
115 struct drm_i915_gem_create
*args
= data
;
116 struct drm_gem_object
*obj
;
119 args
->size
= roundup(args
->size
, PAGE_SIZE
);
121 /* Allocate the new object */
122 obj
= drm_gem_object_alloc(dev
, args
->size
);
126 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
127 mutex_lock(&dev
->struct_mutex
);
128 drm_gem_object_handle_unreference(obj
);
129 mutex_unlock(&dev
->struct_mutex
);
134 args
->handle
= handle
;
140 * Reads data from the object referenced by handle.
142 * On error, the contents of *data are undefined.
145 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
146 struct drm_file
*file_priv
)
148 struct drm_i915_gem_pread
*args
= data
;
149 struct drm_gem_object
*obj
;
150 struct drm_i915_gem_object
*obj_priv
;
155 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
158 obj_priv
= obj
->driver_private
;
160 /* Bounds check source.
162 * XXX: This could use review for overflow issues...
164 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
165 args
->offset
+ args
->size
> obj
->size
) {
166 drm_gem_object_unreference(obj
);
170 mutex_lock(&dev
->struct_mutex
);
172 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
175 drm_gem_object_unreference(obj
);
176 mutex_unlock(&dev
->struct_mutex
);
180 offset
= args
->offset
;
182 read
= vfs_read(obj
->filp
, (char __user
*)(uintptr_t)args
->data_ptr
,
183 args
->size
, &offset
);
184 if (read
!= args
->size
) {
185 drm_gem_object_unreference(obj
);
186 mutex_unlock(&dev
->struct_mutex
);
193 drm_gem_object_unreference(obj
);
194 mutex_unlock(&dev
->struct_mutex
);
199 /* This is the fast write path which cannot handle
200 * page faults in the source data
204 fast_user_write(struct io_mapping
*mapping
,
205 loff_t page_base
, int page_offset
,
206 char __user
*user_data
,
210 unsigned long unwritten
;
212 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
213 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
215 io_mapping_unmap_atomic(vaddr_atomic
);
221 /* Here's the write path which can sleep for
226 slow_user_write(struct io_mapping
*mapping
,
227 loff_t page_base
, int page_offset
,
228 char __user
*user_data
,
232 unsigned long unwritten
;
234 vaddr
= io_mapping_map_wc(mapping
, page_base
);
237 unwritten
= __copy_from_user(vaddr
+ page_offset
,
239 io_mapping_unmap(vaddr
);
246 i915_gem_gtt_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
247 struct drm_i915_gem_pwrite
*args
,
248 struct drm_file
*file_priv
)
250 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
251 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
253 loff_t offset
, page_base
;
254 char __user
*user_data
;
255 int page_offset
, page_length
;
258 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
260 if (!access_ok(VERIFY_READ
, user_data
, remain
))
264 mutex_lock(&dev
->struct_mutex
);
265 ret
= i915_gem_object_pin(obj
, 0);
267 mutex_unlock(&dev
->struct_mutex
);
270 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
274 obj_priv
= obj
->driver_private
;
275 offset
= obj_priv
->gtt_offset
+ args
->offset
;
279 /* Operation in this page
281 * page_base = page offset within aperture
282 * page_offset = offset within page
283 * page_length = bytes to copy for this page
285 page_base
= (offset
& ~(PAGE_SIZE
-1));
286 page_offset
= offset
& (PAGE_SIZE
-1);
287 page_length
= remain
;
288 if ((page_offset
+ remain
) > PAGE_SIZE
)
289 page_length
= PAGE_SIZE
- page_offset
;
291 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
292 page_offset
, user_data
, page_length
);
294 /* If we get a fault while copying data, then (presumably) our
295 * source page isn't available. In this case, use the
296 * non-atomic function
299 ret
= slow_user_write (dev_priv
->mm
.gtt_mapping
,
300 page_base
, page_offset
,
301 user_data
, page_length
);
306 remain
-= page_length
;
307 user_data
+= page_length
;
308 offset
+= page_length
;
312 i915_gem_object_unpin(obj
);
313 mutex_unlock(&dev
->struct_mutex
);
319 i915_gem_shmem_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
320 struct drm_i915_gem_pwrite
*args
,
321 struct drm_file
*file_priv
)
327 mutex_lock(&dev
->struct_mutex
);
329 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
331 mutex_unlock(&dev
->struct_mutex
);
335 offset
= args
->offset
;
337 written
= vfs_write(obj
->filp
,
338 (char __user
*)(uintptr_t) args
->data_ptr
,
339 args
->size
, &offset
);
340 if (written
!= args
->size
) {
341 mutex_unlock(&dev
->struct_mutex
);
348 mutex_unlock(&dev
->struct_mutex
);
354 * Writes data to the object referenced by handle.
356 * On error, the contents of the buffer that were to be modified are undefined.
359 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
360 struct drm_file
*file_priv
)
362 struct drm_i915_gem_pwrite
*args
= data
;
363 struct drm_gem_object
*obj
;
364 struct drm_i915_gem_object
*obj_priv
;
367 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
370 obj_priv
= obj
->driver_private
;
372 /* Bounds check destination.
374 * XXX: This could use review for overflow issues...
376 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
377 args
->offset
+ args
->size
> obj
->size
) {
378 drm_gem_object_unreference(obj
);
382 /* We can only do the GTT pwrite on untiled buffers, as otherwise
383 * it would end up going through the fenced access, and we'll get
384 * different detiling behavior between reading and writing.
385 * pread/pwrite currently are reading and writing from the CPU
386 * perspective, requiring manual detiling by the client.
388 if (obj_priv
->phys_obj
)
389 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
390 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
392 ret
= i915_gem_gtt_pwrite(dev
, obj
, args
, file_priv
);
394 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file_priv
);
398 DRM_INFO("pwrite failed %d\n", ret
);
401 drm_gem_object_unreference(obj
);
407 * Called when user space prepares to use an object with the CPU, either
408 * through the mmap ioctl's mapping or a GTT mapping.
411 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
412 struct drm_file
*file_priv
)
414 struct drm_i915_gem_set_domain
*args
= data
;
415 struct drm_gem_object
*obj
;
416 uint32_t read_domains
= args
->read_domains
;
417 uint32_t write_domain
= args
->write_domain
;
420 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
423 /* Only handle setting domains to types used by the CPU. */
424 if (write_domain
& ~(I915_GEM_DOMAIN_CPU
| I915_GEM_DOMAIN_GTT
))
427 if (read_domains
& ~(I915_GEM_DOMAIN_CPU
| I915_GEM_DOMAIN_GTT
))
430 /* Having something in the write domain implies it's in the read
431 * domain, and only that read domain. Enforce that in the request.
433 if (write_domain
!= 0 && read_domains
!= write_domain
)
436 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
440 mutex_lock(&dev
->struct_mutex
);
442 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
443 obj
, obj
->size
, read_domains
, write_domain
);
445 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
446 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
448 /* Silently promote "you're not bound, there was nothing to do"
449 * to success, since the client was just asking us to
450 * make sure everything was done.
455 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
458 drm_gem_object_unreference(obj
);
459 mutex_unlock(&dev
->struct_mutex
);
464 * Called when user space has done writes to this buffer
467 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
468 struct drm_file
*file_priv
)
470 struct drm_i915_gem_sw_finish
*args
= data
;
471 struct drm_gem_object
*obj
;
472 struct drm_i915_gem_object
*obj_priv
;
475 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
478 mutex_lock(&dev
->struct_mutex
);
479 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
481 mutex_unlock(&dev
->struct_mutex
);
486 DRM_INFO("%s: sw_finish %d (%p %d)\n",
487 __func__
, args
->handle
, obj
, obj
->size
);
489 obj_priv
= obj
->driver_private
;
491 /* Pinned buffers may be scanout, so flush the cache */
492 if (obj_priv
->pin_count
)
493 i915_gem_object_flush_cpu_write_domain(obj
);
495 drm_gem_object_unreference(obj
);
496 mutex_unlock(&dev
->struct_mutex
);
501 * Maps the contents of an object, returning the address it is mapped
504 * While the mapping holds a reference on the contents of the object, it doesn't
505 * imply a ref on the object itself.
508 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
509 struct drm_file
*file_priv
)
511 struct drm_i915_gem_mmap
*args
= data
;
512 struct drm_gem_object
*obj
;
516 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
519 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
523 offset
= args
->offset
;
525 down_write(¤t
->mm
->mmap_sem
);
526 addr
= do_mmap(obj
->filp
, 0, args
->size
,
527 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
529 up_write(¤t
->mm
->mmap_sem
);
530 mutex_lock(&dev
->struct_mutex
);
531 drm_gem_object_unreference(obj
);
532 mutex_unlock(&dev
->struct_mutex
);
533 if (IS_ERR((void *)addr
))
536 args
->addr_ptr
= (uint64_t) addr
;
542 * i915_gem_fault - fault a page into the GTT
543 * vma: VMA in question
546 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
547 * from userspace. The fault handler takes care of binding the object to
548 * the GTT (if needed), allocating and programming a fence register (again,
549 * only if needed based on whether the old reg is still valid or the object
550 * is tiled) and inserting a new PTE into the faulting process.
552 * Note that the faulting process may involve evicting existing objects
553 * from the GTT and/or fence registers to make room. So performance may
554 * suffer if the GTT working set is large or there are few fence registers
557 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
559 struct drm_gem_object
*obj
= vma
->vm_private_data
;
560 struct drm_device
*dev
= obj
->dev
;
561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
562 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
566 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
568 /* We don't use vmf->pgoff since that has the fake offset */
569 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
572 /* Now bind it into the GTT if needed */
573 mutex_lock(&dev
->struct_mutex
);
574 if (!obj_priv
->gtt_space
) {
575 ret
= i915_gem_object_bind_to_gtt(obj
, obj_priv
->gtt_alignment
);
577 mutex_unlock(&dev
->struct_mutex
);
578 return VM_FAULT_SIGBUS
;
580 list_add(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
583 /* Need a new fence register? */
584 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
585 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
586 ret
= i915_gem_object_get_fence_reg(obj
, write
);
588 mutex_unlock(&dev
->struct_mutex
);
589 return VM_FAULT_SIGBUS
;
593 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
596 /* Finally, remap it using the new GTT offset */
597 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
599 mutex_unlock(&dev
->struct_mutex
);
606 return VM_FAULT_SIGBUS
;
608 return VM_FAULT_NOPAGE
;
613 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
614 * @obj: obj in question
616 * GEM memory mapping works by handing back to userspace a fake mmap offset
617 * it can use in a subsequent mmap(2) call. The DRM core code then looks
618 * up the object based on the offset and sets up the various memory mapping
621 * This routine allocates and attaches a fake offset for @obj.
624 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
626 struct drm_device
*dev
= obj
->dev
;
627 struct drm_gem_mm
*mm
= dev
->mm_private
;
628 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
629 struct drm_map_list
*list
;
633 /* Set the object up for mmap'ing */
634 list
= &obj
->map_list
;
635 list
->map
= drm_calloc(1, sizeof(struct drm_map_list
),
641 map
->type
= _DRM_GEM
;
642 map
->size
= obj
->size
;
645 /* Get a DRM GEM mmap offset allocated... */
646 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
647 obj
->size
/ PAGE_SIZE
, 0, 0);
648 if (!list
->file_offset_node
) {
649 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
654 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
655 obj
->size
/ PAGE_SIZE
, 0);
656 if (!list
->file_offset_node
) {
661 list
->hash
.key
= list
->file_offset_node
->start
;
662 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
663 DRM_ERROR("failed to add to map hash\n");
667 /* By now we should be all set, any drm_mmap request on the offset
668 * below will get to our mmap & fault handler */
669 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
674 drm_mm_put_block(list
->file_offset_node
);
676 drm_free(list
->map
, sizeof(struct drm_map_list
), DRM_MEM_DRIVER
);
682 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
684 struct drm_device
*dev
= obj
->dev
;
685 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
686 struct drm_gem_mm
*mm
= dev
->mm_private
;
687 struct drm_map_list
*list
;
689 list
= &obj
->map_list
;
690 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
692 if (list
->file_offset_node
) {
693 drm_mm_put_block(list
->file_offset_node
);
694 list
->file_offset_node
= NULL
;
698 drm_free(list
->map
, sizeof(struct drm_map
), DRM_MEM_DRIVER
);
702 obj_priv
->mmap_offset
= 0;
706 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
707 * @obj: object to check
709 * Return the required GTT alignment for an object, taking into account
710 * potential fence register mapping if needed.
713 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
715 struct drm_device
*dev
= obj
->dev
;
716 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
720 * Minimum alignment is 4k (GTT page size), but might be greater
721 * if a fence register is needed for the object.
723 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
727 * Previous chips need to be aligned to the size of the smallest
728 * fence register that can contain the object.
735 for (i
= start
; i
< obj
->size
; i
<<= 1)
742 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
744 * @data: GTT mapping ioctl data
745 * @file_priv: GEM object info
747 * Simply returns the fake offset to userspace so it can mmap it.
748 * The mmap call will end up in drm_gem_mmap(), which will set things
749 * up so we can get faults in the handler above.
751 * The fault handler will take care of binding the object into the GTT
752 * (since it may have been evicted to make room for something), allocating
753 * a fence register, and mapping the appropriate aperture address into
757 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
758 struct drm_file
*file_priv
)
760 struct drm_i915_gem_mmap_gtt
*args
= data
;
761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
762 struct drm_gem_object
*obj
;
763 struct drm_i915_gem_object
*obj_priv
;
766 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
769 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
773 mutex_lock(&dev
->struct_mutex
);
775 obj_priv
= obj
->driver_private
;
777 if (!obj_priv
->mmap_offset
) {
778 ret
= i915_gem_create_mmap_offset(obj
);
780 drm_gem_object_unreference(obj
);
781 mutex_unlock(&dev
->struct_mutex
);
786 args
->offset
= obj_priv
->mmap_offset
;
788 obj_priv
->gtt_alignment
= i915_gem_get_gtt_alignment(obj
);
790 /* Make sure the alignment is correct for fence regs etc */
791 if (obj_priv
->agp_mem
&&
792 (obj_priv
->gtt_offset
& (obj_priv
->gtt_alignment
- 1))) {
793 drm_gem_object_unreference(obj
);
794 mutex_unlock(&dev
->struct_mutex
);
799 * Pull it into the GTT so that we have a page list (makes the
800 * initial fault faster and any subsequent flushing possible).
802 if (!obj_priv
->agp_mem
) {
803 ret
= i915_gem_object_bind_to_gtt(obj
, obj_priv
->gtt_alignment
);
805 drm_gem_object_unreference(obj
);
806 mutex_unlock(&dev
->struct_mutex
);
809 list_add(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
812 drm_gem_object_unreference(obj
);
813 mutex_unlock(&dev
->struct_mutex
);
819 i915_gem_object_free_page_list(struct drm_gem_object
*obj
)
821 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
822 int page_count
= obj
->size
/ PAGE_SIZE
;
825 if (obj_priv
->page_list
== NULL
)
829 for (i
= 0; i
< page_count
; i
++)
830 if (obj_priv
->page_list
[i
] != NULL
) {
832 set_page_dirty(obj_priv
->page_list
[i
]);
833 mark_page_accessed(obj_priv
->page_list
[i
]);
834 page_cache_release(obj_priv
->page_list
[i
]);
838 drm_free(obj_priv
->page_list
,
839 page_count
* sizeof(struct page
*),
841 obj_priv
->page_list
= NULL
;
845 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
847 struct drm_device
*dev
= obj
->dev
;
848 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
849 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
851 /* Add a reference if we're newly entering the active list. */
852 if (!obj_priv
->active
) {
853 drm_gem_object_reference(obj
);
854 obj_priv
->active
= 1;
856 /* Move from whatever list we were on to the tail of execution. */
857 list_move_tail(&obj_priv
->list
,
858 &dev_priv
->mm
.active_list
);
859 obj_priv
->last_rendering_seqno
= seqno
;
863 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
865 struct drm_device
*dev
= obj
->dev
;
866 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
867 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
869 BUG_ON(!obj_priv
->active
);
870 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
871 obj_priv
->last_rendering_seqno
= 0;
875 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
877 struct drm_device
*dev
= obj
->dev
;
878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
879 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
881 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
882 if (obj_priv
->pin_count
!= 0)
883 list_del_init(&obj_priv
->list
);
885 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
887 obj_priv
->last_rendering_seqno
= 0;
888 if (obj_priv
->active
) {
889 obj_priv
->active
= 0;
890 drm_gem_object_unreference(obj
);
892 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
896 * Creates a new sequence number, emitting a write of it to the status page
897 * plus an interrupt, which will trigger i915_user_interrupt_handler.
899 * Must be called with struct_lock held.
901 * Returned sequence numbers are nonzero on success.
904 i915_add_request(struct drm_device
*dev
, uint32_t flush_domains
)
906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
907 struct drm_i915_gem_request
*request
;
912 request
= drm_calloc(1, sizeof(*request
), DRM_MEM_DRIVER
);
916 /* Grab the seqno we're going to make this request be, and bump the
917 * next (skipping 0 so it can be the reserved no-seqno value).
919 seqno
= dev_priv
->mm
.next_gem_seqno
;
920 dev_priv
->mm
.next_gem_seqno
++;
921 if (dev_priv
->mm
.next_gem_seqno
== 0)
922 dev_priv
->mm
.next_gem_seqno
++;
925 OUT_RING(MI_STORE_DWORD_INDEX
);
926 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
929 OUT_RING(MI_USER_INTERRUPT
);
932 DRM_DEBUG("%d\n", seqno
);
934 request
->seqno
= seqno
;
935 request
->emitted_jiffies
= jiffies
;
936 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
937 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
939 /* Associate any objects on the flushing list matching the write
940 * domain we're flushing with our flush.
942 if (flush_domains
!= 0) {
943 struct drm_i915_gem_object
*obj_priv
, *next
;
945 list_for_each_entry_safe(obj_priv
, next
,
946 &dev_priv
->mm
.flushing_list
, list
) {
947 struct drm_gem_object
*obj
= obj_priv
->obj
;
949 if ((obj
->write_domain
& flush_domains
) ==
951 obj
->write_domain
= 0;
952 i915_gem_object_move_to_active(obj
, seqno
);
958 if (was_empty
&& !dev_priv
->mm
.suspended
)
959 schedule_delayed_work(&dev_priv
->mm
.retire_work
, HZ
);
964 * Command execution barrier
966 * Ensures that all commands in the ring are finished
967 * before signalling the CPU
970 i915_retire_commands(struct drm_device
*dev
)
972 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
973 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
974 uint32_t flush_domains
= 0;
977 /* The sampler always gets flushed on i965 (sigh) */
979 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
982 OUT_RING(0); /* noop */
984 return flush_domains
;
988 * Moves buffers associated only with the given active seqno from the active
989 * to inactive list, potentially freeing them.
992 i915_gem_retire_request(struct drm_device
*dev
,
993 struct drm_i915_gem_request
*request
)
995 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
997 /* Move any buffers on the active list that are no longer referenced
998 * by the ringbuffer to the flushing/inactive lists as appropriate.
1000 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1001 struct drm_gem_object
*obj
;
1002 struct drm_i915_gem_object
*obj_priv
;
1004 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1005 struct drm_i915_gem_object
,
1007 obj
= obj_priv
->obj
;
1009 /* If the seqno being retired doesn't match the oldest in the
1010 * list, then the oldest in the list must still be newer than
1013 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1017 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1018 __func__
, request
->seqno
, obj
);
1021 if (obj
->write_domain
!= 0)
1022 i915_gem_object_move_to_flushing(obj
);
1024 i915_gem_object_move_to_inactive(obj
);
1029 * Returns true if seq1 is later than seq2.
1032 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1034 return (int32_t)(seq1
- seq2
) >= 0;
1038 i915_get_gem_seqno(struct drm_device
*dev
)
1040 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1042 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1046 * This function clears the request list as sequence numbers are passed.
1049 i915_gem_retire_requests(struct drm_device
*dev
)
1051 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1054 seqno
= i915_get_gem_seqno(dev
);
1056 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1057 struct drm_i915_gem_request
*request
;
1058 uint32_t retiring_seqno
;
1060 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1061 struct drm_i915_gem_request
,
1063 retiring_seqno
= request
->seqno
;
1065 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1066 dev_priv
->mm
.wedged
) {
1067 i915_gem_retire_request(dev
, request
);
1069 list_del(&request
->list
);
1070 drm_free(request
, sizeof(*request
), DRM_MEM_DRIVER
);
1077 i915_gem_retire_work_handler(struct work_struct
*work
)
1079 drm_i915_private_t
*dev_priv
;
1080 struct drm_device
*dev
;
1082 dev_priv
= container_of(work
, drm_i915_private_t
,
1083 mm
.retire_work
.work
);
1084 dev
= dev_priv
->dev
;
1086 mutex_lock(&dev
->struct_mutex
);
1087 i915_gem_retire_requests(dev
);
1088 if (!dev_priv
->mm
.suspended
&&
1089 !list_empty(&dev_priv
->mm
.request_list
))
1090 schedule_delayed_work(&dev_priv
->mm
.retire_work
, HZ
);
1091 mutex_unlock(&dev
->struct_mutex
);
1095 * Waits for a sequence number to be signaled, and cleans up the
1096 * request and object lists appropriately for that event.
1099 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1101 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1106 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1107 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1108 i915_user_irq_get(dev
);
1109 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1110 i915_seqno_passed(i915_get_gem_seqno(dev
),
1112 dev_priv
->mm
.wedged
);
1113 i915_user_irq_put(dev
);
1114 dev_priv
->mm
.waiting_gem_seqno
= 0;
1116 if (dev_priv
->mm
.wedged
)
1119 if (ret
&& ret
!= -ERESTARTSYS
)
1120 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1121 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1123 /* Directly dispatch request retiring. While we have the work queue
1124 * to handle this, the waiter on a request often wants an associated
1125 * buffer to have made it to the inactive list, and we would need
1126 * a separate wait queue to handle that.
1129 i915_gem_retire_requests(dev
);
1135 i915_gem_flush(struct drm_device
*dev
,
1136 uint32_t invalidate_domains
,
1137 uint32_t flush_domains
)
1139 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1144 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1145 invalidate_domains
, flush_domains
);
1148 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1149 drm_agp_chipset_flush(dev
);
1151 if ((invalidate_domains
| flush_domains
) & ~(I915_GEM_DOMAIN_CPU
|
1152 I915_GEM_DOMAIN_GTT
)) {
1154 * read/write caches:
1156 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1157 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1158 * also flushed at 2d versus 3d pipeline switches.
1162 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1163 * MI_READ_FLUSH is set, and is always flushed on 965.
1165 * I915_GEM_DOMAIN_COMMAND may not exist?
1167 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1168 * invalidated when MI_EXE_FLUSH is set.
1170 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1171 * invalidated with every MI_FLUSH.
1175 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1176 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1177 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1178 * are flushed at any MI_FLUSH.
1181 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1182 if ((invalidate_domains
|flush_domains
) &
1183 I915_GEM_DOMAIN_RENDER
)
1184 cmd
&= ~MI_NO_WRITE_FLUSH
;
1185 if (!IS_I965G(dev
)) {
1187 * On the 965, the sampler cache always gets flushed
1188 * and this bit is reserved.
1190 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1191 cmd
|= MI_READ_FLUSH
;
1193 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1194 cmd
|= MI_EXE_FLUSH
;
1197 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1201 OUT_RING(0); /* noop */
1207 * Ensures that all rendering to the object has completed and the object is
1208 * safe to unbind from the GTT or access from the CPU.
1211 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1213 struct drm_device
*dev
= obj
->dev
;
1214 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1217 /* This function only exists to support waiting for existing rendering,
1218 * not for emitting required flushes.
1220 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1222 /* If there is rendering queued on the buffer being evicted, wait for
1225 if (obj_priv
->active
) {
1227 DRM_INFO("%s: object %p wait for seqno %08x\n",
1228 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1230 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1239 * Unbinds an object from the GTT aperture.
1242 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1244 struct drm_device
*dev
= obj
->dev
;
1245 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1250 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1251 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1253 if (obj_priv
->gtt_space
== NULL
)
1256 if (obj_priv
->pin_count
!= 0) {
1257 DRM_ERROR("Attempting to unbind pinned buffer\n");
1261 /* Move the object to the CPU domain to ensure that
1262 * any possible CPU writes while it's not in the GTT
1263 * are flushed when we go to remap it. This will
1264 * also ensure that all pending GPU writes are finished
1267 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1269 if (ret
!= -ERESTARTSYS
)
1270 DRM_ERROR("set_domain failed: %d\n", ret
);
1274 if (obj_priv
->agp_mem
!= NULL
) {
1275 drm_unbind_agp(obj_priv
->agp_mem
);
1276 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1277 obj_priv
->agp_mem
= NULL
;
1280 BUG_ON(obj_priv
->active
);
1282 /* blow away mappings if mapped through GTT */
1283 offset
= ((loff_t
) obj
->map_list
.hash
.key
) << PAGE_SHIFT
;
1284 if (dev
->dev_mapping
)
1285 unmap_mapping_range(dev
->dev_mapping
, offset
, obj
->size
, 1);
1287 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1288 i915_gem_clear_fence_reg(obj
);
1290 i915_gem_object_free_page_list(obj
);
1292 if (obj_priv
->gtt_space
) {
1293 atomic_dec(&dev
->gtt_count
);
1294 atomic_sub(obj
->size
, &dev
->gtt_memory
);
1296 drm_mm_put_block(obj_priv
->gtt_space
);
1297 obj_priv
->gtt_space
= NULL
;
1300 /* Remove ourselves from the LRU list if present. */
1301 if (!list_empty(&obj_priv
->list
))
1302 list_del_init(&obj_priv
->list
);
1308 i915_gem_evict_something(struct drm_device
*dev
)
1310 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1311 struct drm_gem_object
*obj
;
1312 struct drm_i915_gem_object
*obj_priv
;
1316 /* If there's an inactive buffer available now, grab it
1319 if (!list_empty(&dev_priv
->mm
.inactive_list
)) {
1320 obj_priv
= list_first_entry(&dev_priv
->mm
.inactive_list
,
1321 struct drm_i915_gem_object
,
1323 obj
= obj_priv
->obj
;
1324 BUG_ON(obj_priv
->pin_count
!= 0);
1326 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
1328 BUG_ON(obj_priv
->active
);
1330 /* Wait on the rendering and unbind the buffer. */
1331 ret
= i915_gem_object_unbind(obj
);
1335 /* If we didn't get anything, but the ring is still processing
1336 * things, wait for one of those things to finish and hopefully
1337 * leave us a buffer to evict.
1339 if (!list_empty(&dev_priv
->mm
.request_list
)) {
1340 struct drm_i915_gem_request
*request
;
1342 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1343 struct drm_i915_gem_request
,
1346 ret
= i915_wait_request(dev
, request
->seqno
);
1350 /* if waiting caused an object to become inactive,
1351 * then loop around and wait for it. Otherwise, we
1352 * assume that waiting freed and unbound something,
1353 * so there should now be some space in the GTT
1355 if (!list_empty(&dev_priv
->mm
.inactive_list
))
1360 /* If we didn't have anything on the request list but there
1361 * are buffers awaiting a flush, emit one and try again.
1362 * When we wait on it, those buffers waiting for that flush
1363 * will get moved to inactive.
1365 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1366 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1367 struct drm_i915_gem_object
,
1369 obj
= obj_priv
->obj
;
1374 i915_add_request(dev
, obj
->write_domain
);
1380 DRM_ERROR("inactive empty %d request empty %d "
1381 "flushing empty %d\n",
1382 list_empty(&dev_priv
->mm
.inactive_list
),
1383 list_empty(&dev_priv
->mm
.request_list
),
1384 list_empty(&dev_priv
->mm
.flushing_list
));
1385 /* If we didn't do any of the above, there's nothing to be done
1386 * and we just can't fit it in.
1394 i915_gem_evict_everything(struct drm_device
*dev
)
1399 ret
= i915_gem_evict_something(dev
);
1409 i915_gem_object_get_page_list(struct drm_gem_object
*obj
)
1411 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1413 struct address_space
*mapping
;
1414 struct inode
*inode
;
1418 if (obj_priv
->page_list
)
1421 /* Get the list of pages out of our struct file. They'll be pinned
1422 * at this point until we release them.
1424 page_count
= obj
->size
/ PAGE_SIZE
;
1425 BUG_ON(obj_priv
->page_list
!= NULL
);
1426 obj_priv
->page_list
= drm_calloc(page_count
, sizeof(struct page
*),
1428 if (obj_priv
->page_list
== NULL
) {
1429 DRM_ERROR("Faled to allocate page list\n");
1433 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1434 mapping
= inode
->i_mapping
;
1435 for (i
= 0; i
< page_count
; i
++) {
1436 page
= read_mapping_page(mapping
, i
, NULL
);
1438 ret
= PTR_ERR(page
);
1439 DRM_ERROR("read_mapping_page failed: %d\n", ret
);
1440 i915_gem_object_free_page_list(obj
);
1443 obj_priv
->page_list
[i
] = page
;
1448 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
1450 struct drm_gem_object
*obj
= reg
->obj
;
1451 struct drm_device
*dev
= obj
->dev
;
1452 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1453 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1454 int regnum
= obj_priv
->fence_reg
;
1457 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
1459 val
|= obj_priv
->gtt_offset
& 0xfffff000;
1460 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
1461 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
1462 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
1463 val
|= I965_FENCE_REG_VALID
;
1465 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
1468 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
1470 struct drm_gem_object
*obj
= reg
->obj
;
1471 struct drm_device
*dev
= obj
->dev
;
1472 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1473 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1474 int regnum
= obj_priv
->fence_reg
;
1479 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
1480 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
1481 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
1482 __func__
, obj_priv
->gtt_offset
, obj
->size
);
1486 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
1487 HAS_128_BYTE_Y_TILING(dev
))
1492 /* Note: pitch better be a power of two tile widths */
1493 pitch_val
= obj_priv
->stride
/ tile_width
;
1494 pitch_val
= ffs(pitch_val
) - 1;
1496 val
= obj_priv
->gtt_offset
;
1497 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
1498 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
1499 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
1500 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
1501 val
|= I830_FENCE_REG_VALID
;
1503 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
1506 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
1508 struct drm_gem_object
*obj
= reg
->obj
;
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1512 int regnum
= obj_priv
->fence_reg
;
1516 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
1517 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
1518 WARN(1, "%s: object 0x%08x not 1M or size aligned\n",
1519 __func__
, obj_priv
->gtt_offset
);
1523 pitch_val
= (obj_priv
->stride
/ 128) - 1;
1525 val
= obj_priv
->gtt_offset
;
1526 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
1527 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
1528 val
|= I830_FENCE_SIZE_BITS(obj
->size
);
1529 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
1530 val
|= I830_FENCE_REG_VALID
;
1532 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
1537 * i915_gem_object_get_fence_reg - set up a fence reg for an object
1538 * @obj: object to map through a fence reg
1539 * @write: object is about to be written
1541 * When mapping objects through the GTT, userspace wants to be able to write
1542 * to them without having to worry about swizzling if the object is tiled.
1544 * This function walks the fence regs looking for a free one for @obj,
1545 * stealing one if it can't find any.
1547 * It then sets up the reg based on the object's properties: address, pitch
1548 * and tiling format.
1551 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
, bool write
)
1553 struct drm_device
*dev
= obj
->dev
;
1554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1555 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1556 struct drm_i915_fence_reg
*reg
= NULL
;
1559 switch (obj_priv
->tiling_mode
) {
1560 case I915_TILING_NONE
:
1561 WARN(1, "allocating a fence for non-tiled object?\n");
1564 if (!obj_priv
->stride
)
1566 WARN((obj_priv
->stride
& (512 - 1)),
1567 "object 0x%08x is X tiled but has non-512B pitch\n",
1568 obj_priv
->gtt_offset
);
1571 if (!obj_priv
->stride
)
1573 WARN((obj_priv
->stride
& (128 - 1)),
1574 "object 0x%08x is Y tiled but has non-128B pitch\n",
1575 obj_priv
->gtt_offset
);
1579 /* First try to find a free reg */
1580 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
1581 reg
= &dev_priv
->fence_regs
[i
];
1586 /* None available, try to steal one or wait for a user to finish */
1587 if (i
== dev_priv
->num_fence_regs
) {
1588 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
1592 /* Could try to use LRU here instead... */
1593 for (i
= dev_priv
->fence_reg_start
;
1594 i
< dev_priv
->num_fence_regs
; i
++) {
1595 reg
= &dev_priv
->fence_regs
[i
];
1596 old_obj_priv
= reg
->obj
->driver_private
;
1597 if (!old_obj_priv
->pin_count
)
1602 * Now things get ugly... we have to wait for one of the
1603 * objects to finish before trying again.
1605 if (i
== dev_priv
->num_fence_regs
) {
1606 ret
= i915_gem_object_set_to_gtt_domain(reg
->obj
, 0);
1608 WARN(ret
!= -ERESTARTSYS
,
1609 "switch to GTT domain failed: %d\n", ret
);
1616 * Zap this virtual mapping so we can set up a fence again
1617 * for this object next time we need it.
1619 offset
= ((loff_t
) reg
->obj
->map_list
.hash
.key
) << PAGE_SHIFT
;
1620 if (dev
->dev_mapping
)
1621 unmap_mapping_range(dev
->dev_mapping
, offset
,
1623 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
1626 obj_priv
->fence_reg
= i
;
1630 i965_write_fence_reg(reg
);
1631 else if (IS_I9XX(dev
))
1632 i915_write_fence_reg(reg
);
1634 i830_write_fence_reg(reg
);
1640 * i915_gem_clear_fence_reg - clear out fence register info
1641 * @obj: object to clear
1643 * Zeroes out the fence register itself and clears out the associated
1644 * data structures in dev_priv and obj_priv.
1647 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
1649 struct drm_device
*dev
= obj
->dev
;
1650 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1651 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1654 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
1656 I915_WRITE(FENCE_REG_830_0
+ (obj_priv
->fence_reg
* 4), 0);
1658 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
1659 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
1663 * Finds free space in the GTT aperture and binds the object there.
1666 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
1668 struct drm_device
*dev
= obj
->dev
;
1669 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1670 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1671 struct drm_mm_node
*free_space
;
1672 int page_count
, ret
;
1674 if (dev_priv
->mm
.suspended
)
1677 alignment
= i915_gem_get_gtt_alignment(obj
);
1678 if (alignment
& (PAGE_SIZE
- 1)) {
1679 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
1684 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
1685 obj
->size
, alignment
, 0);
1686 if (free_space
!= NULL
) {
1687 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
1689 if (obj_priv
->gtt_space
!= NULL
) {
1690 obj_priv
->gtt_space
->private = obj
;
1691 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
1694 if (obj_priv
->gtt_space
== NULL
) {
1695 /* If the gtt is empty and we're still having trouble
1696 * fitting our object in, we're out of memory.
1699 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
1701 if (list_empty(&dev_priv
->mm
.inactive_list
) &&
1702 list_empty(&dev_priv
->mm
.flushing_list
) &&
1703 list_empty(&dev_priv
->mm
.active_list
)) {
1704 DRM_ERROR("GTT full, but LRU list empty\n");
1708 ret
= i915_gem_evict_something(dev
);
1710 if (ret
!= -ERESTARTSYS
)
1711 DRM_ERROR("Failed to evict a buffer %d\n", ret
);
1718 DRM_INFO("Binding object of size %d at 0x%08x\n",
1719 obj
->size
, obj_priv
->gtt_offset
);
1721 ret
= i915_gem_object_get_page_list(obj
);
1723 drm_mm_put_block(obj_priv
->gtt_space
);
1724 obj_priv
->gtt_space
= NULL
;
1728 page_count
= obj
->size
/ PAGE_SIZE
;
1729 /* Create an AGP memory structure pointing at our pages, and bind it
1732 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
1733 obj_priv
->page_list
,
1735 obj_priv
->gtt_offset
,
1736 obj_priv
->agp_type
);
1737 if (obj_priv
->agp_mem
== NULL
) {
1738 i915_gem_object_free_page_list(obj
);
1739 drm_mm_put_block(obj_priv
->gtt_space
);
1740 obj_priv
->gtt_space
= NULL
;
1743 atomic_inc(&dev
->gtt_count
);
1744 atomic_add(obj
->size
, &dev
->gtt_memory
);
1746 /* Assert that the object is not currently in any GPU domain. As it
1747 * wasn't in the GTT, there shouldn't be any way it could have been in
1750 BUG_ON(obj
->read_domains
& ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
1751 BUG_ON(obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
1757 i915_gem_clflush_object(struct drm_gem_object
*obj
)
1759 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1761 /* If we don't have a page list set up, then we're not pinned
1762 * to GPU, and we can ignore the cache flush because it'll happen
1763 * again at bind time.
1765 if (obj_priv
->page_list
== NULL
)
1768 drm_clflush_pages(obj_priv
->page_list
, obj
->size
/ PAGE_SIZE
);
1771 /** Flushes any GPU write domain for the object if it's dirty. */
1773 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
1775 struct drm_device
*dev
= obj
->dev
;
1778 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
1781 /* Queue the GPU write cache flushing we need. */
1782 i915_gem_flush(dev
, 0, obj
->write_domain
);
1783 seqno
= i915_add_request(dev
, obj
->write_domain
);
1784 obj
->write_domain
= 0;
1785 i915_gem_object_move_to_active(obj
, seqno
);
1788 /** Flushes the GTT write domain for the object if it's dirty. */
1790 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
1792 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
1795 /* No actual flushing is required for the GTT write domain. Writes
1796 * to it immediately go to main memory as far as we know, so there's
1797 * no chipset flush. It also doesn't land in render cache.
1799 obj
->write_domain
= 0;
1802 /** Flushes the CPU write domain for the object if it's dirty. */
1804 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
1806 struct drm_device
*dev
= obj
->dev
;
1808 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
1811 i915_gem_clflush_object(obj
);
1812 drm_agp_chipset_flush(dev
);
1813 obj
->write_domain
= 0;
1817 * Moves a single object to the GTT read, and possibly write domain.
1819 * This function returns when the move is complete, including waiting on
1823 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
1825 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1828 /* Not valid to be called on unbound objects. */
1829 if (obj_priv
->gtt_space
== NULL
)
1832 i915_gem_object_flush_gpu_write_domain(obj
);
1833 /* Wait on any GPU rendering and flushing to occur. */
1834 ret
= i915_gem_object_wait_rendering(obj
);
1838 /* If we're writing through the GTT domain, then CPU and GPU caches
1839 * will need to be invalidated at next use.
1842 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
1844 i915_gem_object_flush_cpu_write_domain(obj
);
1846 /* It should now be out of any other write domains, and we can update
1847 * the domain values for our changes.
1849 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
1850 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
1852 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
1853 obj_priv
->dirty
= 1;
1860 * Moves a single object to the CPU read, and possibly write domain.
1862 * This function returns when the move is complete, including waiting on
1866 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
1868 struct drm_device
*dev
= obj
->dev
;
1871 i915_gem_object_flush_gpu_write_domain(obj
);
1872 /* Wait on any GPU rendering and flushing to occur. */
1873 ret
= i915_gem_object_wait_rendering(obj
);
1877 i915_gem_object_flush_gtt_write_domain(obj
);
1879 /* If we have a partially-valid cache of the object in the CPU,
1880 * finish invalidating it and free the per-page flags.
1882 i915_gem_object_set_to_full_cpu_read_domain(obj
);
1884 /* Flush the CPU cache if it's still invalid. */
1885 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
1886 i915_gem_clflush_object(obj
);
1887 drm_agp_chipset_flush(dev
);
1889 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
1892 /* It should now be out of any other write domains, and we can update
1893 * the domain values for our changes.
1895 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
1897 /* If we're writing through the CPU, then the GPU read domains will
1898 * need to be invalidated at next use.
1901 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
1902 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
1909 * Set the next domain for the specified object. This
1910 * may not actually perform the necessary flushing/invaliding though,
1911 * as that may want to be batched with other set_domain operations
1913 * This is (we hope) the only really tricky part of gem. The goal
1914 * is fairly simple -- track which caches hold bits of the object
1915 * and make sure they remain coherent. A few concrete examples may
1916 * help to explain how it works. For shorthand, we use the notation
1917 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1918 * a pair of read and write domain masks.
1920 * Case 1: the batch buffer
1926 * 5. Unmapped from GTT
1929 * Let's take these a step at a time
1932 * Pages allocated from the kernel may still have
1933 * cache contents, so we set them to (CPU, CPU) always.
1934 * 2. Written by CPU (using pwrite)
1935 * The pwrite function calls set_domain (CPU, CPU) and
1936 * this function does nothing (as nothing changes)
1938 * This function asserts that the object is not
1939 * currently in any GPU-based read or write domains
1941 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1942 * As write_domain is zero, this function adds in the
1943 * current read domains (CPU+COMMAND, 0).
1944 * flush_domains is set to CPU.
1945 * invalidate_domains is set to COMMAND
1946 * clflush is run to get data out of the CPU caches
1947 * then i915_dev_set_domain calls i915_gem_flush to
1948 * emit an MI_FLUSH and drm_agp_chipset_flush
1949 * 5. Unmapped from GTT
1950 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1951 * flush_domains and invalidate_domains end up both zero
1952 * so no flushing/invalidating happens
1956 * Case 2: The shared render buffer
1960 * 3. Read/written by GPU
1961 * 4. set_domain to (CPU,CPU)
1962 * 5. Read/written by CPU
1963 * 6. Read/written by GPU
1966 * Same as last example, (CPU, CPU)
1968 * Nothing changes (assertions find that it is not in the GPU)
1969 * 3. Read/written by GPU
1970 * execbuffer calls set_domain (RENDER, RENDER)
1971 * flush_domains gets CPU
1972 * invalidate_domains gets GPU
1974 * MI_FLUSH and drm_agp_chipset_flush
1975 * 4. set_domain (CPU, CPU)
1976 * flush_domains gets GPU
1977 * invalidate_domains gets CPU
1978 * wait_rendering (obj) to make sure all drawing is complete.
1979 * This will include an MI_FLUSH to get the data from GPU
1981 * clflush (obj) to invalidate the CPU cache
1982 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1983 * 5. Read/written by CPU
1984 * cache lines are loaded and dirtied
1985 * 6. Read written by GPU
1986 * Same as last GPU access
1988 * Case 3: The constant buffer
1993 * 4. Updated (written) by CPU again
2002 * flush_domains = CPU
2003 * invalidate_domains = RENDER
2006 * drm_agp_chipset_flush
2007 * 4. Updated (written) by CPU again
2009 * flush_domains = 0 (no previous write domain)
2010 * invalidate_domains = 0 (no new read domains)
2013 * flush_domains = CPU
2014 * invalidate_domains = RENDER
2017 * drm_agp_chipset_flush
2020 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2022 struct drm_device
*dev
= obj
->dev
;
2023 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2024 uint32_t invalidate_domains
= 0;
2025 uint32_t flush_domains
= 0;
2027 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2028 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2031 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2033 obj
->read_domains
, obj
->pending_read_domains
,
2034 obj
->write_domain
, obj
->pending_write_domain
);
2037 * If the object isn't moving to a new write domain,
2038 * let the object stay in multiple read domains
2040 if (obj
->pending_write_domain
== 0)
2041 obj
->pending_read_domains
|= obj
->read_domains
;
2043 obj_priv
->dirty
= 1;
2046 * Flush the current write domain if
2047 * the new read domains don't match. Invalidate
2048 * any read domains which differ from the old
2051 if (obj
->write_domain
&&
2052 obj
->write_domain
!= obj
->pending_read_domains
) {
2053 flush_domains
|= obj
->write_domain
;
2054 invalidate_domains
|=
2055 obj
->pending_read_domains
& ~obj
->write_domain
;
2058 * Invalidate any read caches which may have
2059 * stale data. That is, any new read domains.
2061 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2062 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
2064 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2065 __func__
, flush_domains
, invalidate_domains
);
2067 i915_gem_clflush_object(obj
);
2070 /* The actual obj->write_domain will be updated with
2071 * pending_write_domain after we emit the accumulated flush for all
2072 * of our domain changes in execbuffers (which clears objects'
2073 * write_domains). So if we have a current write domain that we
2074 * aren't changing, set pending_write_domain to that.
2076 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
2077 obj
->pending_write_domain
= obj
->write_domain
;
2078 obj
->read_domains
= obj
->pending_read_domains
;
2080 dev
->invalidate_domains
|= invalidate_domains
;
2081 dev
->flush_domains
|= flush_domains
;
2083 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
2085 obj
->read_domains
, obj
->write_domain
,
2086 dev
->invalidate_domains
, dev
->flush_domains
);
2091 * Moves the object from a partially CPU read to a full one.
2093 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2094 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2097 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
2099 struct drm_device
*dev
= obj
->dev
;
2100 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2102 if (!obj_priv
->page_cpu_valid
)
2105 /* If we're partially in the CPU read domain, finish moving it in.
2107 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
2110 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
2111 if (obj_priv
->page_cpu_valid
[i
])
2113 drm_clflush_pages(obj_priv
->page_list
+ i
, 1);
2115 drm_agp_chipset_flush(dev
);
2118 /* Free the page_cpu_valid mappings which are now stale, whether
2119 * or not we've got I915_GEM_DOMAIN_CPU.
2121 drm_free(obj_priv
->page_cpu_valid
, obj
->size
/ PAGE_SIZE
,
2123 obj_priv
->page_cpu_valid
= NULL
;
2127 * Set the CPU read domain on a range of the object.
2129 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2130 * not entirely valid. The page_cpu_valid member of the object flags which
2131 * pages have been flushed, and will be respected by
2132 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2133 * of the whole object.
2135 * This function returns when the move is complete, including waiting on
2139 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
2140 uint64_t offset
, uint64_t size
)
2142 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2145 if (offset
== 0 && size
== obj
->size
)
2146 return i915_gem_object_set_to_cpu_domain(obj
, 0);
2148 i915_gem_object_flush_gpu_write_domain(obj
);
2149 /* Wait on any GPU rendering and flushing to occur. */
2150 ret
= i915_gem_object_wait_rendering(obj
);
2153 i915_gem_object_flush_gtt_write_domain(obj
);
2155 /* If we're already fully in the CPU read domain, we're done. */
2156 if (obj_priv
->page_cpu_valid
== NULL
&&
2157 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
2160 /* Otherwise, create/clear the per-page CPU read domain flag if we're
2161 * newly adding I915_GEM_DOMAIN_CPU
2163 if (obj_priv
->page_cpu_valid
== NULL
) {
2164 obj_priv
->page_cpu_valid
= drm_calloc(1, obj
->size
/ PAGE_SIZE
,
2166 if (obj_priv
->page_cpu_valid
== NULL
)
2168 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
2169 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
2171 /* Flush the cache on any pages that are still invalid from the CPU's
2174 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
2176 if (obj_priv
->page_cpu_valid
[i
])
2179 drm_clflush_pages(obj_priv
->page_list
+ i
, 1);
2181 obj_priv
->page_cpu_valid
[i
] = 1;
2184 /* It should now be out of any other write domains, and we can update
2185 * the domain values for our changes.
2187 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2189 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2195 * Pin an object to the GTT and evaluate the relocations landing in it.
2198 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
2199 struct drm_file
*file_priv
,
2200 struct drm_i915_gem_exec_object
*entry
)
2202 struct drm_device
*dev
= obj
->dev
;
2203 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2204 struct drm_i915_gem_relocation_entry reloc
;
2205 struct drm_i915_gem_relocation_entry __user
*relocs
;
2206 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2208 void __iomem
*reloc_page
;
2210 /* Choose the GTT offset for our buffer and put it there. */
2211 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
2215 entry
->offset
= obj_priv
->gtt_offset
;
2217 relocs
= (struct drm_i915_gem_relocation_entry __user
*)
2218 (uintptr_t) entry
->relocs_ptr
;
2219 /* Apply the relocations, using the GTT aperture to avoid cache
2220 * flushing requirements.
2222 for (i
= 0; i
< entry
->relocation_count
; i
++) {
2223 struct drm_gem_object
*target_obj
;
2224 struct drm_i915_gem_object
*target_obj_priv
;
2225 uint32_t reloc_val
, reloc_offset
;
2226 uint32_t __iomem
*reloc_entry
;
2228 ret
= copy_from_user(&reloc
, relocs
+ i
, sizeof(reloc
));
2230 i915_gem_object_unpin(obj
);
2234 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
2235 reloc
.target_handle
);
2236 if (target_obj
== NULL
) {
2237 i915_gem_object_unpin(obj
);
2240 target_obj_priv
= target_obj
->driver_private
;
2242 /* The target buffer should have appeared before us in the
2243 * exec_object list, so it should have a GTT space bound by now.
2245 if (target_obj_priv
->gtt_space
== NULL
) {
2246 DRM_ERROR("No GTT space found for object %d\n",
2247 reloc
.target_handle
);
2248 drm_gem_object_unreference(target_obj
);
2249 i915_gem_object_unpin(obj
);
2253 if (reloc
.offset
> obj
->size
- 4) {
2254 DRM_ERROR("Relocation beyond object bounds: "
2255 "obj %p target %d offset %d size %d.\n",
2256 obj
, reloc
.target_handle
,
2257 (int) reloc
.offset
, (int) obj
->size
);
2258 drm_gem_object_unreference(target_obj
);
2259 i915_gem_object_unpin(obj
);
2262 if (reloc
.offset
& 3) {
2263 DRM_ERROR("Relocation not 4-byte aligned: "
2264 "obj %p target %d offset %d.\n",
2265 obj
, reloc
.target_handle
,
2266 (int) reloc
.offset
);
2267 drm_gem_object_unreference(target_obj
);
2268 i915_gem_object_unpin(obj
);
2272 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
2273 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
2274 DRM_ERROR("reloc with read/write CPU domains: "
2275 "obj %p target %d offset %d "
2276 "read %08x write %08x",
2277 obj
, reloc
.target_handle
,
2280 reloc
.write_domain
);
2281 drm_gem_object_unreference(target_obj
);
2282 i915_gem_object_unpin(obj
);
2286 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
2287 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
2288 DRM_ERROR("Write domain conflict: "
2289 "obj %p target %d offset %d "
2290 "new %08x old %08x\n",
2291 obj
, reloc
.target_handle
,
2294 target_obj
->pending_write_domain
);
2295 drm_gem_object_unreference(target_obj
);
2296 i915_gem_object_unpin(obj
);
2301 DRM_INFO("%s: obj %p offset %08x target %d "
2302 "read %08x write %08x gtt %08x "
2303 "presumed %08x delta %08x\n",
2307 (int) reloc
.target_handle
,
2308 (int) reloc
.read_domains
,
2309 (int) reloc
.write_domain
,
2310 (int) target_obj_priv
->gtt_offset
,
2311 (int) reloc
.presumed_offset
,
2315 target_obj
->pending_read_domains
|= reloc
.read_domains
;
2316 target_obj
->pending_write_domain
|= reloc
.write_domain
;
2318 /* If the relocation already has the right value in it, no
2319 * more work needs to be done.
2321 if (target_obj_priv
->gtt_offset
== reloc
.presumed_offset
) {
2322 drm_gem_object_unreference(target_obj
);
2326 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
2328 drm_gem_object_unreference(target_obj
);
2329 i915_gem_object_unpin(obj
);
2333 /* Map the page containing the relocation we're going to
2336 reloc_offset
= obj_priv
->gtt_offset
+ reloc
.offset
;
2337 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
2340 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
2341 (reloc_offset
& (PAGE_SIZE
- 1)));
2342 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
.delta
;
2345 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
2346 obj
, (unsigned int) reloc
.offset
,
2347 readl(reloc_entry
), reloc_val
);
2349 writel(reloc_val
, reloc_entry
);
2350 io_mapping_unmap_atomic(reloc_page
);
2352 /* Write the updated presumed offset for this entry back out
2355 reloc
.presumed_offset
= target_obj_priv
->gtt_offset
;
2356 ret
= copy_to_user(relocs
+ i
, &reloc
, sizeof(reloc
));
2358 drm_gem_object_unreference(target_obj
);
2359 i915_gem_object_unpin(obj
);
2363 drm_gem_object_unreference(target_obj
);
2368 i915_gem_dump_object(obj
, 128, __func__
, ~0);
2373 /** Dispatch a batchbuffer to the ring
2376 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
2377 struct drm_i915_gem_execbuffer
*exec
,
2378 uint64_t exec_offset
)
2380 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2381 struct drm_clip_rect __user
*boxes
= (struct drm_clip_rect __user
*)
2382 (uintptr_t) exec
->cliprects_ptr
;
2383 int nbox
= exec
->num_cliprects
;
2385 uint32_t exec_start
, exec_len
;
2388 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
2389 exec_len
= (uint32_t) exec
->batch_len
;
2391 if ((exec_start
| exec_len
) & 0x7) {
2392 DRM_ERROR("alignment\n");
2399 count
= nbox
? nbox
: 1;
2401 for (i
= 0; i
< count
; i
++) {
2403 int ret
= i915_emit_box(dev
, boxes
, i
,
2404 exec
->DR1
, exec
->DR4
);
2409 if (IS_I830(dev
) || IS_845G(dev
)) {
2411 OUT_RING(MI_BATCH_BUFFER
);
2412 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
2413 OUT_RING(exec_start
+ exec_len
- 4);
2418 if (IS_I965G(dev
)) {
2419 OUT_RING(MI_BATCH_BUFFER_START
|
2421 MI_BATCH_NON_SECURE_I965
);
2422 OUT_RING(exec_start
);
2424 OUT_RING(MI_BATCH_BUFFER_START
|
2426 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
2432 /* XXX breadcrumb */
2436 /* Throttle our rendering by waiting until the ring has completed our requests
2437 * emitted over 20 msec ago.
2439 * This should get us reasonable parallelism between CPU and GPU but also
2440 * relatively low latency when blocking on a particular request to finish.
2443 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
2445 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
2449 mutex_lock(&dev
->struct_mutex
);
2450 seqno
= i915_file_priv
->mm
.last_gem_throttle_seqno
;
2451 i915_file_priv
->mm
.last_gem_throttle_seqno
=
2452 i915_file_priv
->mm
.last_gem_seqno
;
2454 ret
= i915_wait_request(dev
, seqno
);
2455 mutex_unlock(&dev
->struct_mutex
);
2460 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2461 struct drm_file
*file_priv
)
2463 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2464 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
2465 struct drm_i915_gem_execbuffer
*args
= data
;
2466 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
2467 struct drm_gem_object
**object_list
= NULL
;
2468 struct drm_gem_object
*batch_obj
;
2469 int ret
, i
, pinned
= 0;
2470 uint64_t exec_offset
;
2471 uint32_t seqno
, flush_domains
;
2475 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
2476 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
2479 if (args
->buffer_count
< 1) {
2480 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
2483 /* Copy in the exec list from userland */
2484 exec_list
= drm_calloc(sizeof(*exec_list
), args
->buffer_count
,
2486 object_list
= drm_calloc(sizeof(*object_list
), args
->buffer_count
,
2488 if (exec_list
== NULL
|| object_list
== NULL
) {
2489 DRM_ERROR("Failed to allocate exec or object list "
2491 args
->buffer_count
);
2495 ret
= copy_from_user(exec_list
,
2496 (struct drm_i915_relocation_entry __user
*)
2497 (uintptr_t) args
->buffers_ptr
,
2498 sizeof(*exec_list
) * args
->buffer_count
);
2500 DRM_ERROR("copy %d exec entries failed %d\n",
2501 args
->buffer_count
, ret
);
2505 mutex_lock(&dev
->struct_mutex
);
2507 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2509 if (dev_priv
->mm
.wedged
) {
2510 DRM_ERROR("Execbuf while wedged\n");
2511 mutex_unlock(&dev
->struct_mutex
);
2516 if (dev_priv
->mm
.suspended
) {
2517 DRM_ERROR("Execbuf while VT-switched.\n");
2518 mutex_unlock(&dev
->struct_mutex
);
2523 /* Look up object handles */
2524 for (i
= 0; i
< args
->buffer_count
; i
++) {
2525 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
2526 exec_list
[i
].handle
);
2527 if (object_list
[i
] == NULL
) {
2528 DRM_ERROR("Invalid object handle %d at index %d\n",
2529 exec_list
[i
].handle
, i
);
2535 /* Pin and relocate */
2536 for (pin_tries
= 0; ; pin_tries
++) {
2538 for (i
= 0; i
< args
->buffer_count
; i
++) {
2539 object_list
[i
]->pending_read_domains
= 0;
2540 object_list
[i
]->pending_write_domain
= 0;
2541 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
2552 /* error other than GTT full, or we've already tried again */
2553 if (ret
!= -ENOMEM
|| pin_tries
>= 1) {
2554 if (ret
!= -ERESTARTSYS
)
2555 DRM_ERROR("Failed to pin buffers %d\n", ret
);
2559 /* unpin all of our buffers */
2560 for (i
= 0; i
< pinned
; i
++)
2561 i915_gem_object_unpin(object_list
[i
]);
2564 /* evict everyone we can from the aperture */
2565 ret
= i915_gem_evict_everything(dev
);
2570 /* Set the pending read domains for the batch buffer to COMMAND */
2571 batch_obj
= object_list
[args
->buffer_count
-1];
2572 batch_obj
->pending_read_domains
= I915_GEM_DOMAIN_COMMAND
;
2573 batch_obj
->pending_write_domain
= 0;
2575 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2577 /* Zero the global flush/invalidate flags. These
2578 * will be modified as new domains are computed
2581 dev
->invalidate_domains
= 0;
2582 dev
->flush_domains
= 0;
2584 for (i
= 0; i
< args
->buffer_count
; i
++) {
2585 struct drm_gem_object
*obj
= object_list
[i
];
2587 /* Compute new gpu domains and update invalidate/flush */
2588 i915_gem_object_set_to_gpu_domain(obj
);
2591 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2593 if (dev
->invalidate_domains
| dev
->flush_domains
) {
2595 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2597 dev
->invalidate_domains
,
2598 dev
->flush_domains
);
2601 dev
->invalidate_domains
,
2602 dev
->flush_domains
);
2603 if (dev
->flush_domains
)
2604 (void)i915_add_request(dev
, dev
->flush_domains
);
2607 for (i
= 0; i
< args
->buffer_count
; i
++) {
2608 struct drm_gem_object
*obj
= object_list
[i
];
2610 obj
->write_domain
= obj
->pending_write_domain
;
2613 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2616 for (i
= 0; i
< args
->buffer_count
; i
++) {
2617 i915_gem_object_check_coherency(object_list
[i
],
2618 exec_list
[i
].handle
);
2622 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
2625 i915_gem_dump_object(object_list
[args
->buffer_count
- 1],
2631 /* Exec the batchbuffer */
2632 ret
= i915_dispatch_gem_execbuffer(dev
, args
, exec_offset
);
2634 DRM_ERROR("dispatch failed %d\n", ret
);
2639 * Ensure that the commands in the batch buffer are
2640 * finished before the interrupt fires
2642 flush_domains
= i915_retire_commands(dev
);
2644 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2647 * Get a seqno representing the execution of the current buffer,
2648 * which we can wait on. We would like to mitigate these interrupts,
2649 * likely by only creating seqnos occasionally (so that we have
2650 * *some* interrupts representing completion of buffers that we can
2651 * wait on when trying to clear up gtt space).
2653 seqno
= i915_add_request(dev
, flush_domains
);
2655 i915_file_priv
->mm
.last_gem_seqno
= seqno
;
2656 for (i
= 0; i
< args
->buffer_count
; i
++) {
2657 struct drm_gem_object
*obj
= object_list
[i
];
2659 i915_gem_object_move_to_active(obj
, seqno
);
2661 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
2665 i915_dump_lru(dev
, __func__
);
2668 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2671 for (i
= 0; i
< pinned
; i
++)
2672 i915_gem_object_unpin(object_list
[i
]);
2674 for (i
= 0; i
< args
->buffer_count
; i
++)
2675 drm_gem_object_unreference(object_list
[i
]);
2677 mutex_unlock(&dev
->struct_mutex
);
2680 /* Copy the new buffer offsets back to the user's exec list. */
2681 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
2682 (uintptr_t) args
->buffers_ptr
,
2684 sizeof(*exec_list
) * args
->buffer_count
);
2686 DRM_ERROR("failed to copy %d exec entries "
2687 "back to user (%d)\n",
2688 args
->buffer_count
, ret
);
2692 drm_free(object_list
, sizeof(*object_list
) * args
->buffer_count
,
2694 drm_free(exec_list
, sizeof(*exec_list
) * args
->buffer_count
,
2701 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
2703 struct drm_device
*dev
= obj
->dev
;
2704 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2707 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2708 if (obj_priv
->gtt_space
== NULL
) {
2709 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
2711 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
2712 DRM_ERROR("Failure to bind: %d", ret
);
2716 * Pre-965 chips need a fence register set up in order to
2717 * properly handle tiled surfaces.
2719 if (!IS_I965G(dev
) &&
2720 obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
2721 obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2722 i915_gem_object_get_fence_reg(obj
, true);
2724 obj_priv
->pin_count
++;
2726 /* If the object is not active and not pending a flush,
2727 * remove it from the inactive list
2729 if (obj_priv
->pin_count
== 1) {
2730 atomic_inc(&dev
->pin_count
);
2731 atomic_add(obj
->size
, &dev
->pin_memory
);
2732 if (!obj_priv
->active
&&
2733 (obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|
2734 I915_GEM_DOMAIN_GTT
)) == 0 &&
2735 !list_empty(&obj_priv
->list
))
2736 list_del_init(&obj_priv
->list
);
2738 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2744 i915_gem_object_unpin(struct drm_gem_object
*obj
)
2746 struct drm_device
*dev
= obj
->dev
;
2747 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2748 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2750 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2751 obj_priv
->pin_count
--;
2752 BUG_ON(obj_priv
->pin_count
< 0);
2753 BUG_ON(obj_priv
->gtt_space
== NULL
);
2755 /* If the object is no longer pinned, and is
2756 * neither active nor being flushed, then stick it on
2759 if (obj_priv
->pin_count
== 0) {
2760 if (!obj_priv
->active
&&
2761 (obj
->write_domain
& ~(I915_GEM_DOMAIN_CPU
|
2762 I915_GEM_DOMAIN_GTT
)) == 0)
2763 list_move_tail(&obj_priv
->list
,
2764 &dev_priv
->mm
.inactive_list
);
2765 atomic_dec(&dev
->pin_count
);
2766 atomic_sub(obj
->size
, &dev
->pin_memory
);
2768 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
2772 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2773 struct drm_file
*file_priv
)
2775 struct drm_i915_gem_pin
*args
= data
;
2776 struct drm_gem_object
*obj
;
2777 struct drm_i915_gem_object
*obj_priv
;
2780 mutex_lock(&dev
->struct_mutex
);
2782 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2784 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2786 mutex_unlock(&dev
->struct_mutex
);
2789 obj_priv
= obj
->driver_private
;
2791 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
2792 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
2794 drm_gem_object_unreference(obj
);
2795 mutex_unlock(&dev
->struct_mutex
);
2799 obj_priv
->user_pin_count
++;
2800 obj_priv
->pin_filp
= file_priv
;
2801 if (obj_priv
->user_pin_count
== 1) {
2802 ret
= i915_gem_object_pin(obj
, args
->alignment
);
2804 drm_gem_object_unreference(obj
);
2805 mutex_unlock(&dev
->struct_mutex
);
2810 /* XXX - flush the CPU caches for pinned objects
2811 * as the X server doesn't manage domains yet
2813 i915_gem_object_flush_cpu_write_domain(obj
);
2814 args
->offset
= obj_priv
->gtt_offset
;
2815 drm_gem_object_unreference(obj
);
2816 mutex_unlock(&dev
->struct_mutex
);
2822 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2823 struct drm_file
*file_priv
)
2825 struct drm_i915_gem_pin
*args
= data
;
2826 struct drm_gem_object
*obj
;
2827 struct drm_i915_gem_object
*obj_priv
;
2829 mutex_lock(&dev
->struct_mutex
);
2831 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2833 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2835 mutex_unlock(&dev
->struct_mutex
);
2839 obj_priv
= obj
->driver_private
;
2840 if (obj_priv
->pin_filp
!= file_priv
) {
2841 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
2843 drm_gem_object_unreference(obj
);
2844 mutex_unlock(&dev
->struct_mutex
);
2847 obj_priv
->user_pin_count
--;
2848 if (obj_priv
->user_pin_count
== 0) {
2849 obj_priv
->pin_filp
= NULL
;
2850 i915_gem_object_unpin(obj
);
2853 drm_gem_object_unreference(obj
);
2854 mutex_unlock(&dev
->struct_mutex
);
2859 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2860 struct drm_file
*file_priv
)
2862 struct drm_i915_gem_busy
*args
= data
;
2863 struct drm_gem_object
*obj
;
2864 struct drm_i915_gem_object
*obj_priv
;
2866 mutex_lock(&dev
->struct_mutex
);
2867 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
2869 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2871 mutex_unlock(&dev
->struct_mutex
);
2875 /* Update the active list for the hardware's current position.
2876 * Otherwise this only updates on a delayed timer or when irqs are
2877 * actually unmasked, and our working set ends up being larger than
2880 i915_gem_retire_requests(dev
);
2882 obj_priv
= obj
->driver_private
;
2883 /* Don't count being on the flushing list against the object being
2884 * done. Otherwise, a buffer left on the flushing list but not getting
2885 * flushed (because nobody's flushing that domain) won't ever return
2886 * unbusy and get reused by libdrm's bo cache. The other expected
2887 * consumer of this interface, OpenGL's occlusion queries, also specs
2888 * that the objects get unbusy "eventually" without any interference.
2890 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
2892 drm_gem_object_unreference(obj
);
2893 mutex_unlock(&dev
->struct_mutex
);
2898 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2899 struct drm_file
*file_priv
)
2901 return i915_gem_ring_throttle(dev
, file_priv
);
2904 int i915_gem_init_object(struct drm_gem_object
*obj
)
2906 struct drm_i915_gem_object
*obj_priv
;
2908 obj_priv
= drm_calloc(1, sizeof(*obj_priv
), DRM_MEM_DRIVER
);
2909 if (obj_priv
== NULL
)
2913 * We've just allocated pages from the kernel,
2914 * so they've just been written by the CPU with
2915 * zeros. They'll need to be clflushed before we
2916 * use them with the GPU.
2918 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2919 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2921 obj_priv
->agp_type
= AGP_USER_MEMORY
;
2923 obj
->driver_private
= obj_priv
;
2924 obj_priv
->obj
= obj
;
2925 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2926 INIT_LIST_HEAD(&obj_priv
->list
);
2931 void i915_gem_free_object(struct drm_gem_object
*obj
)
2933 struct drm_device
*dev
= obj
->dev
;
2934 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2936 while (obj_priv
->pin_count
> 0)
2937 i915_gem_object_unpin(obj
);
2939 if (obj_priv
->phys_obj
)
2940 i915_gem_detach_phys_object(dev
, obj
);
2942 i915_gem_object_unbind(obj
);
2944 i915_gem_free_mmap_offset(obj
);
2946 drm_free(obj_priv
->page_cpu_valid
, 1, DRM_MEM_DRIVER
);
2947 drm_free(obj
->driver_private
, 1, DRM_MEM_DRIVER
);
2950 /** Unbinds all objects that are on the given buffer list. */
2952 i915_gem_evict_from_list(struct drm_device
*dev
, struct list_head
*head
)
2954 struct drm_gem_object
*obj
;
2955 struct drm_i915_gem_object
*obj_priv
;
2958 while (!list_empty(head
)) {
2959 obj_priv
= list_first_entry(head
,
2960 struct drm_i915_gem_object
,
2962 obj
= obj_priv
->obj
;
2964 if (obj_priv
->pin_count
!= 0) {
2965 DRM_ERROR("Pinned object in unbind list\n");
2966 mutex_unlock(&dev
->struct_mutex
);
2970 ret
= i915_gem_object_unbind(obj
);
2972 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2974 mutex_unlock(&dev
->struct_mutex
);
2984 i915_gem_idle(struct drm_device
*dev
)
2986 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2987 uint32_t seqno
, cur_seqno
, last_seqno
;
2990 mutex_lock(&dev
->struct_mutex
);
2992 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
2993 mutex_unlock(&dev
->struct_mutex
);
2997 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2998 * We need to replace this with a semaphore, or something.
3000 dev_priv
->mm
.suspended
= 1;
3002 /* Cancel the retire work handler, wait for it to finish if running
3004 mutex_unlock(&dev
->struct_mutex
);
3005 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3006 mutex_lock(&dev
->struct_mutex
);
3008 i915_kernel_lost_context(dev
);
3010 /* Flush the GPU along with all non-CPU write domains
3012 i915_gem_flush(dev
, ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
),
3013 ~(I915_GEM_DOMAIN_CPU
|I915_GEM_DOMAIN_GTT
));
3014 seqno
= i915_add_request(dev
, ~I915_GEM_DOMAIN_CPU
);
3017 mutex_unlock(&dev
->struct_mutex
);
3021 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
3025 cur_seqno
= i915_get_gem_seqno(dev
);
3026 if (i915_seqno_passed(cur_seqno
, seqno
))
3028 if (last_seqno
== cur_seqno
) {
3029 if (stuck
++ > 100) {
3030 DRM_ERROR("hardware wedged\n");
3031 dev_priv
->mm
.wedged
= 1;
3032 DRM_WAKEUP(&dev_priv
->irq_queue
);
3037 last_seqno
= cur_seqno
;
3039 dev_priv
->mm
.waiting_gem_seqno
= 0;
3041 i915_gem_retire_requests(dev
);
3043 if (!dev_priv
->mm
.wedged
) {
3044 /* Active and flushing should now be empty as we've
3045 * waited for a sequence higher than any pending execbuffer
3047 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
3048 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3049 /* Request should now be empty as we've also waited
3050 * for the last request in the list
3052 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
3055 /* Empty the active and flushing lists to inactive. If there's
3056 * anything left at this point, it means that we're wedged and
3057 * nothing good's going to happen by leaving them there. So strip
3058 * the GPU domains and just stuff them onto inactive.
3060 while (!list_empty(&dev_priv
->mm
.active_list
)) {
3061 struct drm_i915_gem_object
*obj_priv
;
3063 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
3064 struct drm_i915_gem_object
,
3066 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
3067 i915_gem_object_move_to_inactive(obj_priv
->obj
);
3070 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
3071 struct drm_i915_gem_object
*obj_priv
;
3073 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
3074 struct drm_i915_gem_object
,
3076 obj_priv
->obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
3077 i915_gem_object_move_to_inactive(obj_priv
->obj
);
3081 /* Move all inactive buffers out of the GTT. */
3082 ret
= i915_gem_evict_from_list(dev
, &dev_priv
->mm
.inactive_list
);
3083 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3085 mutex_unlock(&dev
->struct_mutex
);
3089 i915_gem_cleanup_ringbuffer(dev
);
3090 mutex_unlock(&dev
->struct_mutex
);
3096 i915_gem_init_hws(struct drm_device
*dev
)
3098 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3099 struct drm_gem_object
*obj
;
3100 struct drm_i915_gem_object
*obj_priv
;
3103 /* If we need a physical address for the status page, it's already
3104 * initialized at driver load time.
3106 if (!I915_NEED_GFX_HWS(dev
))
3109 obj
= drm_gem_object_alloc(dev
, 4096);
3111 DRM_ERROR("Failed to allocate status page\n");
3114 obj_priv
= obj
->driver_private
;
3115 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
3117 ret
= i915_gem_object_pin(obj
, 4096);
3119 drm_gem_object_unreference(obj
);
3123 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
3125 dev_priv
->hw_status_page
= kmap(obj_priv
->page_list
[0]);
3126 if (dev_priv
->hw_status_page
== NULL
) {
3127 DRM_ERROR("Failed to map status page.\n");
3128 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
3129 i915_gem_object_unpin(obj
);
3130 drm_gem_object_unreference(obj
);
3133 dev_priv
->hws_obj
= obj
;
3134 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
3135 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
3136 I915_READ(HWS_PGA
); /* posting read */
3137 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
3143 i915_gem_cleanup_hws(struct drm_device
*dev
)
3145 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3146 struct drm_gem_object
*obj
;
3147 struct drm_i915_gem_object
*obj_priv
;
3149 if (dev_priv
->hws_obj
== NULL
)
3152 obj
= dev_priv
->hws_obj
;
3153 obj_priv
= obj
->driver_private
;
3155 kunmap(obj_priv
->page_list
[0]);
3156 i915_gem_object_unpin(obj
);
3157 drm_gem_object_unreference(obj
);
3158 dev_priv
->hws_obj
= NULL
;
3160 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
3161 dev_priv
->hw_status_page
= NULL
;
3163 /* Write high address into HWS_PGA when disabling. */
3164 I915_WRITE(HWS_PGA
, 0x1ffff000);
3168 i915_gem_init_ringbuffer(struct drm_device
*dev
)
3170 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3171 struct drm_gem_object
*obj
;
3172 struct drm_i915_gem_object
*obj_priv
;
3173 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
3177 ret
= i915_gem_init_hws(dev
);
3181 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
3183 DRM_ERROR("Failed to allocate ringbuffer\n");
3184 i915_gem_cleanup_hws(dev
);
3187 obj_priv
= obj
->driver_private
;
3189 ret
= i915_gem_object_pin(obj
, 4096);
3191 drm_gem_object_unreference(obj
);
3192 i915_gem_cleanup_hws(dev
);
3196 /* Set up the kernel mapping for the ring. */
3197 ring
->Size
= obj
->size
;
3198 ring
->tail_mask
= obj
->size
- 1;
3200 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
3201 ring
->map
.size
= obj
->size
;
3203 ring
->map
.flags
= 0;
3206 drm_core_ioremap_wc(&ring
->map
, dev
);
3207 if (ring
->map
.handle
== NULL
) {
3208 DRM_ERROR("Failed to map ringbuffer.\n");
3209 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
3210 i915_gem_object_unpin(obj
);
3211 drm_gem_object_unreference(obj
);
3212 i915_gem_cleanup_hws(dev
);
3215 ring
->ring_obj
= obj
;
3216 ring
->virtual_start
= ring
->map
.handle
;
3218 /* Stop the ring if it's running. */
3219 I915_WRITE(PRB0_CTL
, 0);
3220 I915_WRITE(PRB0_TAIL
, 0);
3221 I915_WRITE(PRB0_HEAD
, 0);
3223 /* Initialize the ring. */
3224 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
3225 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
3227 /* G45 ring initialization fails to reset head to zero */
3229 DRM_ERROR("Ring head not reset to zero "
3230 "ctl %08x head %08x tail %08x start %08x\n",
3231 I915_READ(PRB0_CTL
),
3232 I915_READ(PRB0_HEAD
),
3233 I915_READ(PRB0_TAIL
),
3234 I915_READ(PRB0_START
));
3235 I915_WRITE(PRB0_HEAD
, 0);
3237 DRM_ERROR("Ring head forced to zero "
3238 "ctl %08x head %08x tail %08x start %08x\n",
3239 I915_READ(PRB0_CTL
),
3240 I915_READ(PRB0_HEAD
),
3241 I915_READ(PRB0_TAIL
),
3242 I915_READ(PRB0_START
));
3245 I915_WRITE(PRB0_CTL
,
3246 ((obj
->size
- 4096) & RING_NR_PAGES
) |
3250 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
3252 /* If the head is still not zero, the ring is dead */
3254 DRM_ERROR("Ring initialization failed "
3255 "ctl %08x head %08x tail %08x start %08x\n",
3256 I915_READ(PRB0_CTL
),
3257 I915_READ(PRB0_HEAD
),
3258 I915_READ(PRB0_TAIL
),
3259 I915_READ(PRB0_START
));
3263 /* Update our cache of the ring state */
3264 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3265 i915_kernel_lost_context(dev
);
3267 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
3268 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
3269 ring
->space
= ring
->head
- (ring
->tail
+ 8);
3270 if (ring
->space
< 0)
3271 ring
->space
+= ring
->Size
;
3278 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3280 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3282 if (dev_priv
->ring
.ring_obj
== NULL
)
3285 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
3287 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
3288 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
3289 dev_priv
->ring
.ring_obj
= NULL
;
3290 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
3292 i915_gem_cleanup_hws(dev
);
3296 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3297 struct drm_file
*file_priv
)
3299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3302 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3305 if (dev_priv
->mm
.wedged
) {
3306 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3307 dev_priv
->mm
.wedged
= 0;
3310 mutex_lock(&dev
->struct_mutex
);
3311 dev_priv
->mm
.suspended
= 0;
3313 ret
= i915_gem_init_ringbuffer(dev
);
3317 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3318 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3319 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3320 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
3321 mutex_unlock(&dev
->struct_mutex
);
3323 drm_irq_install(dev
);
3329 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3330 struct drm_file
*file_priv
)
3334 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3337 ret
= i915_gem_idle(dev
);
3338 drm_irq_uninstall(dev
);
3344 i915_gem_lastclose(struct drm_device
*dev
)
3348 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3351 ret
= i915_gem_idle(dev
);
3353 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3357 i915_gem_load(struct drm_device
*dev
)
3359 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3361 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3362 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3363 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3364 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
3365 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3366 i915_gem_retire_work_handler
);
3367 dev_priv
->mm
.next_gem_seqno
= 1;
3369 /* Old X drivers will take 0-2 for front, back, depth buffers */
3370 dev_priv
->fence_reg_start
= 3;
3372 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3373 dev_priv
->num_fence_regs
= 16;
3375 dev_priv
->num_fence_regs
= 8;
3377 i915_gem_detect_bit_6_swizzle(dev
);
3381 * Create a physically contiguous memory object for this object
3382 * e.g. for cursor + overlay regs
3384 int i915_gem_init_phys_object(struct drm_device
*dev
,
3387 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3388 struct drm_i915_gem_phys_object
*phys_obj
;
3391 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3394 phys_obj
= drm_calloc(1, sizeof(struct drm_i915_gem_phys_object
), DRM_MEM_DRIVER
);
3400 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0, 0xffffffff);
3401 if (!phys_obj
->handle
) {
3406 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3409 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3413 drm_free(phys_obj
, sizeof(struct drm_i915_gem_phys_object
), DRM_MEM_DRIVER
);
3417 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3419 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3420 struct drm_i915_gem_phys_object
*phys_obj
;
3422 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3425 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3426 if (phys_obj
->cur_obj
) {
3427 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3431 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3433 drm_pci_free(dev
, phys_obj
->handle
);
3435 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3438 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3442 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3443 i915_gem_free_phys_object(dev
, i
);
3446 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3447 struct drm_gem_object
*obj
)
3449 struct drm_i915_gem_object
*obj_priv
;
3454 obj_priv
= obj
->driver_private
;
3455 if (!obj_priv
->phys_obj
)
3458 ret
= i915_gem_object_get_page_list(obj
);
3462 page_count
= obj
->size
/ PAGE_SIZE
;
3464 for (i
= 0; i
< page_count
; i
++) {
3465 char *dst
= kmap_atomic(obj_priv
->page_list
[i
], KM_USER0
);
3466 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3468 memcpy(dst
, src
, PAGE_SIZE
);
3469 kunmap_atomic(dst
, KM_USER0
);
3471 drm_clflush_pages(obj_priv
->page_list
, page_count
);
3472 drm_agp_chipset_flush(dev
);
3474 obj_priv
->phys_obj
->cur_obj
= NULL
;
3475 obj_priv
->phys_obj
= NULL
;
3479 i915_gem_attach_phys_object(struct drm_device
*dev
,
3480 struct drm_gem_object
*obj
, int id
)
3482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3483 struct drm_i915_gem_object
*obj_priv
;
3488 if (id
> I915_MAX_PHYS_OBJECT
)
3491 obj_priv
= obj
->driver_private
;
3493 if (obj_priv
->phys_obj
) {
3494 if (obj_priv
->phys_obj
->id
== id
)
3496 i915_gem_detach_phys_object(dev
, obj
);
3500 /* create a new object */
3501 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3502 ret
= i915_gem_init_phys_object(dev
, id
,
3505 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
3510 /* bind to the object */
3511 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3512 obj_priv
->phys_obj
->cur_obj
= obj
;
3514 ret
= i915_gem_object_get_page_list(obj
);
3516 DRM_ERROR("failed to get page list\n");
3520 page_count
= obj
->size
/ PAGE_SIZE
;
3522 for (i
= 0; i
< page_count
; i
++) {
3523 char *src
= kmap_atomic(obj_priv
->page_list
[i
], KM_USER0
);
3524 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3526 memcpy(dst
, src
, PAGE_SIZE
);
3527 kunmap_atomic(src
, KM_USER0
);
3536 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
3537 struct drm_i915_gem_pwrite
*args
,
3538 struct drm_file
*file_priv
)
3540 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3543 char __user
*user_data
;
3545 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
3546 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
3548 DRM_ERROR("obj_addr %p, %lld\n", obj_addr
, args
->size
);
3549 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
3553 drm_agp_chipset_flush(dev
);