arch/mips/kernel/traps.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
   7  * Copyright (C) 1995, 1996 Paul M. Antoine
   8  * Copyright (C) 1998 Ulf Carlsson
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  11  * Copyright (C) 2000, 01 MIPS Technologies, Inc.
  12  * Copyright (C) 2002, 2003, 2004, 2005  Maciej W. Rozycki
  13  */
  14 #include <linux/init.h>
  15 #include <linux/mm.h>
  16 #include <linux/module.h>
  17 #include <linux/sched.h>
  18 #include <linux/smp.h>
  19 #include <linux/smp_lock.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kallsyms.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/interrupt.h>
  24
  25 #include <asm/bootinfo.h>
  26 #include <asm/branch.h>
  27 #include <asm/break.h>
  28 #include <asm/cpu.h>
  29 #include <asm/dsp.h>
  30 #include <asm/fpu.h>
  31 #include <asm/mipsregs.h>
  32 #include <asm/mipsmtregs.h>
  33 #include <asm/module.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/ptrace.h>
  36 #include <asm/sections.h>
  37 #include <asm/system.h>
  38 #include <asm/tlbdebug.h>
  39 #include <asm/traps.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/mmu_context.h>
  42 #include <asm/watch.h>
  43 #include <asm/types.h>
  44 #include <asm/stacktrace.h>
  45
  46 extern asmlinkage void handle_int(void);
  47 extern asmlinkage void handle_tlbm(void);
  48 extern asmlinkage void handle_tlbl(void);
  49 extern asmlinkage void handle_tlbs(void);
  50 extern asmlinkage void handle_adel(void);
  51 extern asmlinkage void handle_ades(void);
  52 extern asmlinkage void handle_ibe(void);
  53 extern asmlinkage void handle_dbe(void);
  54 extern asmlinkage void handle_sys(void);
  55 extern asmlinkage void handle_bp(void);
  56 extern asmlinkage void handle_ri(void);
  57 extern asmlinkage void handle_ri_rdhwr_vivt(void);
  58 extern asmlinkage void handle_ri_rdhwr(void);
  59 extern asmlinkage void handle_cpu(void);
  60 extern asmlinkage void handle_ov(void);
  61 extern asmlinkage void handle_tr(void);
  62 extern asmlinkage void handle_fpe(void);
  63 extern asmlinkage void handle_mdmx(void);
  64 extern asmlinkage void handle_watch(void);
  65 extern asmlinkage void handle_mt(void);
  66 extern asmlinkage void handle_dsp(void);
  67 extern asmlinkage void handle_mcheck(void);
  68 extern asmlinkage void handle_reserved(void);
  69
  70 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
  71         struct mips_fpu_struct *ctx, int has_fpu);
  72
  73 void (*board_be_init)(void);
  74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  75 void (*board_nmi_handler_setup)(void);
  76 void (*board_ejtag_handler_setup)(void);
  77 void (*board_bind_eic_interrupt)(int irq, int regset);
  78
  79
  80 static void show_raw_backtrace(unsigned long reg29)
  81 {
  82         unsigned long *sp = (unsigned long *)reg29;
  83         unsigned long addr;
  84
  85         printk("Call Trace:");
  86 #ifdef CONFIG_KALLSYMS
  87         printk("\n");
  88 #endif
  89         while (!kstack_end(sp)) {
  90                 addr = *sp++;
  91                 if (__kernel_text_address(addr))
  92                         print_ip_sym(addr);
  93         }
  94         printk("\n");
  95 }
  96
  97 #ifdef CONFIG_KALLSYMS
  98 int raw_show_trace;
  99 static int __init set_raw_show_trace(char *str)
 100 {
 101         raw_show_trace = 1;
 102         return 1;
 103 }
 104 __setup("raw_show_trace", set_raw_show_trace);
 105 #endif
 106
 107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
 108 {
 109         unsigned long sp = regs->regs[29];
 110         unsigned long ra = regs->regs[31];
 111         unsigned long pc = regs->cp0_epc;
 112
 113         if (raw_show_trace || !__kernel_text_address(pc)) {
 114                 show_raw_backtrace(sp);
 115                 return;
 116         }
 117         printk("Call Trace:\n");
 118         do {
 119                 print_ip_sym(pc);
 120                 pc = unwind_stack(task, &sp, pc, &ra);
 121         } while (pc);
 122         printk("\n");
 123 }
 124
 125 /*
 126  * This routine abuses get_user()/put_user() to reference pointers
 127  * with at least a bit of error checking ...
 128  */
 129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
 130 {
 131         const int field = 2 * sizeof(unsigned long);
 132         long stackdata;
 133         int i;
 134         unsigned long *sp = (unsigned long *)regs->regs[29];
 135
 136         printk("Stack :");
 137         i = 0;
 138         while ((unsigned long) sp & (PAGE_SIZE - 1)) {
 139                 if (i && ((i % (64 / field)) == 0))
 140                         printk("\n       ");
 141                 if (i > 39) {
 142                         printk(" ...");
 143                         break;
 144                 }
 145
 146                 if (__get_user(stackdata, sp++)) {
 147                         printk(" (Bad stack address)");
 148                         break;
 149                 }
 150
 151                 printk(" %0*lx", field, stackdata);
 152                 i++;
 153         }
 154         printk("\n");
 155         show_backtrace(task, regs);
 156 }
 157
 158 void show_stack(struct task_struct *task, unsigned long *sp)
 159 {
 160         struct pt_regs regs;
 161         if (sp) {
 162                 regs.regs[29] = (unsigned long)sp;
 163                 regs.regs[31] = 0;
 164                 regs.cp0_epc = 0;
 165         } else {
 166                 if (task && task != current) {
 167                         regs.regs[29] = task->thread.reg29;
 168                         regs.regs[31] = 0;
 169                         regs.cp0_epc = task->thread.reg31;
 170                 } else {
 171                         prepare_frametrace(&regs);
 172                 }
 173         }
 174         show_stacktrace(task, &regs);
 175 }
 176
 177 /*
 178  * The architecture-independent dump_stack generator
 179  */
 180 void dump_stack(void)
 181 {
 182         struct pt_regs regs;
 183
 184         prepare_frametrace(&regs);
 185         show_backtrace(current, &regs);
 186 }
 187
 188 EXPORT_SYMBOL(dump_stack);
 189
 190 void show_code(unsigned int *pc)
 191 {
 192         long i;
 193
 194         printk("\nCode:");
 195
 196         for(i = -3 ; i < 6 ; i++) {
 197                 unsigned int insn;
 198                 if (__get_user(insn, pc + i)) {
 199                         printk(" (Bad address in epc)\n");
 200                         break;
 201                 }
 202                 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
 203         }
 204 }
 205
 206 void show_regs(struct pt_regs *regs)
 207 {
 208         const int field = 2 * sizeof(unsigned long);
 209         unsigned int cause = regs->cp0_cause;
 210         int i;
 211
 212         printk("Cpu %d\n", smp_processor_id());
 213
 214         /*
 215          * Saved main processor registers
 216          */
 217         for (i = 0; i < 32; ) {
 218                 if ((i % 4) == 0)
 219                         printk("$%2d   :", i);
 220                 if (i == 0)
 221                         printk(" %0*lx", field, 0UL);
 222                 else if (i == 26 || i == 27)
 223                         printk(" %*s", field, "");
 224                 else
 225                         printk(" %0*lx", field, regs->regs[i]);
 226
 227                 i++;
 228                 if ((i % 4) == 0)
 229                         printk("\n");
 230         }
 231
 232 #ifdef CONFIG_CPU_HAS_SMARTMIPS
 233         printk("Acx    : %0*lx\n", field, regs->acx);
 234 #endif
 235         printk("Hi    : %0*lx\n", field, regs->hi);
 236         printk("Lo    : %0*lx\n", field, regs->lo);
 237
 238         /*
 239          * Saved cp0 registers
 240          */
 241         printk("epc   : %0*lx ", field, regs->cp0_epc);
 242         print_symbol("%s ", regs->cp0_epc);
 243         printk("    %s\n", print_tainted());
 244         printk("ra    : %0*lx ", field, regs->regs[31]);
 245         print_symbol("%s\n", regs->regs[31]);
 246
 247         printk("Status: %08x    ", (uint32_t) regs->cp0_status);
 248
 249         if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
 250                 if (regs->cp0_status & ST0_KUO)
 251                         printk("KUo ");
 252                 if (regs->cp0_status & ST0_IEO)
 253                         printk("IEo ");
 254                 if (regs->cp0_status & ST0_KUP)
 255                         printk("KUp ");
 256                 if (regs->cp0_status & ST0_IEP)
 257                         printk("IEp ");
 258                 if (regs->cp0_status & ST0_KUC)
 259                         printk("KUc ");
 260                 if (regs->cp0_status & ST0_IEC)
 261                         printk("IEc ");
 262         } else {
 263                 if (regs->cp0_status & ST0_KX)
 264                         printk("KX ");
 265                 if (regs->cp0_status & ST0_SX)
 266                         printk("SX ");
 267                 if (regs->cp0_status & ST0_UX)
 268                         printk("UX ");
 269                 switch (regs->cp0_status & ST0_KSU) {
 270                 case KSU_USER:
 271                         printk("USER ");
 272                         break;
 273                 case KSU_SUPERVISOR:
 274                         printk("SUPERVISOR ");
 275                         break;
 276                 case KSU_KERNEL:
 277                         printk("KERNEL ");
 278                         break;
 279                 default:
 280                         printk("BAD_MODE ");
 281                         break;
 282                 }
 283                 if (regs->cp0_status & ST0_ERL)
 284                         printk("ERL ");
 285                 if (regs->cp0_status & ST0_EXL)
 286                         printk("EXL ");
 287                 if (regs->cp0_status & ST0_IE)
 288                         printk("IE ");
 289         }
 290         printk("\n");
 291
 292         printk("Cause : %08x\n", cause);
 293
 294         cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
 295         if (1 <= cause && cause <= 5)
 296                 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 297
 298         printk("PrId  : %08x\n", read_c0_prid());
 299 }
 300
 301 void show_registers(struct pt_regs *regs)
 302 {
 303         show_regs(regs);
 304         print_modules();
 305         printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 306                 current->comm, current->pid, current_thread_info(), current);
 307         show_stacktrace(current, regs);
 308         show_code((unsigned int *) regs->cp0_epc);
 309         printk("\n");
 310 }
 311
 312 static DEFINE_SPINLOCK(die_lock);
 313
 314 NORET_TYPE void ATTRIB_NORET die(const char * str, struct pt_regs * regs)
 315 {
 316         static int die_counter;
 317 #ifdef CONFIG_MIPS_MT_SMTC
 318         unsigned long dvpret = dvpe();
 319 #endif /* CONFIG_MIPS_MT_SMTC */
 320
 321         console_verbose();
 322         spin_lock_irq(&die_lock);
 323         bust_spinlocks(1);
 324 #ifdef CONFIG_MIPS_MT_SMTC
 325         mips_mt_regdump(dvpret);
 326 #endif /* CONFIG_MIPS_MT_SMTC */
 327         printk("%s[#%d]:\n", str, ++die_counter);
 328         show_registers(regs);
 329         spin_unlock_irq(&die_lock);
 330
 331         if (in_interrupt())
 332                 panic("Fatal exception in interrupt");
 333
 334         if (panic_on_oops) {
 335                 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
 336                 ssleep(5);
 337                 panic("Fatal exception");
 338         }
 339
 340         do_exit(SIGSEGV);
 341 }
 342
 343 extern const struct exception_table_entry __start___dbe_table[];
 344 extern const struct exception_table_entry __stop___dbe_table[];
 345
 346 __asm__(
 347 "       .section        __dbe_table, \"a\"\n"
 348 "       .previous                       \n");
 349
 350 /* Given an address, look for it in the exception tables. */
 351 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
 352 {
 353         const struct exception_table_entry *e;
 354
 355         e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
 356         if (!e)
 357                 e = search_module_dbetables(addr);
 358         return e;
 359 }
 360
 361 asmlinkage void do_be(struct pt_regs *regs)
 362 {
 363         const int field = 2 * sizeof(unsigned long);
 364         const struct exception_table_entry *fixup = NULL;
 365         int data = regs->cp0_cause & 4;
 366         int action = MIPS_BE_FATAL;
 367
 368         /* XXX For now.  Fixme, this searches the wrong table ...  */
 369         if (data && !user_mode(regs))
 370                 fixup = search_dbe_tables(exception_epc(regs));
 371
 372         if (fixup)
 373                 action = MIPS_BE_FIXUP;
 374
 375         if (board_be_handler)
 376                 action = board_be_handler(regs, fixup != 0);
 377
 378         switch (action) {
 379         case MIPS_BE_DISCARD:
 380                 return;
 381         case MIPS_BE_FIXUP:
 382                 if (fixup) {
 383                         regs->cp0_epc = fixup->nextinsn;
 384                         return;
 385                 }
 386                 break;
 387         default:
 388                 break;
 389         }
 390
 391         /*
 392          * Assume it would be too dangerous to continue ...
 393          */
 394         printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
 395                data ? "Data" : "Instruction",
 396                field, regs->cp0_epc, field, regs->regs[31]);
 397         die_if_kernel("Oops", regs);
 398         force_sig(SIGBUS, current);
 399 }
 400
 401 /*
 402  * ll/sc emulation
 403  */
 404
 405 #define OPCODE 0xfc000000
 406 #define BASE   0x03e00000
 407 #define RT     0x001f0000
 408 #define OFFSET 0x0000ffff
 409 #define LL     0xc0000000
 410 #define SC     0xe0000000
 411 #define SPEC3  0x7c000000
 412 #define RD     0x0000f800
 413 #define FUNC   0x0000003f
 414 #define RDHWR  0x0000003b
 415
 416 /*
 417  * The ll_bit is cleared by r*_switch.S
 418  */
 419
 420 unsigned long ll_bit;
 421
 422 static struct task_struct *ll_task = NULL;
 423
 424 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
 425 {
 426         unsigned long value, __user *vaddr;
 427         long offset;
 428         int signal = 0;
 429
 430         /*
 431          * analyse the ll instruction that just caused a ri exception
 432          * and put the referenced address to addr.
 433          */
 434
 435         /* sign extend offset */
 436         offset = opcode & OFFSET;
 437         offset <<= 16;
 438         offset >>= 16;
 439
 440         vaddr = (unsigned long __user *)
 441                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 442
 443         if ((unsigned long)vaddr & 3) {
 444                 signal = SIGBUS;
 445                 goto sig;
 446         }
 447         if (get_user(value, vaddr)) {
 448                 signal = SIGSEGV;
 449                 goto sig;
 450         }
 451
 452         preempt_disable();
 453
 454         if (ll_task == NULL || ll_task == current) {
 455                 ll_bit = 1;
 456         } else {
 457                 ll_bit = 0;
 458         }
 459         ll_task = current;
 460
 461         preempt_enable();
 462
 463         compute_return_epc(regs);
 464
 465         regs->regs[(opcode & RT) >> 16] = value;
 466
 467         return;
 468
 469 sig:
 470         force_sig(signal, current);
 471 }
 472
 473 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
 474 {
 475         unsigned long __user *vaddr;
 476         unsigned long reg;
 477         long offset;
 478         int signal = 0;
 479
 480         /*
 481          * analyse the sc instruction that just caused a ri exception
 482          * and put the referenced address to addr.
 483          */
 484
 485         /* sign extend offset */
 486         offset = opcode & OFFSET;
 487         offset <<= 16;
 488         offset >>= 16;
 489
 490         vaddr = (unsigned long __user *)
 491                 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
 492         reg = (opcode & RT) >> 16;
 493
 494         if ((unsigned long)vaddr & 3) {
 495                 signal = SIGBUS;
 496                 goto sig;
 497         }
 498
 499         preempt_disable();
 500
 501         if (ll_bit == 0 || ll_task != current) {
 502                 compute_return_epc(regs);
 503                 regs->regs[reg] = 0;
 504                 preempt_enable();
 505                 return;
 506         }
 507
 508         preempt_enable();
 509
 510         if (put_user(regs->regs[reg], vaddr)) {
 511                 signal = SIGSEGV;
 512                 goto sig;
 513         }
 514
 515         compute_return_epc(regs);
 516         regs->regs[reg] = 1;
 517
 518         return;
 519
 520 sig:
 521         force_sig(signal, current);
 522 }
 523
 524 /*
 525  * ll uses the opcode of lwc0 and sc uses the opcode of swc0.  That is both
 526  * opcodes are supposed to result in coprocessor unusable exceptions if
 527  * executed on ll/sc-less processors.  That's the theory.  In practice a
 528  * few processors such as NEC's VR4100 throw reserved instruction exceptions
 529  * instead, so we're doing the emulation thing in both exception handlers.
 530  */
 531 static inline int simulate_llsc(struct pt_regs *regs)
 532 {
 533         unsigned int opcode;
 534
 535         if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 536                 goto out_sigsegv;
 537
 538         if ((opcode & OPCODE) == LL) {
 539                 simulate_ll(regs, opcode);
 540                 return 0;
 541         }
 542         if ((opcode & OPCODE) == SC) {
 543                 simulate_sc(regs, opcode);
 544                 return 0;
 545         }
 546
 547         return -EFAULT;                 /* Strange things going on ... */
 548
 549 out_sigsegv:
 550         force_sig(SIGSEGV, current);
 551         return -EFAULT;
 552 }
 553
 554 /*
 555  * Simulate trapping 'rdhwr' instructions to provide user accessible
 556  * registers not implemented in hardware.  The only current use of this
 557  * is the thread area pointer.
 558  */
 559 static inline int simulate_rdhwr(struct pt_regs *regs)
 560 {
 561         struct thread_info *ti = task_thread_info(current);
 562         unsigned int opcode;
 563
 564         if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 565                 goto out_sigsegv;
 566
 567         if (unlikely(compute_return_epc(regs)))
 568                 return -EFAULT;
 569
 570         if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 571                 int rd = (opcode & RD) >> 11;
 572                 int rt = (opcode & RT) >> 16;
 573                 switch (rd) {
 574                         case 29:
 575                                 regs->regs[rt] = ti->tp_value;
 576                                 return 0;
 577                         default:
 578                                 return -EFAULT;
 579                 }
 580         }
 581
 582         /* Not ours.  */
 583         return -EFAULT;
 584
 585 out_sigsegv:
 586         force_sig(SIGSEGV, current);
 587         return -EFAULT;
 588 }
 589
 590 asmlinkage void do_ov(struct pt_regs *regs)
 591 {
 592         siginfo_t info;
 593
 594         die_if_kernel("Integer overflow", regs);
 595
 596         info.si_code = FPE_INTOVF;
 597         info.si_signo = SIGFPE;
 598         info.si_errno = 0;
 599         info.si_addr = (void __user *) regs->cp0_epc;
 600         force_sig_info(SIGFPE, &info, current);
 601 }
 602
 603 /*
 604  * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
 605  */
 606 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
 607 {
 608         die_if_kernel("FP exception in kernel code", regs);
 609
 610         if (fcr31 & FPU_CSR_UNI_X) {
 611                 int sig;
 612
 613                 /*
 614                  * Unimplemented operation exception.  If we've got the full
 615                  * software emulator on-board, let's use it...
 616                  *
 617                  * Force FPU to dump state into task/thread context.  We're
 618                  * moving a lot of data here for what is probably a single
 619                  * instruction, but the alternative is to pre-decode the FP
 620                  * register operands before invoking the emulator, which seems
 621                  * a bit extreme for what should be an infrequent event.
 622                  */
 623                 /* Ensure 'resume' not overwrite saved fp context again. */
 624                 lose_fpu(1);
 625
 626                 /* Run the emulator */
 627                 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1);
 628
 629                 /*
 630                  * We can't allow the emulated instruction to leave any of
 631                  * the cause bit set in $fcr31.
 632                  */
 633                 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 634
 635                 /* Restore the hardware register state */
 636                 own_fpu(1);     /* Using the FPU again.  */
 637
 638                 /* If something went wrong, signal */
 639                 if (sig)
 640                         force_sig(sig, current);
 641
 642                 return;
 643         }
 644
 645         force_sig(SIGFPE, current);
 646 }
 647
 648 asmlinkage void do_bp(struct pt_regs *regs)
 649 {
 650         unsigned int opcode, bcode;
 651         siginfo_t info;
 652
 653         if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 654                 goto out_sigsegv;
 655
 656         /*
 657          * There is the ancient bug in the MIPS assemblers that the break
 658          * code starts left to bit 16 instead to bit 6 in the opcode.
 659          * Gas is bug-compatible, but not always, grrr...
 660          * We handle both cases with a simple heuristics.  --macro
 661          */
 662         bcode = ((opcode >> 6) & ((1 << 20) - 1));
 663         if (bcode < (1 << 10))
 664                 bcode <<= 10;
 665
 666         /*
 667          * (A short test says that IRIX 5.3 sends SIGTRAP for all break
 668          * insns, even for break codes that indicate arithmetic failures.
 669          * Weird ...)
 670          * But should we continue the brokenness???  --macro
 671          */
 672         switch (bcode) {
 673         case BRK_OVERFLOW << 10:
 674         case BRK_DIVZERO << 10:
 675                 die_if_kernel("Break instruction in kernel code", regs);
 676                 if (bcode == (BRK_DIVZERO << 10))
 677                         info.si_code = FPE_INTDIV;
 678                 else
 679                         info.si_code = FPE_INTOVF;
 680                 info.si_signo = SIGFPE;
 681                 info.si_errno = 0;
 682                 info.si_addr = (void __user *) regs->cp0_epc;
 683                 force_sig_info(SIGFPE, &info, current);
 684                 break;
 685         case BRK_BUG:
 686                 die("Kernel bug detected", regs);
 687                 break;
 688         default:
 689                 die_if_kernel("Break instruction in kernel code", regs);
 690                 force_sig(SIGTRAP, current);
 691         }
 692         return;
 693
 694 out_sigsegv:
 695         force_sig(SIGSEGV, current);
 696 }
 697
 698 asmlinkage void do_tr(struct pt_regs *regs)
 699 {
 700         unsigned int opcode, tcode = 0;
 701         siginfo_t info;
 702
 703         if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
 704                 goto out_sigsegv;
 705
 706         /* Immediate versions don't provide a code.  */
 707         if (!(opcode & OPCODE))
 708                 tcode = ((opcode >> 6) & ((1 << 10) - 1));
 709
 710         /*
 711          * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
 712          * insns, even for trap codes that indicate arithmetic failures.
 713          * Weird ...)
 714          * But should we continue the brokenness???  --macro
 715          */
 716         switch (tcode) {
 717         case BRK_OVERFLOW:
 718         case BRK_DIVZERO:
 719                 die_if_kernel("Trap instruction in kernel code", regs);
 720                 if (tcode == BRK_DIVZERO)
 721                         info.si_code = FPE_INTDIV;
 722                 else
 723                         info.si_code = FPE_INTOVF;
 724                 info.si_signo = SIGFPE;
 725                 info.si_errno = 0;
 726                 info.si_addr = (void __user *) regs->cp0_epc;
 727                 force_sig_info(SIGFPE, &info, current);
 728                 break;
 729         case BRK_BUG:
 730                 die("Kernel bug detected", regs);
 731                 break;
 732         default:
 733                 die_if_kernel("Trap instruction in kernel code", regs);
 734                 force_sig(SIGTRAP, current);
 735         }
 736         return;
 737
 738 out_sigsegv:
 739         force_sig(SIGSEGV, current);
 740 }
 741
 742 asmlinkage void do_ri(struct pt_regs *regs)
 743 {
 744         die_if_kernel("Reserved instruction in kernel code", regs);
 745
 746         if (!cpu_has_llsc)
 747                 if (!simulate_llsc(regs))
 748                         return;
 749
 750         if (!simulate_rdhwr(regs))
 751                 return;
 752
 753         force_sig(SIGILL, current);
 754 }
 755
 756 asmlinkage void do_cpu(struct pt_regs *regs)
 757 {
 758         unsigned int cpid;
 759
 760         die_if_kernel("do_cpu invoked from kernel context!", regs);
 761
 762         cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
 763
 764         switch (cpid) {
 765         case 0:
 766                 if (!cpu_has_llsc)
 767                         if (!simulate_llsc(regs))
 768                                 return;
 769
 770                 if (!simulate_rdhwr(regs))
 771                         return;
 772
 773                 break;
 774
 775         case 1:
 776                 if (used_math())        /* Using the FPU again.  */
 777                         own_fpu(1);
 778                 else {                  /* First time FPU user.  */
 779                         init_fpu();
 780                         set_used_math();
 781                 }
 782
 783                 if (!raw_cpu_has_fpu) {
 784                         int sig;
 785                         sig = fpu_emulator_cop1Handler(regs,
 786                                                 &current->thread.fpu, 0);
 787                         if (sig)
 788                                 force_sig(sig, current);
 789 #ifdef CONFIG_MIPS_MT_FPAFF
 790                         else {
 791                         /*
 792                          * MIPS MT processors may have fewer FPU contexts
 793                          * than CPU threads. If we've emulated more than
 794                          * some threshold number of instructions, force
 795                          * migration to a "CPU" that has FP support.
 796                          */
 797                          if(mt_fpemul_threshold > 0
 798                          && ((current->thread.emulated_fp++
 799                             > mt_fpemul_threshold))) {
 800                           /*
 801                            * If there's no FPU present, or if the
 802                            * application has already restricted
 803                            * the allowed set to exclude any CPUs
 804                            * with FPUs, we'll skip the procedure.
 805                            */
 806                           if (cpus_intersects(current->cpus_allowed,
 807                                                 mt_fpu_cpumask)) {
 808                             cpumask_t tmask;
 809
 810                             cpus_and(tmask,
 811                                         current->thread.user_cpus_allowed,
 812                                         mt_fpu_cpumask);
 813                             set_cpus_allowed(current, tmask);
 814                             current->thread.mflags |= MF_FPUBOUND;
 815                           }
 816                          }
 817                         }
 818 #endif /* CONFIG_MIPS_MT_FPAFF */
 819                 }
 820
 821                 return;
 822
 823         case 2:
 824         case 3:
 825                 break;
 826         }
 827
 828         force_sig(SIGILL, current);
 829 }
 830
 831 asmlinkage void do_mdmx(struct pt_regs *regs)
 832 {
 833         force_sig(SIGILL, current);
 834 }
 835
 836 asmlinkage void do_watch(struct pt_regs *regs)
 837 {
 838         /*
 839          * We use the watch exception where available to detect stack
 840          * overflows.
 841          */
 842         dump_tlb_all();
 843         show_regs(regs);
 844         panic("Caught WATCH exception - probably caused by stack overflow.");
 845 }
 846
 847 asmlinkage void do_mcheck(struct pt_regs *regs)
 848 {
 849         const int field = 2 * sizeof(unsigned long);
 850         int multi_match = regs->cp0_status & ST0_TS;
 851
 852         show_regs(regs);
 853
 854         if (multi_match) {
 855                 printk("Index   : %0x\n", read_c0_index());
 856                 printk("Pagemask: %0x\n", read_c0_pagemask());
 857                 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
 858                 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
 859                 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
 860                 printk("\n");
 861                 dump_tlb_all();
 862         }
 863
 864         show_code((unsigned int *) regs->cp0_epc);
 865
 866         /*
 867          * Some chips may have other causes of machine check (e.g. SB1
 868          * graduation timer)
 869          */
 870         panic("Caught Machine Check exception - %scaused by multiple "
 871               "matching entries in the TLB.",
 872               (multi_match) ? "" : "not ");
 873 }
 874
 875 asmlinkage void do_mt(struct pt_regs *regs)
 876 {
 877         int subcode;
 878
 879         subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
 880                         >> VPECONTROL_EXCPT_SHIFT;
 881         switch (subcode) {
 882         case 0:
 883                 printk(KERN_DEBUG "Thread Underflow\n");
 884                 break;
 885         case 1:
 886                 printk(KERN_DEBUG "Thread Overflow\n");
 887                 break;
 888         case 2:
 889                 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
 890                 break;
 891         case 3:
 892                 printk(KERN_DEBUG "Gating Storage Exception\n");
 893                 break;
 894         case 4:
 895                 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
 896                 break;
 897         case 5:
 898                 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
 899                 break;
 900         default:
 901                 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
 902                         subcode);
 903                 break;
 904         }
 905         die_if_kernel("MIPS MT Thread exception in kernel", regs);
 906
 907         force_sig(SIGILL, current);
 908 }
 909
 910
 911 asmlinkage void do_dsp(struct pt_regs *regs)
 912 {
 913         if (cpu_has_dsp)
 914                 panic("Unexpected DSP exception\n");
 915
 916         force_sig(SIGILL, current);
 917 }
 918
 919 asmlinkage void do_reserved(struct pt_regs *regs)
 920 {
 921         /*
 922          * Game over - no way to handle this if it ever occurs.  Most probably
 923          * caused by a new unknown cpu type or after another deadly
 924          * hard/software error.
 925          */
 926         show_regs(regs);
 927         panic("Caught reserved exception %ld - should not happen.",
 928               (regs->cp0_cause & 0x7f) >> 2);
 929 }
 930
 931 asmlinkage void do_default_vi(struct pt_regs *regs)
 932 {
 933         show_regs(regs);
 934         panic("Caught unexpected vectored interrupt.");
 935 }
 936
 937 /*
 938  * Some MIPS CPUs can enable/disable for cache parity detection, but do
 939  * it different ways.
 940  */
 941 static inline void parity_protection_init(void)
 942 {
 943         switch (current_cpu_data.cputype) {
 944         case CPU_24K:
 945         case CPU_34K:
 946         case CPU_5KC:
 947                 write_c0_ecc(0x80000000);
 948                 back_to_back_c0_hazard();
 949                 /* Set the PE bit (bit 31) in the c0_errctl register. */
 950                 printk(KERN_INFO "Cache parity protection %sabled\n",
 951                        (read_c0_ecc() & 0x80000000) ? "en" : "dis");
 952                 break;
 953         case CPU_20KC:
 954         case CPU_25KF:
 955                 /* Clear the DE bit (bit 16) in the c0_status register. */
 956                 printk(KERN_INFO "Enable cache parity protection for "
 957                        "MIPS 20KC/25KF CPUs.\n");
 958                 clear_c0_status(ST0_DE);
 959                 break;
 960         default:
 961                 break;
 962         }
 963 }
 964
 965 asmlinkage void cache_parity_error(void)
 966 {
 967         const int field = 2 * sizeof(unsigned long);
 968         unsigned int reg_val;
 969
 970         /* For the moment, report the problem and hang. */
 971         printk("Cache error exception:\n");
 972         printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
 973         reg_val = read_c0_cacheerr();
 974         printk("c0_cacheerr == %08x\n", reg_val);
 975
 976         printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
 977                reg_val & (1<<30) ? "secondary" : "primary",
 978                reg_val & (1<<31) ? "data" : "insn");
 979         printk("Error bits: %s%s%s%s%s%s%s\n",
 980                reg_val & (1<<29) ? "ED " : "",
 981                reg_val & (1<<28) ? "ET " : "",
 982                reg_val & (1<<26) ? "EE " : "",
 983                reg_val & (1<<25) ? "EB " : "",
 984                reg_val & (1<<24) ? "EI " : "",
 985                reg_val & (1<<23) ? "E1 " : "",
 986                reg_val & (1<<22) ? "E0 " : "");
 987         printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
 988
 989 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
 990         if (reg_val & (1<<22))
 991                 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
 992
 993         if (reg_val & (1<<23))
 994                 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
 995 #endif
 996
 997         panic("Can't handle the cache error!");
 998 }
 999
1000 /*
1001  * SDBBP EJTAG debug exception handler.
1002  * We skip the instruction and return to the next instruction.
1003  */
1004 void ejtag_exception_handler(struct pt_regs *regs)
1005 {
1006         const int field = 2 * sizeof(unsigned long);
1007         unsigned long depc, old_epc;
1008         unsigned int debug;
1009
1010         printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1011         depc = read_c0_depc();
1012         debug = read_c0_debug();
1013         printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1014         if (debug & 0x80000000) {
1015                 /*
1016                  * In branch delay slot.
1017                  * We cheat a little bit here and use EPC to calculate the
1018                  * debug return address (DEPC). EPC is restored after the
1019                  * calculation.
1020                  */
1021                 old_epc = regs->cp0_epc;
1022                 regs->cp0_epc = depc;
1023                 __compute_return_epc(regs);
1024                 depc = regs->cp0_epc;
1025                 regs->cp0_epc = old_epc;
1026         } else
1027                 depc += 4;
1028         write_c0_depc(depc);
1029
1030 #if 0
1031         printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1032         write_c0_debug(debug | 0x100);
1033 #endif
1034 }
1035
1036 /*
1037  * NMI exception handler.
1038  */
1039 void nmi_exception_handler(struct pt_regs *regs)
1040 {
1041 #ifdef CONFIG_MIPS_MT_SMTC
1042         unsigned long dvpret = dvpe();
1043         bust_spinlocks(1);
1044         printk("NMI taken!!!!\n");
1045         mips_mt_regdump(dvpret);
1046 #else
1047         bust_spinlocks(1);
1048         printk("NMI taken!!!!\n");
1049 #endif /* CONFIG_MIPS_MT_SMTC */
1050         die("NMI", regs);
1051         while(1) ;
1052 }
1053
1054 #define VECTORSPACING 0x100     /* for EI/VI mode */
1055
1056 unsigned long ebase;
1057 unsigned long exception_handlers[32];
1058 unsigned long vi_handlers[64];
1059
1060 /*
1061  * As a side effect of the way this is implemented we're limited
1062  * to interrupt handlers in the address range from
1063  * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
1064  */
1065 void *set_except_vector(int n, void *addr)
1066 {
1067         unsigned long handler = (unsigned long) addr;
1068         unsigned long old_handler = exception_handlers[n];
1069
1070         exception_handlers[n] = handler;
1071         if (n == 0 && cpu_has_divec) {
1072                 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1073                                                  (0x03ffffff & (handler >> 2));
1074                 flush_icache_range(ebase + 0x200, ebase + 0x204);
1075         }
1076         return (void *)old_handler;
1077 }
1078
1079 #ifdef CONFIG_CPU_MIPSR2_SRS
1080 /*
1081  * MIPSR2 shadow register set allocation
1082  * FIXME: SMP...
1083  */
1084
1085 static struct shadow_registers {
1086         /*
1087          * Number of shadow register sets supported
1088          */
1089         unsigned long sr_supported;
1090         /*
1091          * Bitmap of allocated shadow registers
1092          */
1093         unsigned long sr_allocated;
1094 } shadow_registers;
1095
1096 static void mips_srs_init(void)
1097 {
1098         shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1099         printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1100                shadow_registers.sr_supported);
1101         shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
1102 }
1103
1104 int mips_srs_max(void)
1105 {
1106         return shadow_registers.sr_supported;
1107 }
1108
1109 int mips_srs_alloc(void)
1110 {
1111         struct shadow_registers *sr = &shadow_registers;
1112         int set;
1113
1114 again:
1115         set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1116         if (set >= sr->sr_supported)
1117                 return -1;
1118
1119         if (test_and_set_bit(set, &sr->sr_allocated))
1120                 goto again;
1121
1122         return set;
1123 }
1124
1125 void mips_srs_free(int set)
1126 {
1127         struct shadow_registers *sr = &shadow_registers;
1128
1129         clear_bit(set, &sr->sr_allocated);
1130 }
1131
1132 static void *set_vi_srs_handler(int n, void *addr, int srs)
1133 {
1134         unsigned long handler;
1135         unsigned long old_handler = vi_handlers[n];
1136         u32 *w;
1137         unsigned char *b;
1138
1139         if (!cpu_has_veic && !cpu_has_vint)
1140                 BUG();
1141
1142         if (addr == NULL) {
1143                 handler = (unsigned long) do_default_vi;
1144                 srs = 0;
1145         } else
1146                 handler = (unsigned long) addr;
1147         vi_handlers[n] = (unsigned long) addr;
1148
1149         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1150
1151         if (srs >= mips_srs_max())
1152                 panic("Shadow register set %d not supported", srs);
1153
1154         if (cpu_has_veic) {
1155                 if (board_bind_eic_interrupt)
1156                         board_bind_eic_interrupt (n, srs);
1157         } else if (cpu_has_vint) {
1158                 /* SRSMap is only defined if shadow sets are implemented */
1159                 if (mips_srs_max() > 1)
1160                         change_c0_srsmap (0xf << n*4, srs << n*4);
1161         }
1162
1163         if (srs == 0) {
1164                 /*
1165                  * If no shadow set is selected then use the default handler
1166                  * that does normal register saving and a standard interrupt exit
1167                  */
1168
1169                 extern char except_vec_vi, except_vec_vi_lui;
1170                 extern char except_vec_vi_ori, except_vec_vi_end;
1171 #ifdef CONFIG_MIPS_MT_SMTC
1172                 /*
1173                  * We need to provide the SMTC vectored interrupt handler
1174                  * not only with the address of the handler, but with the
1175                  * Status.IM bit to be masked before going there.
1176                  */
1177                 extern char except_vec_vi_mori;
1178                 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1179 #endif /* CONFIG_MIPS_MT_SMTC */
1180                 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1181                 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1182                 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1183
1184                 if (handler_len > VECTORSPACING) {
1185                         /*
1186                          * Sigh... panicing won't help as the console
1187                          * is probably not configured :(
1188                          */
1189                         panic ("VECTORSPACING too small");
1190                 }
1191
1192                 memcpy (b, &except_vec_vi, handler_len);
1193 #ifdef CONFIG_MIPS_MT_SMTC
1194                 if (n > 7)
1195                         printk("Vector index %d exceeds SMTC maximum\n", n);
1196                 w = (u32 *)(b + mori_offset);
1197                 *w = (*w & 0xffff0000) | (0x100 << n);
1198 #endif /* CONFIG_MIPS_MT_SMTC */
1199                 w = (u32 *)(b + lui_offset);
1200                 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1201                 w = (u32 *)(b + ori_offset);
1202                 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1203                 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1204         }
1205         else {
1206                 /*
1207                  * In other cases jump directly to the interrupt handler
1208                  *
1209                  * It is the handlers responsibility to save registers if required
1210                  * (eg hi/lo) and return from the exception using "eret"
1211                  */
1212                 w = (u32 *)b;
1213                 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1214                 *w = 0;
1215                 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1216         }
1217
1218         return (void *)old_handler;
1219 }
1220
1221 void *set_vi_handler(int n, void *addr)
1222 {
1223         return set_vi_srs_handler(n, addr, 0);
1224 }
1225
1226 #else
1227
1228 static inline void mips_srs_init(void)
1229 {
1230 }
1231
1232 #endif /* CONFIG_CPU_MIPSR2_SRS */
1233
1234 /*
1235  * This is used by native signal handling
1236  */
1237 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1238 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1239
1240 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1241 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1242
1243 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1244 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1245
1246 #ifdef CONFIG_SMP
1247 static int smp_save_fp_context(struct sigcontext __user *sc)
1248 {
1249         return raw_cpu_has_fpu
1250                ? _save_fp_context(sc)
1251                : fpu_emulator_save_context(sc);
1252 }
1253
1254 static int smp_restore_fp_context(struct sigcontext __user *sc)
1255 {
1256         return raw_cpu_has_fpu
1257                ? _restore_fp_context(sc)
1258                : fpu_emulator_restore_context(sc);
1259 }
1260 #endif
1261
1262 static inline void signal_init(void)
1263 {
1264 #ifdef CONFIG_SMP
1265         /* For now just do the cpu_has_fpu check when the functions are invoked */
1266         save_fp_context = smp_save_fp_context;
1267         restore_fp_context = smp_restore_fp_context;
1268 #else
1269         if (cpu_has_fpu) {
1270                 save_fp_context = _save_fp_context;
1271                 restore_fp_context = _restore_fp_context;
1272         } else {
1273                 save_fp_context = fpu_emulator_save_context;
1274                 restore_fp_context = fpu_emulator_restore_context;
1275         }
1276 #endif
1277 }
1278
1279 #ifdef CONFIG_MIPS32_COMPAT
1280
1281 /*
1282  * This is used by 32-bit signal stuff on the 64-bit kernel
1283  */
1284 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1285 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1286
1287 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1288 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1289
1290 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1291 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1292
1293 static inline void signal32_init(void)
1294 {
1295         if (cpu_has_fpu) {
1296                 save_fp_context32 = _save_fp_context32;
1297                 restore_fp_context32 = _restore_fp_context32;
1298         } else {
1299                 save_fp_context32 = fpu_emulator_save_context32;
1300                 restore_fp_context32 = fpu_emulator_restore_context32;
1301         }
1302 }
1303 #endif
1304
1305 extern void cpu_cache_init(void);
1306 extern void tlb_init(void);
1307 extern void flush_tlb_handlers(void);
1308
1309 void __init per_cpu_trap_init(void)
1310 {
1311         unsigned int cpu = smp_processor_id();
1312         unsigned int status_set = ST0_CU0;
1313 #ifdef CONFIG_MIPS_MT_SMTC
1314         int secondaryTC = 0;
1315         int bootTC = (cpu == 0);
1316
1317         /*
1318          * Only do per_cpu_trap_init() for first TC of Each VPE.
1319          * Note that this hack assumes that the SMTC init code
1320          * assigns TCs consecutively and in ascending order.
1321          */
1322
1323         if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1324             ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1325                 secondaryTC = 1;
1326 #endif /* CONFIG_MIPS_MT_SMTC */
1327
1328         /*
1329          * Disable coprocessors and select 32-bit or 64-bit addressing
1330          * and the 16/32 or 32/32 FPR register model.  Reset the BEV
1331          * flag that some firmware may have left set and the TS bit (for
1332          * IP27).  Set XX for ISA IV code to work.
1333          */
1334 #ifdef CONFIG_64BIT
1335         status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1336 #endif
1337         if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1338                 status_set |= ST0_XX;
1339         change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1340                          status_set);
1341
1342         if (cpu_has_dsp)
1343                 set_c0_status(ST0_MX);
1344
1345 #ifdef CONFIG_CPU_MIPSR2
1346         write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
1347 #endif
1348
1349 #ifdef CONFIG_MIPS_MT_SMTC
1350         if (!secondaryTC) {
1351 #endif /* CONFIG_MIPS_MT_SMTC */
1352
1353         /*
1354          * Interrupt handling.
1355          */
1356         if (cpu_has_veic || cpu_has_vint) {
1357                 write_c0_ebase (ebase);
1358                 /* Setting vector spacing enables EI/VI mode  */
1359                 change_c0_intctl (0x3e0, VECTORSPACING);
1360         }
1361         if (cpu_has_divec) {
1362                 if (cpu_has_mipsmt) {
1363                         unsigned int vpflags = dvpe();
1364                         set_c0_cause(CAUSEF_IV);
1365                         evpe(vpflags);
1366                 } else
1367                         set_c0_cause(CAUSEF_IV);
1368         }
1369 #ifdef CONFIG_MIPS_MT_SMTC
1370         }
1371 #endif /* CONFIG_MIPS_MT_SMTC */
1372
1373         cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1374         TLBMISS_HANDLER_SETUP();
1375
1376         atomic_inc(&init_mm.mm_count);
1377         current->active_mm = &init_mm;
1378         BUG_ON(current->mm);
1379         enter_lazy_tlb(&init_mm, current);
1380
1381 #ifdef CONFIG_MIPS_MT_SMTC
1382         if (bootTC) {
1383 #endif /* CONFIG_MIPS_MT_SMTC */
1384                 cpu_cache_init();
1385                 tlb_init();
1386 #ifdef CONFIG_MIPS_MT_SMTC
1387         }
1388 #endif /* CONFIG_MIPS_MT_SMTC */
1389 }
1390
1391 /* Install CPU exception handler */
1392 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1393 {
1394         memcpy((void *)(ebase + offset), addr, size);
1395         flush_icache_range(ebase + offset, ebase + offset + size);
1396 }
1397
1398 /* Install uncached CPU exception handler */
1399 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1400 {
1401 #ifdef CONFIG_32BIT
1402         unsigned long uncached_ebase = KSEG1ADDR(ebase);
1403 #endif
1404 #ifdef CONFIG_64BIT
1405         unsigned long uncached_ebase = TO_UNCAC(ebase);
1406 #endif
1407
1408         memcpy((void *)(uncached_ebase + offset), addr, size);
1409 }
1410
1411 static int __initdata rdhwr_noopt;
1412 static int __init set_rdhwr_noopt(char *str)
1413 {
1414         rdhwr_noopt = 1;
1415         return 1;
1416 }
1417
1418 __setup("rdhwr_noopt", set_rdhwr_noopt);
1419
1420 void __init trap_init(void)
1421 {
1422         extern char except_vec3_generic, except_vec3_r4000;
1423         extern char except_vec4;
1424         unsigned long i;
1425
1426         if (cpu_has_veic || cpu_has_vint)
1427                 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1428         else
1429                 ebase = CAC_BASE;
1430
1431         mips_srs_init();
1432
1433         per_cpu_trap_init();
1434
1435         /*
1436          * Copy the generic exception handlers to their final destination.
1437          * This will be overriden later as suitable for a particular
1438          * configuration.
1439          */
1440         set_handler(0x180, &except_vec3_generic, 0x80);
1441
1442         /*
1443          * Setup default vectors
1444          */
1445         for (i = 0; i <= 31; i++)
1446                 set_except_vector(i, handle_reserved);
1447
1448         /*
1449          * Copy the EJTAG debug exception vector handler code to it's final
1450          * destination.
1451          */
1452         if (cpu_has_ejtag && board_ejtag_handler_setup)
1453                 board_ejtag_handler_setup ();
1454
1455         /*
1456          * Only some CPUs have the watch exceptions.
1457          */
1458         if (cpu_has_watch)
1459                 set_except_vector(23, handle_watch);
1460
1461         /*
1462          * Initialise interrupt handlers
1463          */
1464         if (cpu_has_veic || cpu_has_vint) {
1465                 int nvec = cpu_has_veic ? 64 : 8;
1466                 for (i = 0; i < nvec; i++)
1467                         set_vi_handler(i, NULL);
1468         }
1469         else if (cpu_has_divec)
1470                 set_handler(0x200, &except_vec4, 0x8);
1471
1472         /*
1473          * Some CPUs can enable/disable for cache parity detection, but does
1474          * it different ways.
1475          */
1476         parity_protection_init();
1477
1478         /*
1479          * The Data Bus Errors / Instruction Bus Errors are signaled
1480          * by external hardware.  Therefore these two exceptions
1481          * may have board specific handlers.
1482          */
1483         if (board_be_init)
1484                 board_be_init();
1485
1486         set_except_vector(0, handle_int);
1487         set_except_vector(1, handle_tlbm);
1488         set_except_vector(2, handle_tlbl);
1489         set_except_vector(3, handle_tlbs);
1490
1491         set_except_vector(4, handle_adel);
1492         set_except_vector(5, handle_ades);
1493
1494         set_except_vector(6, handle_ibe);
1495         set_except_vector(7, handle_dbe);
1496
1497         set_except_vector(8, handle_sys);
1498         set_except_vector(9, handle_bp);
1499         set_except_vector(10, rdhwr_noopt ? handle_ri :
1500                           (cpu_has_vtag_icache ?
1501                            handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1502         set_except_vector(11, handle_cpu);
1503         set_except_vector(12, handle_ov);
1504         set_except_vector(13, handle_tr);
1505
1506         if (current_cpu_data.cputype == CPU_R6000 ||
1507             current_cpu_data.cputype == CPU_R6000A) {
1508                 /*
1509                  * The R6000 is the only R-series CPU that features a machine
1510                  * check exception (similar to the R4000 cache error) and
1511                  * unaligned ldc1/sdc1 exception.  The handlers have not been
1512                  * written yet.  Well, anyway there is no R6000 machine on the
1513                  * current list of targets for Linux/MIPS.
1514                  * (Duh, crap, there is someone with a triple R6k machine)
1515                  */
1516                 //set_except_vector(14, handle_mc);
1517                 //set_except_vector(15, handle_ndc);
1518         }
1519
1520
1521         if (board_nmi_handler_setup)
1522                 board_nmi_handler_setup();
1523
1524         if (cpu_has_fpu && !cpu_has_nofpuex)
1525                 set_except_vector(15, handle_fpe);
1526
1527         set_except_vector(22, handle_mdmx);
1528
1529         if (cpu_has_mcheck)
1530                 set_except_vector(24, handle_mcheck);
1531
1532         if (cpu_has_mipsmt)
1533                 set_except_vector(25, handle_mt);
1534
1535         if (cpu_has_dsp)
1536                 set_except_vector(26, handle_dsp);
1537
1538         if (cpu_has_vce)
1539                 /* Special exception: R4[04]00 uses also the divec space. */
1540                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1541         else if (cpu_has_4kex)
1542                 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1543         else
1544                 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1545
1546         signal_init();
1547 #ifdef CONFIG_MIPS32_COMPAT
1548         signal32_init();
1549 #endif
1550
1551         flush_icache_range(ebase, ebase + 0x400);
1552         flush_tlb_handlers();
1553 }