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[linux-2.6/linux-2.6-openrd.git] / drivers / net / pcmcia / nmclan_cs.c
blob448cd40aeba5ab37c2c913db34745ac87b2857fd
1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19 References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47 -------------------------------------------------------------------------------
48 Driver Notes and Issues
49 -------------------------------------------------------------------------------
50
51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
63 4. There is a bad slow-down problem in this driver.
64
65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68 -------------------------------------------------------------------------------
69 History
70 -------------------------------------------------------------------------------
71 Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
96 95/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
100 95/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
105 95/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112 ---------------------------------------------------------------------------- */
113
114 #define DRV_NAME "nmclan_cs"
115 #define DRV_VERSION "0.16"
116
117
118 /* ----------------------------------------------------------------------------
119 Conditional Compilation Options
120 ---------------------------------------------------------------------------- */
121
122 #define MULTI_TX 0
123 #define RESET_ON_TIMEOUT 1
124 #define TX_INTERRUPTABLE 1
125 #define RESET_XILINX 0
126
127 /* ----------------------------------------------------------------------------
128 Include Files
129 ---------------------------------------------------------------------------- */
130
131 #include <linux/module.h>
132 #include <linux/kernel.h>
133 #include <linux/init.h>
134 #include <linux/ptrace.h>
135 #include <linux/slab.h>
136 #include <linux/string.h>
137 #include <linux/timer.h>
138 #include <linux/interrupt.h>
139 #include <linux/in.h>
140 #include <linux/delay.h>
141 #include <linux/ethtool.h>
142 #include <linux/netdevice.h>
143 #include <linux/etherdevice.h>
144 #include <linux/skbuff.h>
145 #include <linux/if_arp.h>
146 #include <linux/ioport.h>
147 #include <linux/bitops.h>
148
149 #include <pcmcia/cs_types.h>
150 #include <pcmcia/cs.h>
151 #include <pcmcia/cisreg.h>
152 #include <pcmcia/cistpl.h>
153 #include <pcmcia/ds.h>
154
155 #include <asm/uaccess.h>
156 #include <asm/io.h>
157 #include <asm/system.h>
158
159 /* ----------------------------------------------------------------------------
160 Defines
161 ---------------------------------------------------------------------------- */
162
163 #define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165 #define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168 /* Loop Control Defines */
169 #define MACE_MAX_IR_ITERATIONS 10
170 #define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180 /*
181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182 which manages the interface between the MACE and the PCMCIA bus. It
183 also includes buffer management for the 32K x 8 SRAM to control up to
184 four transmit and 12 receive frames at a time.
185 */
186 #define AM2150_MAX_TX_FRAMES 4
187 #define AM2150_MAX_RX_FRAMES 12
188
189 /* Am2150 Ethernet Card I/O Mapping */
190 #define AM2150_RCV 0x00
191 #define AM2150_XMT 0x04
192 #define AM2150_XMT_SKIP 0x09
193 #define AM2150_RCV_NEXT 0x0A
194 #define AM2150_RCV_FRAME_COUNT 0x0B
195 #define AM2150_MACE_BANK 0x0C
196 #define AM2150_MACE_BASE 0x10
197
198 /* MACE Registers */
199 #define MACE_RCVFIFO 0
200 #define MACE_XMTFIFO 1
201 #define MACE_XMTFC 2
202 #define MACE_XMTFS 3
203 #define MACE_XMTRC 4
204 #define MACE_RCVFC 5
205 #define MACE_RCVFS 6
206 #define MACE_FIFOFC 7
207 #define MACE_IR 8
208 #define MACE_IMR 9
209 #define MACE_PR 10
210 #define MACE_BIUCC 11
211 #define MACE_FIFOCC 12
212 #define MACE_MACCC 13
213 #define MACE_PLSCC 14
214 #define MACE_PHYCC 15
215 #define MACE_CHIPIDL 16
216 #define MACE_CHIPIDH 17
217 #define MACE_IAC 18
218 /* Reserved */
219 #define MACE_LADRF 20
220 #define MACE_PADR 21
221 /* Reserved */
222 /* Reserved */
223 #define MACE_MPC 24
224 /* Reserved */
225 #define MACE_RNTPC 26
226 #define MACE_RCVCC 27
227 /* Reserved */
228 #define MACE_UTR 29
229 #define MACE_RTR1 30
230 #define MACE_RTR2 31
231
232 /* MACE Bit Masks */
233 #define MACE_XMTRC_EXDEF 0x80
234 #define MACE_XMTRC_XMTRC 0x0F
235
236 #define MACE_XMTFS_XMTSV 0x80
237 #define MACE_XMTFS_UFLO 0x40
238 #define MACE_XMTFS_LCOL 0x20
239 #define MACE_XMTFS_MORE 0x10
240 #define MACE_XMTFS_ONE 0x08
241 #define MACE_XMTFS_DEFER 0x04
242 #define MACE_XMTFS_LCAR 0x02
243 #define MACE_XMTFS_RTRY 0x01
244
245 #define MACE_RCVFS_RCVSTS 0xF000
246 #define MACE_RCVFS_OFLO 0x8000
247 #define MACE_RCVFS_CLSN 0x4000
248 #define MACE_RCVFS_FRAM 0x2000
249 #define MACE_RCVFS_FCS 0x1000
250
251 #define MACE_FIFOFC_RCVFC 0xF0
252 #define MACE_FIFOFC_XMTFC 0x0F
253
254 #define MACE_IR_JAB 0x80
255 #define MACE_IR_BABL 0x40
256 #define MACE_IR_CERR 0x20
257 #define MACE_IR_RCVCCO 0x10
258 #define MACE_IR_RNTPCO 0x08
259 #define MACE_IR_MPCO 0x04
260 #define MACE_IR_RCVINT 0x02
261 #define MACE_IR_XMTINT 0x01
262
263 #define MACE_MACCC_PROM 0x80
264 #define MACE_MACCC_DXMT2PD 0x40
265 #define MACE_MACCC_EMBA 0x20
266 #define MACE_MACCC_RESERVED 0x10
267 #define MACE_MACCC_DRCVPA 0x08
268 #define MACE_MACCC_DRCVBC 0x04
269 #define MACE_MACCC_ENXMT 0x02
270 #define MACE_MACCC_ENRCV 0x01
271
272 #define MACE_PHYCC_LNKFL 0x80
273 #define MACE_PHYCC_DLNKTST 0x40
274 #define MACE_PHYCC_REVPOL 0x20
275 #define MACE_PHYCC_DAPC 0x10
276 #define MACE_PHYCC_LRT 0x08
277 #define MACE_PHYCC_ASEL 0x04
278 #define MACE_PHYCC_RWAKE 0x02
279 #define MACE_PHYCC_AWAKE 0x01
280
281 #define MACE_IAC_ADDRCHG 0x80
282 #define MACE_IAC_PHYADDR 0x04
283 #define MACE_IAC_LOGADDR 0x02
284
285 #define MACE_UTR_RTRE 0x80
286 #define MACE_UTR_RTRD 0x40
287 #define MACE_UTR_RPA 0x20
288 #define MACE_UTR_FCOLL 0x10
289 #define MACE_UTR_RCVFCSE 0x08
290 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
291 #define MACE_UTR_LOOP_NO_MENDEC 0x04
292 #define MACE_UTR_LOOP_EXTERNAL 0x02
293 #define MACE_UTR_LOOP_NONE 0x00
294 #define MACE_UTR_RESERVED 0x01
295
296 /* Switch MACE register bank (only 0 and 1 are valid) */
297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299 #define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310 #undef MACE_IMR_DEFAULT
311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313 #define TX_TIMEOUT ((400*HZ)/1000)
314
315 /* ----------------------------------------------------------------------------
316 Type Definitions
317 ---------------------------------------------------------------------------- */
318
319 typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362 } mace_statistics;
363
364 typedef struct _mace_private {
365 struct pcmcia_device *p_dev;
366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378 } mace_private;
379
380 /* ----------------------------------------------------------------------------
381 Private Global Variables
382 ---------------------------------------------------------------------------- */
383
384 #ifdef PCMCIA_DEBUG
385 static char rcsid[] =
386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
387 static char *version =
388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
389 #endif
390
391 static const char *if_names[]={
392 "Auto", "10baseT", "BNC",
393 };
394
395 /* ----------------------------------------------------------------------------
396 Parameters
397 These are the parameters that can be set during loading with
398 'insmod'.
399 ---------------------------------------------------------------------------- */
400
401 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
402 MODULE_LICENSE("GPL");
403
404 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
405
406 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
407 INT_MODULE_PARM(if_port, 0);
408
409 #ifdef PCMCIA_DEBUG
410 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
411 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
412 #else
413 #define DEBUG(n, args...)
414 #endif
415
416 /* ----------------------------------------------------------------------------
417 Function Prototypes
418 ---------------------------------------------------------------------------- */
419
420 static int nmclan_config(struct pcmcia_device *link);
421 static void nmclan_release(struct pcmcia_device *link);
422
423 static void nmclan_reset(struct net_device *dev);
424 static int mace_config(struct net_device *dev, struct ifmap *map);
425 static int mace_open(struct net_device *dev);
426 static int mace_close(struct net_device *dev);
427 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
428 static void mace_tx_timeout(struct net_device *dev);
429 static irqreturn_t mace_interrupt(int irq, void *dev_id);
430 static struct net_device_stats *mace_get_stats(struct net_device *dev);
431 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
432 static void restore_multicast_list(struct net_device *dev);
433 static void set_multicast_list(struct net_device *dev);
434 static const struct ethtool_ops netdev_ethtool_ops;
435
436
437 static void nmclan_detach(struct pcmcia_device *p_dev);
438
439 /* ----------------------------------------------------------------------------
440 nmclan_attach
441 Creates an "instance" of the driver, allocating local data
442 structures for one device. The device is registered with Card
443 Services.
444 ---------------------------------------------------------------------------- */
445
446 static int nmclan_probe(struct pcmcia_device *link)
447 {
448 mace_private *lp;
449 struct net_device *dev;
450
451 DEBUG(0, "nmclan_attach()\n");
452 DEBUG(1, "%s\n", rcsid);
453
454 /* Create new ethernet device */
455 dev = alloc_etherdev(sizeof(mace_private));
456 if (!dev)
457 return -ENOMEM;
458 lp = netdev_priv(dev);
459 lp->p_dev = link;
460 link->priv = dev;
461
462 spin_lock_init(&lp->bank_lock);
463 link->io.NumPorts1 = 32;
464 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
465 link->io.IOAddrLines = 5;
466 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
467 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
468 link->irq.Handler = &mace_interrupt;
469 link->irq.Instance = dev;
470 link->conf.Attributes = CONF_ENABLE_IRQ;
471 link->conf.IntType = INT_MEMORY_AND_IO;
472 link->conf.ConfigIndex = 1;
473 link->conf.Present = PRESENT_OPTION;
474
475 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
476
477 dev->hard_start_xmit = &mace_start_xmit;
478 dev->set_config = &mace_config;
479 dev->get_stats = &mace_get_stats;
480 dev->set_multicast_list = &set_multicast_list;
481 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
482 dev->open = &mace_open;
483 dev->stop = &mace_close;
484 #ifdef HAVE_TX_TIMEOUT
485 dev->tx_timeout = mace_tx_timeout;
486 dev->watchdog_timeo = TX_TIMEOUT;
487 #endif
488
489 return nmclan_config(link);
490 } /* nmclan_attach */
491
492 /* ----------------------------------------------------------------------------
493 nmclan_detach
494 This deletes a driver "instance". The device is de-registered
495 with Card Services. If it has been released, all local data
496 structures are freed. Otherwise, the structures will be freed
497 when the device is released.
498 ---------------------------------------------------------------------------- */
499
500 static void nmclan_detach(struct pcmcia_device *link)
501 {
502 struct net_device *dev = link->priv;
503
504 DEBUG(0, "nmclan_detach(0x%p)\n", link);
505
506 if (link->dev_node)
507 unregister_netdev(dev);
508
509 nmclan_release(link);
510
511 free_netdev(dev);
512 } /* nmclan_detach */
513
514 /* ----------------------------------------------------------------------------
515 mace_read
516 Reads a MACE register. This is bank independent; however, the
517 caller must ensure that this call is not interruptable. We are
518 assuming that during normal operation, the MACE is always in
519 bank 0.
520 ---------------------------------------------------------------------------- */
521 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
522 {
523 int data = 0xFF;
524 unsigned long flags;
525
526 switch (reg >> 4) {
527 case 0: /* register 0-15 */
528 data = inb(ioaddr + AM2150_MACE_BASE + reg);
529 break;
530 case 1: /* register 16-31 */
531 spin_lock_irqsave(&lp->bank_lock, flags);
532 MACEBANK(1);
533 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
534 MACEBANK(0);
535 spin_unlock_irqrestore(&lp->bank_lock, flags);
536 break;
537 }
538 return (data & 0xFF);
539 } /* mace_read */
540
541 /* ----------------------------------------------------------------------------
542 mace_write
543 Writes to a MACE register. This is bank independent; however,
544 the caller must ensure that this call is not interruptable. We
545 are assuming that during normal operation, the MACE is always in
546 bank 0.
547 ---------------------------------------------------------------------------- */
548 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
549 int data)
550 {
551 unsigned long flags;
552
553 switch (reg >> 4) {
554 case 0: /* register 0-15 */
555 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
556 break;
557 case 1: /* register 16-31 */
558 spin_lock_irqsave(&lp->bank_lock, flags);
559 MACEBANK(1);
560 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
561 MACEBANK(0);
562 spin_unlock_irqrestore(&lp->bank_lock, flags);
563 break;
564 }
565 } /* mace_write */
566
567 /* ----------------------------------------------------------------------------
568 mace_init
569 Resets the MACE chip.
570 ---------------------------------------------------------------------------- */
571 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
572 {
573 int i;
574 int ct = 0;
575
576 /* MACE Software reset */
577 mace_write(lp, ioaddr, MACE_BIUCC, 1);
578 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
579 /* Wait for reset bit to be cleared automatically after <= 200ns */;
580 if(++ct > 500)
581 {
582 printk(KERN_ERR "mace: reset failed, card removed ?\n");
583 return -1;
584 }
585 udelay(1);
586 }
587 mace_write(lp, ioaddr, MACE_BIUCC, 0);
588
589 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
590 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
591
592 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
593 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
594
595 /*
596 * Bit 2-1 PORTSEL[1-0] Port Select.
597 * 00 AUI/10Base-2
598 * 01 10Base-T
599 * 10 DAI Port (reserved in Am2150)
600 * 11 GPSI
601 * For this card, only the first two are valid.
602 * So, PLSCC should be set to
603 * 0x00 for 10Base-2
604 * 0x02 for 10Base-T
605 * Or just set ASEL in PHYCC below!
606 */
607 switch (if_port) {
608 case 1:
609 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
610 break;
611 case 2:
612 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
613 break;
614 default:
615 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
616 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
617 and the MACE device will automatically select the operating media
618 interface port. */
619 break;
620 }
621
622 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
623 /* Poll ADDRCHG bit */
624 ct = 0;
625 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
626 {
627 if(++ ct > 500)
628 {
629 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
630 return -1;
631 }
632 }
633 /* Set PADR register */
634 for (i = 0; i < ETHER_ADDR_LEN; i++)
635 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
636
637 /* MAC Configuration Control Register should be written last */
638 /* Let set_multicast_list set this. */
639 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
640 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
641 return 0;
642 } /* mace_init */
643
644 /* ----------------------------------------------------------------------------
645 nmclan_config
646 This routine is scheduled to run after a CARD_INSERTION event
647 is received, to configure the PCMCIA socket, and to make the
648 ethernet device available to the system.
649 ---------------------------------------------------------------------------- */
650
651 #define CS_CHECK(fn, ret) \
652 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
653
654 static int nmclan_config(struct pcmcia_device *link)
655 {
656 struct net_device *dev = link->priv;
657 mace_private *lp = netdev_priv(dev);
658 tuple_t tuple;
659 u_char buf[64];
660 int i, last_ret, last_fn;
661 unsigned int ioaddr;
662 DECLARE_MAC_BUF(mac);
663
664 DEBUG(0, "nmclan_config(0x%p)\n", link);
665
666 CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
667 CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
668 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
669 dev->irq = link->irq.AssignedIRQ;
670 dev->base_addr = link->io.BasePort1;
671
672 ioaddr = dev->base_addr;
673
674 /* Read the ethernet address from the CIS. */
675 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
676 tuple.TupleData = buf;
677 tuple.TupleDataMax = 64;
678 tuple.TupleOffset = 0;
679 tuple.Attributes = 0;
680 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
681 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
682 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
683
684 /* Verify configuration by reading the MACE ID. */
685 {
686 char sig[2];
687
688 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
689 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
690 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
691 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
692 sig[0], sig[1]);
693 } else {
694 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
695 " be 0x40 0x?9\n", sig[0], sig[1]);
696 return -ENODEV;
697 }
698 }
699
700 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
701 goto failed;
702
703 /* The if_port symbol can be set when the module is loaded */
704 if (if_port <= 2)
705 dev->if_port = if_port;
706 else
707 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
708
709 link->dev_node = &lp->node;
710 SET_NETDEV_DEV(dev, &handle_to_dev(link));
711
712 i = register_netdev(dev);
713 if (i != 0) {
714 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
715 link->dev_node = NULL;
716 goto failed;
717 }
718
719 strcpy(lp->node.dev_name, dev->name);
720
721 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
722 " hw_addr %s\n",
723 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
724 print_mac(mac, dev->dev_addr));
725 return 0;
726
727 cs_failed:
728 cs_error(link, last_fn, last_ret);
729 failed:
730 nmclan_release(link);
731 return -ENODEV;
732 } /* nmclan_config */
733
734 /* ----------------------------------------------------------------------------
735 nmclan_release
736 After a card is removed, nmclan_release() will unregister the
737 net device, and release the PCMCIA configuration. If the device
738 is still open, this will be postponed until it is closed.
739 ---------------------------------------------------------------------------- */
740 static void nmclan_release(struct pcmcia_device *link)
741 {
742 DEBUG(0, "nmclan_release(0x%p)\n", link);
743 pcmcia_disable_device(link);
744 }
745
746 static int nmclan_suspend(struct pcmcia_device *link)
747 {
748 struct net_device *dev = link->priv;
749
750 if (link->open)
751 netif_device_detach(dev);
752
753 return 0;
754 }
755
756 static int nmclan_resume(struct pcmcia_device *link)
757 {
758 struct net_device *dev = link->priv;
759
760 if (link->open) {
761 nmclan_reset(dev);
762 netif_device_attach(dev);
763 }
764
765 return 0;
766 }
767
768
769 /* ----------------------------------------------------------------------------
770 nmclan_reset
771 Reset and restore all of the Xilinx and MACE registers.
772 ---------------------------------------------------------------------------- */
773 static void nmclan_reset(struct net_device *dev)
774 {
775 mace_private *lp = netdev_priv(dev);
776
777 #if RESET_XILINX
778 struct pcmcia_device *link = &lp->link;
779 conf_reg_t reg;
780 u_long OrigCorValue;
781
782 /* Save original COR value */
783 reg.Function = 0;
784 reg.Action = CS_READ;
785 reg.Offset = CISREG_COR;
786 reg.Value = 0;
787 pcmcia_access_configuration_register(link, &reg);
788 OrigCorValue = reg.Value;
789
790 /* Reset Xilinx */
791 reg.Action = CS_WRITE;
792 reg.Offset = CISREG_COR;
793 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
794 OrigCorValue);
795 reg.Value = COR_SOFT_RESET;
796 pcmcia_access_configuration_register(link, &reg);
797 /* Need to wait for 20 ms for PCMCIA to finish reset. */
798
799 /* Restore original COR configuration index */
800 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
801 pcmcia_access_configuration_register(link, &reg);
802 /* Xilinx is now completely reset along with the MACE chip. */
803 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
804
805 #endif /* #if RESET_XILINX */
806
807 /* Xilinx is now completely reset along with the MACE chip. */
808 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
809
810 /* Reinitialize the MACE chip for operation. */
811 mace_init(lp, dev->base_addr, dev->dev_addr);
812 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
813
814 /* Restore the multicast list and enable TX and RX. */
815 restore_multicast_list(dev);
816 } /* nmclan_reset */
817
818 /* ----------------------------------------------------------------------------
819 mace_config
820 [Someone tell me what this is supposed to do? Is if_port a defined
821 standard? If so, there should be defines to indicate 1=10Base-T,
822 2=10Base-2, etc. including limited automatic detection.]
823 ---------------------------------------------------------------------------- */
824 static int mace_config(struct net_device *dev, struct ifmap *map)
825 {
826 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
827 if (map->port <= 2) {
828 dev->if_port = map->port;
829 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
830 if_names[dev->if_port]);
831 } else
832 return -EINVAL;
833 }
834 return 0;
835 } /* mace_config */
836
837 /* ----------------------------------------------------------------------------
838 mace_open
839 Open device driver.
840 ---------------------------------------------------------------------------- */
841 static int mace_open(struct net_device *dev)
842 {
843 unsigned int ioaddr = dev->base_addr;
844 mace_private *lp = netdev_priv(dev);
845 struct pcmcia_device *link = lp->p_dev;
846
847 if (!pcmcia_dev_present(link))
848 return -ENODEV;
849
850 link->open++;
851
852 MACEBANK(0);
853
854 netif_start_queue(dev);
855 nmclan_reset(dev);
856
857 return 0; /* Always succeed */
858 } /* mace_open */
859
860 /* ----------------------------------------------------------------------------
861 mace_close
862 Closes device driver.
863 ---------------------------------------------------------------------------- */
864 static int mace_close(struct net_device *dev)
865 {
866 unsigned int ioaddr = dev->base_addr;
867 mace_private *lp = netdev_priv(dev);
868 struct pcmcia_device *link = lp->p_dev;
869
870 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
871
872 /* Mask off all interrupts from the MACE chip. */
873 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
874
875 link->open--;
876 netif_stop_queue(dev);
877
878 return 0;
879 } /* mace_close */
880
881 static void netdev_get_drvinfo(struct net_device *dev,
882 struct ethtool_drvinfo *info)
883 {
884 strcpy(info->driver, DRV_NAME);
885 strcpy(info->version, DRV_VERSION);
886 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
887 }
888
889 #ifdef PCMCIA_DEBUG
890 static u32 netdev_get_msglevel(struct net_device *dev)
891 {
892 return pc_debug;
893 }
894
895 static void netdev_set_msglevel(struct net_device *dev, u32 level)
896 {
897 pc_debug = level;
898 }
899 #endif /* PCMCIA_DEBUG */
900
901 static const struct ethtool_ops netdev_ethtool_ops = {
902 .get_drvinfo = netdev_get_drvinfo,
903 #ifdef PCMCIA_DEBUG
904 .get_msglevel = netdev_get_msglevel,
905 .set_msglevel = netdev_set_msglevel,
906 #endif /* PCMCIA_DEBUG */
907 };
908
909 /* ----------------------------------------------------------------------------
910 mace_start_xmit
911 This routine begins the packet transmit function. When completed,
912 it will generate a transmit interrupt.
913
914 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
915 returns 0, the "packet is now solely the responsibility of the
916 driver." If _start_xmit returns non-zero, the "transmission
917 failed, put skb back into a list."
918 ---------------------------------------------------------------------------- */
919
920 static void mace_tx_timeout(struct net_device *dev)
921 {
922 mace_private *lp = netdev_priv(dev);
923 struct pcmcia_device *link = lp->p_dev;
924
925 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
926 #if RESET_ON_TIMEOUT
927 printk("resetting card\n");
928 pcmcia_reset_card(link->socket);
929 #else /* #if RESET_ON_TIMEOUT */
930 printk("NOT resetting card\n");
931 #endif /* #if RESET_ON_TIMEOUT */
932 dev->trans_start = jiffies;
933 netif_wake_queue(dev);
934 }
935
936 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
937 {
938 mace_private *lp = netdev_priv(dev);
939 unsigned int ioaddr = dev->base_addr;
940
941 netif_stop_queue(dev);
942
943 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
944 dev->name, (long)skb->len);
945
946 #if (!TX_INTERRUPTABLE)
947 /* Disable MACE TX interrupts. */
948 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
949 ioaddr + AM2150_MACE_BASE + MACE_IMR);
950 lp->tx_irq_disabled=1;
951 #endif /* #if (!TX_INTERRUPTABLE) */
952
953 {
954 /* This block must not be interrupted by another transmit request!
955 mace_tx_timeout will take care of timer-based retransmissions from
956 the upper layers. The interrupt handler is guaranteed never to
957 service a transmit interrupt while we are in here.
958 */
959
960 lp->linux_stats.tx_bytes += skb->len;
961 lp->tx_free_frames--;
962
963 /* WARNING: Write the _exact_ number of bytes written in the header! */
964 /* Put out the word header [must be an outw()] . . . */
965 outw(skb->len, ioaddr + AM2150_XMT);
966 /* . . . and the packet [may be any combination of outw() and outb()] */
967 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
968 if (skb->len & 1) {
969 /* Odd byte transfer */
970 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
971 }
972
973 dev->trans_start = jiffies;
974
975 #if MULTI_TX
976 if (lp->tx_free_frames > 0)
977 netif_start_queue(dev);
978 #endif /* #if MULTI_TX */
979 }
980
981 #if (!TX_INTERRUPTABLE)
982 /* Re-enable MACE TX interrupts. */
983 lp->tx_irq_disabled=0;
984 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
985 #endif /* #if (!TX_INTERRUPTABLE) */
986
987 dev_kfree_skb(skb);
988
989 return 0;
990 } /* mace_start_xmit */
991
992 /* ----------------------------------------------------------------------------
993 mace_interrupt
994 The interrupt handler.
995 ---------------------------------------------------------------------------- */
996 static irqreturn_t mace_interrupt(int irq, void *dev_id)
997 {
998 struct net_device *dev = (struct net_device *) dev_id;
999 mace_private *lp = netdev_priv(dev);
1000 unsigned int ioaddr;
1001 int status;
1002 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1003
1004 if (dev == NULL) {
1005 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1006 irq);
1007 return IRQ_NONE;
1008 }
1009
1010 ioaddr = dev->base_addr;
1011
1012 if (lp->tx_irq_disabled) {
1013 printk(
1014 (lp->tx_irq_disabled?
1015 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1016 "[isr=%02X, imr=%02X]\n":
1017 KERN_NOTICE "%s: Re-entering the interrupt handler "
1018 "[isr=%02X, imr=%02X]\n"),
1019 dev->name,
1020 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1021 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1022 );
1023 /* WARNING: MACE_IR has been read! */
1024 return IRQ_NONE;
1025 }
1026
1027 if (!netif_device_present(dev)) {
1028 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1029 return IRQ_NONE;
1030 }
1031
1032 do {
1033 /* WARNING: MACE_IR is a READ/CLEAR port! */
1034 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1035
1036 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1037
1038 if (status & MACE_IR_RCVINT) {
1039 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1040 }
1041
1042 if (status & MACE_IR_XMTINT) {
1043 unsigned char fifofc;
1044 unsigned char xmtrc;
1045 unsigned char xmtfs;
1046
1047 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1048 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1049 lp->linux_stats.tx_errors++;
1050 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1051 }
1052
1053 /* Transmit Retry Count (XMTRC, reg 4) */
1054 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1055 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1056 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1057
1058 if (
1059 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1060 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1061 ) {
1062 lp->mace_stats.xmtsv++;
1063
1064 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1065 if (xmtfs & MACE_XMTFS_UFLO) {
1066 /* Underflow. Indicates that the Transmit FIFO emptied before
1067 the end of frame was reached. */
1068 lp->mace_stats.uflo++;
1069 }
1070 if (xmtfs & MACE_XMTFS_LCOL) {
1071 /* Late Collision */
1072 lp->mace_stats.lcol++;
1073 }
1074 if (xmtfs & MACE_XMTFS_MORE) {
1075 /* MORE than one retry was needed */
1076 lp->mace_stats.more++;
1077 }
1078 if (xmtfs & MACE_XMTFS_ONE) {
1079 /* Exactly ONE retry occurred */
1080 lp->mace_stats.one++;
1081 }
1082 if (xmtfs & MACE_XMTFS_DEFER) {
1083 /* Transmission was defered */
1084 lp->mace_stats.defer++;
1085 }
1086 if (xmtfs & MACE_XMTFS_LCAR) {
1087 /* Loss of carrier */
1088 lp->mace_stats.lcar++;
1089 }
1090 if (xmtfs & MACE_XMTFS_RTRY) {
1091 /* Retry error: transmit aborted after 16 attempts */
1092 lp->mace_stats.rtry++;
1093 }
1094 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1095
1096 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1097
1098 lp->linux_stats.tx_packets++;
1099 lp->tx_free_frames++;
1100 netif_wake_queue(dev);
1101 } /* if (status & MACE_IR_XMTINT) */
1102
1103 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1104 if (status & MACE_IR_JAB) {
1105 /* Jabber Error. Excessive transmit duration (20-150ms). */
1106 lp->mace_stats.jab++;
1107 }
1108 if (status & MACE_IR_BABL) {
1109 /* Babble Error. >1518 bytes transmitted. */
1110 lp->mace_stats.babl++;
1111 }
1112 if (status & MACE_IR_CERR) {
1113 /* Collision Error. CERR indicates the absence of the
1114 Signal Quality Error Test message after a packet
1115 transmission. */
1116 lp->mace_stats.cerr++;
1117 }
1118 if (status & MACE_IR_RCVCCO) {
1119 /* Receive Collision Count Overflow; */
1120 lp->mace_stats.rcvcco++;
1121 }
1122 if (status & MACE_IR_RNTPCO) {
1123 /* Runt Packet Count Overflow */
1124 lp->mace_stats.rntpco++;
1125 }
1126 if (status & MACE_IR_MPCO) {
1127 /* Missed Packet Count Overflow */
1128 lp->mace_stats.mpco++;
1129 }
1130 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1131
1132 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1133
1134 return IRQ_HANDLED;
1135 } /* mace_interrupt */
1136
1137 /* ----------------------------------------------------------------------------
1138 mace_rx
1139 Receives packets.
1140 ---------------------------------------------------------------------------- */
1141 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1142 {
1143 mace_private *lp = netdev_priv(dev);
1144 unsigned int ioaddr = dev->base_addr;
1145 unsigned char rx_framecnt;
1146 unsigned short rx_status;
1147
1148 while (
1149 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1150 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1151 (RxCnt--)
1152 ) {
1153 rx_status = inw(ioaddr + AM2150_RCV);
1154
1155 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1156 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1157
1158 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1159 lp->linux_stats.rx_errors++;
1160 if (rx_status & MACE_RCVFS_OFLO) {
1161 lp->mace_stats.oflo++;
1162 }
1163 if (rx_status & MACE_RCVFS_CLSN) {
1164 lp->mace_stats.clsn++;
1165 }
1166 if (rx_status & MACE_RCVFS_FRAM) {
1167 lp->mace_stats.fram++;
1168 }
1169 if (rx_status & MACE_RCVFS_FCS) {
1170 lp->mace_stats.fcs++;
1171 }
1172 } else {
1173 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1174 /* Auto Strip is off, always subtract 4 */
1175 struct sk_buff *skb;
1176
1177 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1178 /* runt packet count */
1179 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1180 /* rcv collision count */
1181
1182 DEBUG(3, " receiving packet size 0x%X rx_status"
1183 " 0x%X.\n", pkt_len, rx_status);
1184
1185 skb = dev_alloc_skb(pkt_len+2);
1186
1187 if (skb != NULL) {
1188 skb_reserve(skb, 2);
1189 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1190 if (pkt_len & 1)
1191 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1192 skb->protocol = eth_type_trans(skb, dev);
1193
1194 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1195
1196 dev->last_rx = jiffies;
1197 lp->linux_stats.rx_packets++;
1198 lp->linux_stats.rx_bytes += pkt_len;
1199 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1200 continue;
1201 } else {
1202 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1203 " %d.\n", dev->name, pkt_len);
1204 lp->linux_stats.rx_dropped++;
1205 }
1206 }
1207 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1208 } /* while */
1209
1210 return 0;
1211 } /* mace_rx */
1212
1213 /* ----------------------------------------------------------------------------
1214 pr_linux_stats
1215 ---------------------------------------------------------------------------- */
1216 static void pr_linux_stats(struct net_device_stats *pstats)
1217 {
1218 DEBUG(2, "pr_linux_stats\n");
1219 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1220 (long)pstats->rx_packets, (long)pstats->tx_packets);
1221 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1222 (long)pstats->rx_errors, (long)pstats->tx_errors);
1223 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1224 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1225 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1226 (long)pstats->multicast, (long)pstats->collisions);
1227
1228 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1229 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1230 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1231 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1232 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1233 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1234
1235 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1236 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1237 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1238 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1239 DEBUG(2, " tx_window_errors=%ld\n",
1240 (long)pstats->tx_window_errors);
1241 } /* pr_linux_stats */
1242
1243 /* ----------------------------------------------------------------------------
1244 pr_mace_stats
1245 ---------------------------------------------------------------------------- */
1246 static void pr_mace_stats(mace_statistics *pstats)
1247 {
1248 DEBUG(2, "pr_mace_stats\n");
1249
1250 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1251 pstats->xmtsv, pstats->uflo);
1252 DEBUG(2, " lcol=%-7d more=%d\n",
1253 pstats->lcol, pstats->more);
1254 DEBUG(2, " one=%-7d defer=%d\n",
1255 pstats->one, pstats->defer);
1256 DEBUG(2, " lcar=%-7d rtry=%d\n",
1257 pstats->lcar, pstats->rtry);
1258
1259 /* MACE_XMTRC */
1260 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1261 pstats->exdef, pstats->xmtrc);
1262
1263 /* RFS1--Receive Status (RCVSTS) */
1264 DEBUG(2, " oflo=%-7d clsn=%d\n",
1265 pstats->oflo, pstats->clsn);
1266 DEBUG(2, " fram=%-7d fcs=%d\n",
1267 pstats->fram, pstats->fcs);
1268
1269 /* RFS2--Runt Packet Count (RNTPC) */
1270 /* RFS3--Receive Collision Count (RCVCC) */
1271 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1272 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1273
1274 /* MACE_IR */
1275 DEBUG(2, " jab=%-7d babl=%d\n",
1276 pstats->jab, pstats->babl);
1277 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1278 pstats->cerr, pstats->rcvcco);
1279 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1280 pstats->rntpco, pstats->mpco);
1281
1282 /* MACE_MPC */
1283 DEBUG(2, " mpc=%d\n", pstats->mpc);
1284
1285 /* MACE_RNTPC */
1286 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1287
1288 /* MACE_RCVCC */
1289 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1290
1291 } /* pr_mace_stats */
1292
1293 /* ----------------------------------------------------------------------------
1294 update_stats
1295 Update statistics. We change to register window 1, so this
1296 should be run single-threaded if the device is active. This is
1297 expected to be a rare operation, and it's simpler for the rest
1298 of the driver to assume that window 0 is always valid rather
1299 than use a special window-state variable.
1300
1301 oflo & uflo should _never_ occur since it would mean the Xilinx
1302 was not able to transfer data between the MACE FIFO and the
1303 card's SRAM fast enough. If this happens, something is
1304 seriously wrong with the hardware.
1305 ---------------------------------------------------------------------------- */
1306 static void update_stats(unsigned int ioaddr, struct net_device *dev)
1307 {
1308 mace_private *lp = netdev_priv(dev);
1309
1310 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1311 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1312 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1313 /* At this point, mace_stats is fully updated for this call.
1314 We may now update the linux_stats. */
1315
1316 /* The MACE has no equivalent for linux_stats field which are commented
1317 out. */
1318
1319 /* lp->linux_stats.multicast; */
1320 lp->linux_stats.collisions =
1321 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1322 /* Collision: The MACE may retry sending a packet 15 times
1323 before giving up. The retry count is in XMTRC.
1324 Does each retry constitute a collision?
1325 If so, why doesn't the RCVCC record these collisions? */
1326
1327 /* detailed rx_errors: */
1328 lp->linux_stats.rx_length_errors =
1329 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1330 /* lp->linux_stats.rx_over_errors */
1331 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1332 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1333 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1334 lp->linux_stats.rx_missed_errors =
1335 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1336
1337 /* detailed tx_errors */
1338 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1339 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1340 /* LCAR usually results from bad cabling. */
1341 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1342 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1343 /* lp->linux_stats.tx_window_errors; */
1344
1345 return;
1346 } /* update_stats */
1347
1348 /* ----------------------------------------------------------------------------
1349 mace_get_stats
1350 Gathers ethernet statistics from the MACE chip.
1351 ---------------------------------------------------------------------------- */
1352 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1353 {
1354 mace_private *lp = netdev_priv(dev);
1355
1356 update_stats(dev->base_addr, dev);
1357
1358 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1359 pr_linux_stats(&lp->linux_stats);
1360 pr_mace_stats(&lp->mace_stats);
1361
1362 return &lp->linux_stats;
1363 } /* net_device_stats */
1364
1365 /* ----------------------------------------------------------------------------
1366 updateCRC
1367 Modified from Am79C90 data sheet.
1368 ---------------------------------------------------------------------------- */
1369
1370 #ifdef BROKEN_MULTICAST
1371
1372 static void updateCRC(int *CRC, int bit)
1373 {
1374 int poly[]={
1375 1,1,1,0, 1,1,0,1,
1376 1,0,1,1, 1,0,0,0,
1377 1,0,0,0, 0,0,1,1,
1378 0,0,1,0, 0,0,0,0
1379 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1380 CRC generator polynomial. */
1381
1382 int j;
1383
1384 /* shift CRC and control bit (CRC[32]) */
1385 for (j = 32; j > 0; j--)
1386 CRC[j] = CRC[j-1];
1387 CRC[0] = 0;
1388
1389 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1390 if (bit ^ CRC[32])
1391 for (j = 0; j < 32; j++)
1392 CRC[j] ^= poly[j];
1393 } /* updateCRC */
1394
1395 /* ----------------------------------------------------------------------------
1396 BuildLAF
1397 Build logical address filter.
1398 Modified from Am79C90 data sheet.
1399
1400 Input
1401 ladrf: logical address filter (contents initialized to 0)
1402 adr: ethernet address
1403 ---------------------------------------------------------------------------- */
1404 static void BuildLAF(int *ladrf, int *adr)
1405 {
1406 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1407
1408 int i, byte; /* temporary array indices */
1409 int hashcode; /* the output object */
1410
1411 CRC[32]=0;
1412
1413 for (byte = 0; byte < 6; byte++)
1414 for (i = 0; i < 8; i++)
1415 updateCRC(CRC, (adr[byte] >> i) & 1);
1416
1417 hashcode = 0;
1418 for (i = 0; i < 6; i++)
1419 hashcode = (hashcode << 1) + CRC[i];
1420
1421 byte = hashcode >> 3;
1422 ladrf[byte] |= (1 << (hashcode & 7));
1423
1424 #ifdef PCMCIA_DEBUG
1425 if (pc_debug > 2) {
1426 printk(KERN_DEBUG " adr =");
1427 for (i = 0; i < 6; i++)
1428 printk(" %02X", adr[i]);
1429 printk("\n" KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63]"
1430 " =", hashcode);
1431 for (i = 0; i < 8; i++)
1432 printk(" %02X", ladrf[i]);
1433 printk("\n");
1434 }
1435 #endif
1436 } /* BuildLAF */
1437
1438 /* ----------------------------------------------------------------------------
1439 restore_multicast_list
1440 Restores the multicast filter for MACE chip to the last
1441 set_multicast_list() call.
1442
1443 Input
1444 multicast_num_addrs
1445 multicast_ladrf[]
1446 ---------------------------------------------------------------------------- */
1447 static void restore_multicast_list(struct net_device *dev)
1448 {
1449 mace_private *lp = netdev_priv(dev);
1450 int num_addrs = lp->multicast_num_addrs;
1451 int *ladrf = lp->multicast_ladrf;
1452 unsigned int ioaddr = dev->base_addr;
1453 int i;
1454
1455 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1456 dev->name, num_addrs);
1457
1458 if (num_addrs > 0) {
1459
1460 DEBUG(1, "Attempt to restore multicast list detected.\n");
1461
1462 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1463 /* Poll ADDRCHG bit */
1464 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1465 ;
1466 /* Set LADRF register */
1467 for (i = 0; i < MACE_LADRF_LEN; i++)
1468 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1469
1470 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1471 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1472
1473 } else if (num_addrs < 0) {
1474
1475 /* Promiscuous mode: receive all packets */
1476 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1477 mace_write(lp, ioaddr, MACE_MACCC,
1478 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1479 );
1480
1481 } else {
1482
1483 /* Normal mode */
1484 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1485 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1486
1487 }
1488 } /* restore_multicast_list */
1489
1490 /* ----------------------------------------------------------------------------
1491 set_multicast_list
1492 Set or clear the multicast filter for this adaptor.
1493
1494 Input
1495 num_addrs == -1 Promiscuous mode, receive all packets
1496 num_addrs == 0 Normal mode, clear multicast list
1497 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1498 best-effort filtering.
1499 Output
1500 multicast_num_addrs
1501 multicast_ladrf[]
1502 ---------------------------------------------------------------------------- */
1503
1504 static void set_multicast_list(struct net_device *dev)
1505 {
1506 mace_private *lp = netdev_priv(dev);
1507 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1508 int i;
1509 struct dev_mc_list *dmi = dev->mc_list;
1510
1511 #ifdef PCMCIA_DEBUG
1512 if (pc_debug > 1) {
1513 static int old;
1514 if (dev->mc_count != old) {
1515 old = dev->mc_count;
1516 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1517 dev->name, old);
1518 }
1519 }
1520 #endif
1521
1522 /* Set multicast_num_addrs. */
1523 lp->multicast_num_addrs = dev->mc_count;
1524
1525 /* Set multicast_ladrf. */
1526 if (num_addrs > 0) {
1527 /* Calculate multicast logical address filter */
1528 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1529 for (i = 0; i < dev->mc_count; i++) {
1530 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1531 dmi = dmi->next;
1532 BuildLAF(lp->multicast_ladrf, adr);
1533 }
1534 }
1535
1536 restore_multicast_list(dev);
1537
1538 } /* set_multicast_list */
1539
1540 #endif /* BROKEN_MULTICAST */
1541
1542 static void restore_multicast_list(struct net_device *dev)
1543 {
1544 unsigned int ioaddr = dev->base_addr;
1545 mace_private *lp = netdev_priv(dev);
1546
1547 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1548 lp->multicast_num_addrs);
1549
1550 if (dev->flags & IFF_PROMISC) {
1551 /* Promiscuous mode: receive all packets */
1552 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1553 mace_write(lp, ioaddr, MACE_MACCC,
1554 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1555 );
1556 } else {
1557 /* Normal mode */
1558 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1559 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1560 }
1561 } /* restore_multicast_list */
1562
1563 static void set_multicast_list(struct net_device *dev)
1564 {
1565 mace_private *lp = netdev_priv(dev);
1566
1567 #ifdef PCMCIA_DEBUG
1568 if (pc_debug > 1) {
1569 static int old;
1570 if (dev->mc_count != old) {
1571 old = dev->mc_count;
1572 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1573 dev->name, old);
1574 }
1575 }
1576 #endif
1577
1578 lp->multicast_num_addrs = dev->mc_count;
1579 restore_multicast_list(dev);
1580
1581 } /* set_multicast_list */
1582
1583 static struct pcmcia_device_id nmclan_ids[] = {
1584 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1585 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1586 PCMCIA_DEVICE_NULL,
1587 };
1588 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1589
1590 static struct pcmcia_driver nmclan_cs_driver = {
1591 .owner = THIS_MODULE,
1592 .drv = {
1593 .name = "nmclan_cs",
1594 },
1595 .probe = nmclan_probe,
1596 .remove = nmclan_detach,
1597 .id_table = nmclan_ids,
1598 .suspend = nmclan_suspend,
1599 .resume = nmclan_resume,
1600 };
1601
1602 static int __init init_nmclan_cs(void)
1603 {
1604 return pcmcia_register_driver(&nmclan_cs_driver);
1605 }
1606
1607 static void __exit exit_nmclan_cs(void)
1608 {
1609 pcmcia_unregister_driver(&nmclan_cs_driver);
1610 }
1611
1612 module_init(init_nmclan_cs);
1613 module_exit(exit_nmclan_cs);
linux 2.6 git repository for openrd