2 * Copyright (C) 2004-2006 Atmel Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 * This file contains the low-level entry-points into the kernel, that is,
11 * exception handlers, debug trap handlers, interrupt handlers and the
12 * system call handler.
14 #include <linux/errno.h>
17 #include <asm/hardirq.h>
21 #include <asm/pgtable.h>
22 #include <asm/ptrace.h>
23 #include <asm/sysreg.h>
24 #include <asm/thread_info.h>
25 #include <asm/unistd.h>
28 # define preempt_stop mask_interrupts
31 # define fault_resume_kernel fault_restore_all
34 #define __MASK(x) ((1 << (x)) - 1)
35 #define IRQ_MASK ((__MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) | \
36 (__MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT))
38 .section .ex.text,"ax",@progbits
45 bral do_bus_error_write
47 bral do_bus_error_read
51 bral handle_address_fault
53 bral handle_protection_fault
57 bral do_illegal_opcode_ll
59 bral do_illegal_opcode_ll
61 bral do_illegal_opcode_ll
65 bral do_illegal_opcode_ll
67 bral handle_address_fault
69 bral handle_address_fault
71 bral handle_protection_fault
73 bral handle_protection_fault
77 #define tlbmiss_save pushm r0-r3
78 #define tlbmiss_restore popm r0-r3
95 .global tlb_miss_common
98 mfsr r0, SYSREG_TLBEAR
102 * First level lookup: The PGD contains virtual pointers to
103 * the second-level page tables, but they may be NULL if not
107 lsr r2, r0, PGDIR_SHIFT
109 bfextu r1, r0, PAGE_SHIFT, PGDIR_SHIFT - PAGE_SHIFT
111 breq page_table_not_present
113 /* Second level lookup */
115 mfsr r0, SYSREG_TLBARLO
116 bld r2, _PAGE_BIT_PRESENT
117 brcc page_not_present
119 /* Mark the page as accessed */
120 sbr r2, _PAGE_BIT_ACCESSED
123 /* Drop software flags */
124 andl r2, _PAGE_FLAGS_HARDWARE_MASK & 0xffff
125 mtsr SYSREG_TLBELO, r2
127 /* Figure out which entry we want to replace */
128 mfsr r1, SYSREG_MMUCR
131 mov r3, -1 /* All entries have been accessed, */
132 mov r2, 0 /* so start at 0 */
133 mtsr SYSREG_TLBARLO, r3 /* and reset TLBAR */
135 1: bfins r1, r2, SYSREG_DRP_OFFSET, SYSREG_DRP_SIZE
136 mtsr SYSREG_MMUCR, r1
142 /* The slow path of the TLB miss handler */
144 page_table_not_present:
145 /* Do we need to synchronize with swapper_pg_dir? */
147 brcs sync_with_swapper_pg_dir
153 rcall save_full_context_ex
157 rjmp ret_from_exception
160 sync_with_swapper_pg_dir:
162 * If swapper_pg_dir contains a non-NULL second-level page
163 * table pointer, copy it into the current PGD. If not, we
164 * must handle it as a full-blown page fault.
166 * Jumping back to pgtbl_lookup causes an unnecessary lookup,
167 * but it is guaranteed to be a cache hit, it won't happen
168 * very often, and we absolutely do not want to sacrifice any
169 * performance in the fast path in order to improve this.
171 mov r1, lo(swapper_pg_dir)
172 orh r1, hi(swapper_pg_dir)
175 breq page_not_present
181 * We currently have two bytes left at this point until we
182 * crash into the system call handler...
184 * Don't worry, the assembler will let us know.
188 /* --- System Call --- */
192 #ifdef CONFIG_PREEMPT
195 pushm r12 /* r12_orig */
198 mfsr r0, SYSREG_RAR_SUP
199 mfsr r1, SYSREG_RSR_SUP
200 #ifdef CONFIG_PREEMPT
206 /* check for syscall tracing */
208 ld.w r1, r0[TI_flags]
209 bld r1, TIF_SYSCALL_TRACE
210 brcs syscall_trace_enter
216 lddpc lr, syscall_table_addr
218 mov r8, r5 /* 5th argument (6th is pushed by stub) */
221 .global syscall_return
224 mask_interrupts /* make sure we don't miss an interrupt
225 setting need_resched or sigpending
226 between sampling and the rets */
228 /* Store the return value so that the correct value is loaded below */
229 stdsp sp[REG_R12], r12
231 ld.w r1, r0[TI_flags]
232 andl r1, _TIF_ALLWORK_MASK, COH
233 brne syscall_exit_work
237 mtsr SYSREG_RAR_SUP, r8
238 mtsr SYSREG_RSR_SUP, r9
240 sub sp, -4 /* r12_orig */
251 .global ret_from_fork
255 /* check for syscall tracing */
257 ld.w r1, r0[TI_flags]
258 andl r1, _TIF_ALLWORK_MASK, COH
259 brne syscall_exit_work
260 rjmp syscall_exit_cont
266 rjmp syscall_trace_cont
269 bld r1, TIF_SYSCALL_TRACE
274 ld.w r1, r0[TI_flags]
276 1: bld r1, TIF_NEED_RESCHED
281 ld.w r1, r0[TI_flags]
284 2: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
290 rcall do_notify_resume
292 ld.w r1, r0[TI_flags]
295 3: bld r1, TIF_BREAKPOINT
296 brcc syscall_exit_cont
297 rjmp enter_monitor_mode
299 /* This function expects to find offending PC in SYSREG_RAR_EX */
300 .type save_full_context_ex, @function
302 save_full_context_ex:
303 mfsr r11, SYSREG_RAR_EX
304 sub r9, pc, . - debug_trampoline
305 mfsr r8, SYSREG_RSR_EX
309 andh r8, (MODE_MASK >> 16), COH
312 1: pushm r11, r12 /* PC and SR */
316 2: sub r10, sp, -(FRAME_SIZE_FULL - REG_LR)
317 stdsp sp[4], r10 /* replace saved SP */
321 * The debug handler set up a trampoline to make us
322 * automatically enter monitor mode upon return, but since
323 * we're saving the full context, we must assume that the
324 * exception handler might want to alter the return address
325 * and/or status register. So we need to restore the original
326 * context and enter monitor mode manually after the exception
329 3: get_thread_info r8
330 ld.w r11, r8[TI_rar_saved]
331 ld.w r12, r8[TI_rsr_saved]
333 .size save_full_context_ex, . - save_full_context_ex
335 /* Low-level exception handlers */
339 rcall save_full_context_ex
342 rcall do_critical_exception
344 /* We should never get here... */
346 sub r12, pc, (. - 1f)
349 1: .asciz "Return from critical exception!"
355 rcall save_full_context_ex
362 rcall save_full_context_ex
364 1: mfsr r12, SYSREG_BEAR
367 rjmp ret_from_exception
373 mfsr r9, SYSREG_RSR_NMI
374 mfsr r8, SYSREG_RAR_NMI
375 bfextu r0, r9, MODE_SHIFT, 3
378 1: pushm r8, r9 /* PC and SR */
383 mtsr SYSREG_RAR_NMI, r8
385 mtsr SYSREG_RSR_NMI, r9
389 sub sp, -4 /* skip r12_orig */
392 2: sub r10, sp, -(FRAME_SIZE_FULL - REG_LR)
393 stdsp sp[4], r10 /* replace saved SP */
397 sub sp, -4 /* skip sp */
399 sub sp, -4 /* skip r12_orig */
402 handle_address_fault:
405 rcall save_full_context_ex
408 rcall do_address_exception
409 rjmp ret_from_exception
411 handle_protection_fault:
414 rcall save_full_context_ex
418 rjmp ret_from_exception
421 do_illegal_opcode_ll:
424 rcall save_full_context_ex
427 rcall do_illegal_opcode
428 rjmp ret_from_exception
432 mfsr r1, SYSREG_TLBEAR
434 lsr r2, r1, PGDIR_SHIFT
436 lsl r1, (32 - PGDIR_SHIFT)
437 lsr r1, (32 - PGDIR_SHIFT) + PAGE_SHIFT
439 /* Translate to virtual address in P1 */
444 sbr r3, _PAGE_BIT_DIRTY
448 /* The page table is up-to-date. Update the TLB entry as well */
449 andl r0, lo(_PAGE_FLAGS_HARDWARE_MASK)
450 mtsr SYSREG_TLBELO, r0
452 /* MMUCR[DRP] is updated automatically, so let's go... */
461 rcall save_full_context_ex
466 rjmp ret_from_exception
472 andh r4, (MODE_MASK >> 16), COH
473 brne fault_resume_kernel
476 ld.w r1, r0[TI_flags]
477 andl r1, _TIF_WORK_MASK, COH
483 mtsr SYSREG_RAR_EX, r8
484 mtsr SYSREG_RSR_EX, r9
490 #ifdef CONFIG_PREEMPT
492 ld.w r2, r0[TI_preempt_count]
495 ld.w r1, r0[TI_flags]
496 bld r1, TIF_NEED_RESCHED
499 bld r4, SYSREG_GM_OFFSET
501 rcall preempt_schedule_irq
508 mtsr SYSREG_RAR_EX, r8
509 mtsr SYSREG_RSR_EX, r9
511 sub sp, -4 /* ignore SP */
513 sub sp, -4 /* ignore r12_orig */
517 /* Switch to exception mode so that we can share the same code. */
519 cbr r8, SYSREG_M0_OFFSET
520 orh r8, hi(SYSREG_BIT(M1) | SYSREG_BIT(M2))
524 ld.w r1, r0[TI_flags]
527 bld r1, TIF_NEED_RESCHED
532 ld.w r1, r0[TI_flags]
535 1: mov r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
541 rcall do_notify_resume
543 ld.w r1, r0[TI_flags]
546 2: bld r1, TIF_BREAKPOINT
547 brcc fault_resume_user
548 rjmp enter_monitor_mode
550 .section .kprobes.text, "ax", @progbits
551 .type handle_debug, @function
553 sub sp, 4 /* r12_orig */
555 mfsr r8, SYSREG_RAR_DBG
556 mfsr r9, SYSREG_RSR_DBG
559 bfextu r9, r9, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
560 brne debug_fixup_regs
563 #ifdef CONFIG_TRACE_IRQFLAGS
564 rcall trace_hardirqs_off
571 bfextu r3, r2, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
572 brne debug_resume_kernel
575 ld.w r1, r0[TI_flags]
576 mov r2, _TIF_DBGWORK_MASK
580 bld r1, TIF_SINGLE_STEP
583 sbr r4, OCD_DC_SS_BIT
588 mtsr SYSREG_RSR_DBG, r11
589 mtsr SYSREG_RAR_DBG, r10
590 #ifdef CONFIG_TRACE_IRQFLAGS
591 rcall trace_hardirqs_on
597 .size handle_debug, . - handle_debug
599 /* Mode of the trapped context is in r9 */
600 .type debug_fixup_regs, @function
604 bfins r8, r9, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
610 sub r8, sp, -FRAME_SIZE_FULL
612 rjmp .Ldebug_fixup_cont
613 .size debug_fixup_regs, . - debug_fixup_regs
615 .type debug_resume_kernel, @function
619 mtsr SYSREG_RAR_DBG, r10
620 mtsr SYSREG_RSR_DBG, r11
621 #ifdef CONFIG_TRACE_IRQFLAGS
622 bld r11, SYSREG_GM_OFFSET
624 rcall trace_hardirqs_on
629 bfins r2, r3, SYSREG_MODE_OFFSET, SYSREG_MODE_SIZE
635 sub sp, -4 /* skip SP */
639 .size debug_resume_kernel, . - debug_resume_kernel
641 .type debug_exit_work, @function
644 * We must return from Monitor Mode using a retd, and we must
645 * not schedule since that involves the D bit in SR getting
646 * cleared by something other than the debug hardware. This
647 * may cause undefined behaviour according to the Architecture
650 * So we fix up the return address and status and return to a
651 * stub below in Exception mode. From there, we can follow the
652 * normal exception return path.
654 * The real return address and status registers are stored on
655 * the stack in the way the exception return path understands,
656 * so no need to fix anything up there.
658 sub r8, pc, . - fault_exit_work
659 mtsr SYSREG_RAR_DBG, r8
661 orh r9, hi(SR_EM | SR_GM | MODE_EXCEPTION)
662 mtsr SYSREG_RSR_DBG, r9
665 .size debug_exit_work, . - debug_exit_work
667 .set rsr_int0, SYSREG_RSR_INT0
668 .set rsr_int1, SYSREG_RSR_INT1
669 .set rsr_int2, SYSREG_RSR_INT2
670 .set rsr_int3, SYSREG_RSR_INT3
671 .set rar_int0, SYSREG_RAR_INT0
672 .set rar_int1, SYSREG_RAR_INT1
673 .set rar_int2, SYSREG_RAR_INT2
674 .set rar_int3, SYSREG_RAR_INT3
676 .macro IRQ_LEVEL level
677 .type irq_level\level, @function
679 sub sp, 4 /* r12_orig */
681 mfsr r8, rar_int\level
682 mfsr r9, rsr_int\level
684 #ifdef CONFIG_PREEMPT
685 sub r11, pc, (. - system_call)
698 bfextu r4, r4, SYSREG_M0_OFFSET, 3
699 cp.w r4, MODE_SUPERVISOR >> SYSREG_M0_OFFSET
701 cp.w r4, MODE_USER >> SYSREG_M0_OFFSET
702 #ifdef CONFIG_PREEMPT
709 ld.w r1, r0[TI_flags]
710 andl r1, _TIF_WORK_MASK, COH
714 #ifdef CONFIG_TRACE_IRQFLAGS
715 rcall trace_hardirqs_on
718 mtsr rar_int\level, r8
719 mtsr rsr_int\level, r9
721 sub sp, -4 /* ignore r12_orig */
724 #ifdef CONFIG_PREEMPT
726 mfsr r8, rsr_int\level
728 mtsr rsr_int\level, r8
730 sub sp, -4 /* ignore r12_orig */
734 2: get_thread_info r0
735 ld.w r1, r0[TI_flags]
736 bld r1, TIF_CPU_GOING_TO_SLEEP
737 #ifdef CONFIG_PREEMPT
742 sub r1, pc, . - cpu_idle_skip_sleep
744 #ifdef CONFIG_PREEMPT
745 3: get_thread_info r0
746 ld.w r2, r0[TI_preempt_count]
749 ld.w r1, r0[TI_flags]
750 bld r1, TIF_NEED_RESCHED
753 bld r4, SYSREG_GM_OFFSET
755 rcall preempt_schedule_irq
760 .section .irq.text,"ax",@progbits
771 .section .kprobes.text, "ax", @progbits
772 .type enter_monitor_mode, @function
775 * We need to enter monitor mode to do a single step. The
776 * monitor code will alter the return address so that we
777 * return directly to the user instead of returning here.
780 rjmp breakpoint_failed
782 .size enter_monitor_mode, . - enter_monitor_mode
784 .type debug_trampoline, @function
785 .global debug_trampoline
788 * Save the registers on the stack so that the monitor code
789 * can find them easily.
791 sub sp, 4 /* r12_orig */
794 ld.w r8, r0[TI_rar_saved]
795 ld.w r9, r0[TI_rsr_saved]
799 * The monitor code will alter the return address so we don't
803 rjmp breakpoint_failed
804 .size debug_trampoline, . - debug_trampoline
806 .type breakpoint_failed, @function
809 * Something went wrong. Perhaps the debug hardware isn't
812 lda.w r12, msg_breakpoint_failed
814 mov r10, 9 /* SIGKILL */
818 msg_breakpoint_failed:
819 .asciz "Failed to enter Debug Mode"