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KVM: x86 emulator: implement 'ret far' instruction (opcode 0xcb)
[linux-2.6/linux-2.6-openrd.git] / arch / x86 / kvm / x86_emulate.c
blobca91749d2083ff71a44b66f4253bda00dff7f4b3
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_x86_emulate.h>
34
35 /*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44 /* Operand sizes: 8-bit operands or specified/overridden size. */
45 #define ByteOp (1<<0) /* 8-bit operands. */
46 /* Destination operand type. */
47 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48 #define DstReg (2<<1) /* Register operand. */
49 #define DstMem (3<<1) /* Memory operand. */
50 #define DstAcc (4<<1) /* Destination Accumulator */
51 #define DstMask (7<<1)
52 /* Source operand type. */
53 #define SrcNone (0<<4) /* No source operand. */
54 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55 #define SrcReg (1<<4) /* Register operand. */
56 #define SrcMem (2<<4) /* Memory operand. */
57 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59 #define SrcImm (5<<4) /* Immediate operand. */
60 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61 #define SrcOne (7<<4) /* Implied '1' */
62 #define SrcMask (7<<4)
63 /* Generic ModRM decode. */
64 #define ModRM (1<<7)
65 /* Destination is only written; never read. */
66 #define Mov (1<<8)
67 #define BitOp (1<<9)
68 #define MemAbs (1<<10) /* Memory operand is absolute displacement */
69 #define String (1<<12) /* String instruction (rep capable) */
70 #define Stack (1<<13) /* Stack instruction (push/pop) */
71 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
72 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
73 #define GroupMask 0xff /* Group number stored in bits 0:7 */
74 /* Source 2 operand type */
75 #define Src2None (0<<29)
76 #define Src2CL (1<<29)
77 #define Src2ImmByte (2<<29)
78 #define Src2One (3<<29)
79 #define Src2Mask (7<<29)
80
81 enum {
82 Group1_80, Group1_81, Group1_82, Group1_83,
83 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
84 };
85
86 static u32 opcode_table[256] = {
87 /* 0x00 - 0x07 */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
91 /* 0x08 - 0x0F */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x10 - 0x17 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x18 - 0x1F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 0, 0, 0, 0,
103 /* 0x20 - 0x27 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
106 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
107 /* 0x28 - 0x2F */
108 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 0, 0, 0, 0,
111 /* 0x30 - 0x37 */
112 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
113 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
114 0, 0, 0, 0,
115 /* 0x38 - 0x3F */
116 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
117 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
118 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
119 0, 0,
120 /* 0x40 - 0x47 */
121 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
122 /* 0x48 - 0x4F */
123 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
124 /* 0x50 - 0x57 */
125 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
126 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
127 /* 0x58 - 0x5F */
128 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
129 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
130 /* 0x60 - 0x67 */
131 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
132 0, 0, 0, 0,
133 /* 0x68 - 0x6F */
134 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
135 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
136 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
137 /* 0x70 - 0x77 */
138 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
139 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
140 /* 0x78 - 0x7F */
141 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
143 /* 0x80 - 0x87 */
144 Group | Group1_80, Group | Group1_81,
145 Group | Group1_82, Group | Group1_83,
146 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 /* 0x88 - 0x8F */
149 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
150 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
151 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
152 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
153 /* 0x90 - 0x97 */
154 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
155 /* 0x98 - 0x9F */
156 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
157 /* 0xA0 - 0xA7 */
158 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
159 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
160 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
161 ByteOp | ImplicitOps | String, ImplicitOps | String,
162 /* 0xA8 - 0xAF */
163 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
164 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
165 ByteOp | ImplicitOps | String, ImplicitOps | String,
166 /* 0xB0 - 0xB7 */
167 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
168 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
169 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 /* 0xB8 - 0xBF */
172 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
173 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
174 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
176 /* 0xC0 - 0xC7 */
177 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
178 0, ImplicitOps | Stack, 0, 0,
179 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
180 /* 0xC8 - 0xCF */
181 0, 0, 0, ImplicitOps | Stack, 0, 0, 0, 0,
182 /* 0xD0 - 0xD7 */
183 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
184 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
185 0, 0, 0, 0,
186 /* 0xD8 - 0xDF */
187 0, 0, 0, 0, 0, 0, 0, 0,
188 /* 0xE0 - 0xE7 */
189 0, 0, 0, 0,
190 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
191 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
192 /* 0xE8 - 0xEF */
193 ImplicitOps | Stack, SrcImm | ImplicitOps,
194 ImplicitOps, SrcImmByte | ImplicitOps,
195 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
196 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
197 /* 0xF0 - 0xF7 */
198 0, 0, 0, 0,
199 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
200 /* 0xF8 - 0xFF */
201 ImplicitOps, 0, ImplicitOps, ImplicitOps,
202 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
203 };
204
205 static u32 twobyte_table[256] = {
206 /* 0x00 - 0x0F */
207 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
208 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
209 /* 0x10 - 0x1F */
210 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
211 /* 0x20 - 0x2F */
212 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
213 0, 0, 0, 0, 0, 0, 0, 0,
214 /* 0x30 - 0x3F */
215 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0x40 - 0x47 */
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 /* 0x48 - 0x4F */
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 /* 0x50 - 0x5F */
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
228 /* 0x60 - 0x6F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0x70 - 0x7F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0x80 - 0x8F */
233 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
234 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
235 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
237 /* 0x90 - 0x9F */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xA0 - 0xA7 */
240 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
241 DstMem | SrcReg | Src2ImmByte | ModRM,
242 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
243 /* 0xA8 - 0xAF */
244 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
245 DstMem | SrcReg | Src2ImmByte | ModRM,
246 DstMem | SrcReg | Src2CL | ModRM,
247 ModRM, 0,
248 /* 0xB0 - 0xB7 */
249 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
250 DstMem | SrcReg | ModRM | BitOp,
251 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem16 | ModRM | Mov,
253 /* 0xB8 - 0xBF */
254 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
255 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
256 DstReg | SrcMem16 | ModRM | Mov,
257 /* 0xC0 - 0xCF */
258 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
259 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0xD0 - 0xDF */
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 /* 0xE0 - 0xEF */
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
264 /* 0xF0 - 0xFF */
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
266 };
267
268 static u32 group_table[] = {
269 [Group1_80*8] =
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 [Group1_81*8] =
275 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
276 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
277 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 [Group1_82*8] =
280 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
281 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
282 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 [Group1_83*8] =
285 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
286 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
287 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
289 [Group1A*8] =
290 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
291 [Group3_Byte*8] =
292 ByteOp | SrcImm | DstMem | ModRM, 0,
293 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
294 0, 0, 0, 0,
295 [Group3*8] =
296 DstMem | SrcImm | ModRM, 0,
297 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
298 0, 0, 0, 0,
299 [Group4*8] =
300 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
301 0, 0, 0, 0, 0, 0,
302 [Group5*8] =
303 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
304 SrcMem | ModRM | Stack, 0,
305 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
306 [Group7*8] =
307 0, 0, ModRM | SrcMem, ModRM | SrcMem,
308 SrcNone | ModRM | DstMem | Mov, 0,
309 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
310 };
311
312 static u32 group2_table[] = {
313 [Group7*8] =
314 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
315 SrcNone | ModRM | DstMem | Mov, 0,
316 SrcMem16 | ModRM | Mov, 0,
317 };
318
319 /* EFLAGS bit definitions. */
320 #define EFLG_OF (1<<11)
321 #define EFLG_DF (1<<10)
322 #define EFLG_SF (1<<7)
323 #define EFLG_ZF (1<<6)
324 #define EFLG_AF (1<<4)
325 #define EFLG_PF (1<<2)
326 #define EFLG_CF (1<<0)
327
328 /*
329 * Instruction emulation:
330 * Most instructions are emulated directly via a fragment of inline assembly
331 * code. This allows us to save/restore EFLAGS and thus very easily pick up
332 * any modified flags.
333 */
334
335 #if defined(CONFIG_X86_64)
336 #define _LO32 "k" /* force 32-bit operand */
337 #define _STK "%%rsp" /* stack pointer */
338 #elif defined(__i386__)
339 #define _LO32 "" /* force 32-bit operand */
340 #define _STK "%%esp" /* stack pointer */
341 #endif
342
343 /*
344 * These EFLAGS bits are restored from saved value during emulation, and
345 * any changes are written back to the saved value after emulation.
346 */
347 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
348
349 /* Before executing instruction: restore necessary bits in EFLAGS. */
350 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
351 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
352 "movl %"_sav",%"_LO32 _tmp"; " \
353 "push %"_tmp"; " \
354 "push %"_tmp"; " \
355 "movl %"_msk",%"_LO32 _tmp"; " \
356 "andl %"_LO32 _tmp",("_STK"); " \
357 "pushf; " \
358 "notl %"_LO32 _tmp"; " \
359 "andl %"_LO32 _tmp",("_STK"); " \
360 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
361 "pop %"_tmp"; " \
362 "orl %"_LO32 _tmp",("_STK"); " \
363 "popf; " \
364 "pop %"_sav"; "
365
366 /* After executing instruction: write-back necessary bits in EFLAGS. */
367 #define _POST_EFLAGS(_sav, _msk, _tmp) \
368 /* _sav |= EFLAGS & _msk; */ \
369 "pushf; " \
370 "pop %"_tmp"; " \
371 "andl %"_msk",%"_LO32 _tmp"; " \
372 "orl %"_LO32 _tmp",%"_sav"; "
373
374 #ifdef CONFIG_X86_64
375 #define ON64(x) x
376 #else
377 #define ON64(x)
378 #endif
379
380 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
381 do { \
382 __asm__ __volatile__ ( \
383 _PRE_EFLAGS("0", "4", "2") \
384 _op _suffix " %"_x"3,%1; " \
385 _POST_EFLAGS("0", "4", "2") \
386 : "=m" (_eflags), "=m" ((_dst).val), \
387 "=&r" (_tmp) \
388 : _y ((_src).val), "i" (EFLAGS_MASK)); \
389 } while (0)
390
391
392 /* Raw emulation: instruction has two explicit operands. */
393 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
394 do { \
395 unsigned long _tmp; \
396 \
397 switch ((_dst).bytes) { \
398 case 2: \
399 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
400 break; \
401 case 4: \
402 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
403 break; \
404 case 8: \
405 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
406 break; \
407 } \
408 } while (0)
409
410 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
411 do { \
412 unsigned long _tmp; \
413 switch ((_dst).bytes) { \
414 case 1: \
415 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
416 break; \
417 default: \
418 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
419 _wx, _wy, _lx, _ly, _qx, _qy); \
420 break; \
421 } \
422 } while (0)
423
424 /* Source operand is byte-sized and may be restricted to just %cl. */
425 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
426 __emulate_2op(_op, _src, _dst, _eflags, \
427 "b", "c", "b", "c", "b", "c", "b", "c")
428
429 /* Source operand is byte, word, long or quad sized. */
430 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
431 __emulate_2op(_op, _src, _dst, _eflags, \
432 "b", "q", "w", "r", _LO32, "r", "", "r")
433
434 /* Source operand is word, long or quad sized. */
435 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
436 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
437 "w", "r", _LO32, "r", "", "r")
438
439 /* Instruction has three operands and one operand is stored in ECX register */
440 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
441 do { \
442 unsigned long _tmp; \
443 _type _clv = (_cl).val; \
444 _type _srcv = (_src).val; \
445 _type _dstv = (_dst).val; \
446 \
447 __asm__ __volatile__ ( \
448 _PRE_EFLAGS("0", "5", "2") \
449 _op _suffix " %4,%1 \n" \
450 _POST_EFLAGS("0", "5", "2") \
451 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
452 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
453 ); \
454 \
455 (_cl).val = (unsigned long) _clv; \
456 (_src).val = (unsigned long) _srcv; \
457 (_dst).val = (unsigned long) _dstv; \
458 } while (0)
459
460 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
461 do { \
462 switch ((_dst).bytes) { \
463 case 2: \
464 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
465 "w", unsigned short); \
466 break; \
467 case 4: \
468 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
469 "l", unsigned int); \
470 break; \
471 case 8: \
472 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
473 "q", unsigned long)); \
474 break; \
475 } \
476 } while (0)
477
478 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
479 do { \
480 unsigned long _tmp; \
481 \
482 __asm__ __volatile__ ( \
483 _PRE_EFLAGS("0", "3", "2") \
484 _op _suffix " %1; " \
485 _POST_EFLAGS("0", "3", "2") \
486 : "=m" (_eflags), "+m" ((_dst).val), \
487 "=&r" (_tmp) \
488 : "i" (EFLAGS_MASK)); \
489 } while (0)
490
491 /* Instruction has only one explicit operand (no source operand). */
492 #define emulate_1op(_op, _dst, _eflags) \
493 do { \
494 switch ((_dst).bytes) { \
495 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
496 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
497 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
498 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
499 } \
500 } while (0)
501
502 /* Fetch next part of the instruction being emulated. */
503 #define insn_fetch(_type, _size, _eip) \
504 ({ unsigned long _x; \
505 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
506 if (rc != 0) \
507 goto done; \
508 (_eip) += (_size); \
509 (_type)_x; \
510 })
511
512 static inline unsigned long ad_mask(struct decode_cache *c)
513 {
514 return (1UL << (c->ad_bytes << 3)) - 1;
515 }
516
517 /* Access/update address held in a register, based on addressing mode. */
518 static inline unsigned long
519 address_mask(struct decode_cache *c, unsigned long reg)
520 {
521 if (c->ad_bytes == sizeof(unsigned long))
522 return reg;
523 else
524 return reg & ad_mask(c);
525 }
526
527 static inline unsigned long
528 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
529 {
530 return base + address_mask(c, reg);
531 }
532
533 static inline void
534 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
535 {
536 if (c->ad_bytes == sizeof(unsigned long))
537 *reg += inc;
538 else
539 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
540 }
541
542 static inline void jmp_rel(struct decode_cache *c, int rel)
543 {
544 register_address_increment(c, &c->eip, rel);
545 }
546
547 static void set_seg_override(struct decode_cache *c, int seg)
548 {
549 c->has_seg_override = true;
550 c->seg_override = seg;
551 }
552
553 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
554 {
555 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
556 return 0;
557
558 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
559 }
560
561 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
562 struct decode_cache *c)
563 {
564 if (!c->has_seg_override)
565 return 0;
566
567 return seg_base(ctxt, c->seg_override);
568 }
569
570 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
571 {
572 return seg_base(ctxt, VCPU_SREG_ES);
573 }
574
575 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
576 {
577 return seg_base(ctxt, VCPU_SREG_SS);
578 }
579
580 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
581 struct x86_emulate_ops *ops,
582 unsigned long linear, u8 *dest)
583 {
584 struct fetch_cache *fc = &ctxt->decode.fetch;
585 int rc;
586 int size;
587
588 if (linear < fc->start || linear >= fc->end) {
589 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
590 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
591 if (rc)
592 return rc;
593 fc->start = linear;
594 fc->end = linear + size;
595 }
596 *dest = fc->data[linear - fc->start];
597 return 0;
598 }
599
600 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
601 struct x86_emulate_ops *ops,
602 unsigned long eip, void *dest, unsigned size)
603 {
604 int rc = 0;
605
606 eip += ctxt->cs_base;
607 while (size--) {
608 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
609 if (rc)
610 return rc;
611 }
612 return 0;
613 }
614
615 /*
616 * Given the 'reg' portion of a ModRM byte, and a register block, return a
617 * pointer into the block that addresses the relevant register.
618 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
619 */
620 static void *decode_register(u8 modrm_reg, unsigned long *regs,
621 int highbyte_regs)
622 {
623 void *p;
624
625 p = &regs[modrm_reg];
626 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
627 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
628 return p;
629 }
630
631 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops,
633 void *ptr,
634 u16 *size, unsigned long *address, int op_bytes)
635 {
636 int rc;
637
638 if (op_bytes == 2)
639 op_bytes = 3;
640 *address = 0;
641 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
642 ctxt->vcpu);
643 if (rc)
644 return rc;
645 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
646 ctxt->vcpu);
647 return rc;
648 }
649
650 static int test_cc(unsigned int condition, unsigned int flags)
651 {
652 int rc = 0;
653
654 switch ((condition & 15) >> 1) {
655 case 0: /* o */
656 rc |= (flags & EFLG_OF);
657 break;
658 case 1: /* b/c/nae */
659 rc |= (flags & EFLG_CF);
660 break;
661 case 2: /* z/e */
662 rc |= (flags & EFLG_ZF);
663 break;
664 case 3: /* be/na */
665 rc |= (flags & (EFLG_CF|EFLG_ZF));
666 break;
667 case 4: /* s */
668 rc |= (flags & EFLG_SF);
669 break;
670 case 5: /* p/pe */
671 rc |= (flags & EFLG_PF);
672 break;
673 case 7: /* le/ng */
674 rc |= (flags & EFLG_ZF);
675 /* fall through */
676 case 6: /* l/nge */
677 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
678 break;
679 }
680
681 /* Odd condition identifiers (lsb == 1) have inverted sense. */
682 return (!!rc ^ (condition & 1));
683 }
684
685 static void decode_register_operand(struct operand *op,
686 struct decode_cache *c,
687 int inhibit_bytereg)
688 {
689 unsigned reg = c->modrm_reg;
690 int highbyte_regs = c->rex_prefix == 0;
691
692 if (!(c->d & ModRM))
693 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
694 op->type = OP_REG;
695 if ((c->d & ByteOp) && !inhibit_bytereg) {
696 op->ptr = decode_register(reg, c->regs, highbyte_regs);
697 op->val = *(u8 *)op->ptr;
698 op->bytes = 1;
699 } else {
700 op->ptr = decode_register(reg, c->regs, 0);
701 op->bytes = c->op_bytes;
702 switch (op->bytes) {
703 case 2:
704 op->val = *(u16 *)op->ptr;
705 break;
706 case 4:
707 op->val = *(u32 *)op->ptr;
708 break;
709 case 8:
710 op->val = *(u64 *) op->ptr;
711 break;
712 }
713 }
714 op->orig_val = op->val;
715 }
716
717 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
718 struct x86_emulate_ops *ops)
719 {
720 struct decode_cache *c = &ctxt->decode;
721 u8 sib;
722 int index_reg = 0, base_reg = 0, scale;
723 int rc = 0;
724
725 if (c->rex_prefix) {
726 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
727 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
728 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
729 }
730
731 c->modrm = insn_fetch(u8, 1, c->eip);
732 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
733 c->modrm_reg |= (c->modrm & 0x38) >> 3;
734 c->modrm_rm |= (c->modrm & 0x07);
735 c->modrm_ea = 0;
736 c->use_modrm_ea = 1;
737
738 if (c->modrm_mod == 3) {
739 c->modrm_ptr = decode_register(c->modrm_rm,
740 c->regs, c->d & ByteOp);
741 c->modrm_val = *(unsigned long *)c->modrm_ptr;
742 return rc;
743 }
744
745 if (c->ad_bytes == 2) {
746 unsigned bx = c->regs[VCPU_REGS_RBX];
747 unsigned bp = c->regs[VCPU_REGS_RBP];
748 unsigned si = c->regs[VCPU_REGS_RSI];
749 unsigned di = c->regs[VCPU_REGS_RDI];
750
751 /* 16-bit ModR/M decode. */
752 switch (c->modrm_mod) {
753 case 0:
754 if (c->modrm_rm == 6)
755 c->modrm_ea += insn_fetch(u16, 2, c->eip);
756 break;
757 case 1:
758 c->modrm_ea += insn_fetch(s8, 1, c->eip);
759 break;
760 case 2:
761 c->modrm_ea += insn_fetch(u16, 2, c->eip);
762 break;
763 }
764 switch (c->modrm_rm) {
765 case 0:
766 c->modrm_ea += bx + si;
767 break;
768 case 1:
769 c->modrm_ea += bx + di;
770 break;
771 case 2:
772 c->modrm_ea += bp + si;
773 break;
774 case 3:
775 c->modrm_ea += bp + di;
776 break;
777 case 4:
778 c->modrm_ea += si;
779 break;
780 case 5:
781 c->modrm_ea += di;
782 break;
783 case 6:
784 if (c->modrm_mod != 0)
785 c->modrm_ea += bp;
786 break;
787 case 7:
788 c->modrm_ea += bx;
789 break;
790 }
791 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
792 (c->modrm_rm == 6 && c->modrm_mod != 0))
793 if (!c->has_seg_override)
794 set_seg_override(c, VCPU_SREG_SS);
795 c->modrm_ea = (u16)c->modrm_ea;
796 } else {
797 /* 32/64-bit ModR/M decode. */
798 if ((c->modrm_rm & 7) == 4) {
799 sib = insn_fetch(u8, 1, c->eip);
800 index_reg |= (sib >> 3) & 7;
801 base_reg |= sib & 7;
802 scale = sib >> 6;
803
804 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
805 c->modrm_ea += insn_fetch(s32, 4, c->eip);
806 else
807 c->modrm_ea += c->regs[base_reg];
808 if (index_reg != 4)
809 c->modrm_ea += c->regs[index_reg] << scale;
810 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
811 if (ctxt->mode == X86EMUL_MODE_PROT64)
812 c->rip_relative = 1;
813 } else
814 c->modrm_ea += c->regs[c->modrm_rm];
815 switch (c->modrm_mod) {
816 case 0:
817 if (c->modrm_rm == 5)
818 c->modrm_ea += insn_fetch(s32, 4, c->eip);
819 break;
820 case 1:
821 c->modrm_ea += insn_fetch(s8, 1, c->eip);
822 break;
823 case 2:
824 c->modrm_ea += insn_fetch(s32, 4, c->eip);
825 break;
826 }
827 }
828 done:
829 return rc;
830 }
831
832 static int decode_abs(struct x86_emulate_ctxt *ctxt,
833 struct x86_emulate_ops *ops)
834 {
835 struct decode_cache *c = &ctxt->decode;
836 int rc = 0;
837
838 switch (c->ad_bytes) {
839 case 2:
840 c->modrm_ea = insn_fetch(u16, 2, c->eip);
841 break;
842 case 4:
843 c->modrm_ea = insn_fetch(u32, 4, c->eip);
844 break;
845 case 8:
846 c->modrm_ea = insn_fetch(u64, 8, c->eip);
847 break;
848 }
849 done:
850 return rc;
851 }
852
853 int
854 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
855 {
856 struct decode_cache *c = &ctxt->decode;
857 int rc = 0;
858 int mode = ctxt->mode;
859 int def_op_bytes, def_ad_bytes, group;
860
861 /* Shadow copy of register state. Committed on successful emulation. */
862
863 memset(c, 0, sizeof(struct decode_cache));
864 c->eip = kvm_rip_read(ctxt->vcpu);
865 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
866 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
867
868 switch (mode) {
869 case X86EMUL_MODE_REAL:
870 case X86EMUL_MODE_PROT16:
871 def_op_bytes = def_ad_bytes = 2;
872 break;
873 case X86EMUL_MODE_PROT32:
874 def_op_bytes = def_ad_bytes = 4;
875 break;
876 #ifdef CONFIG_X86_64
877 case X86EMUL_MODE_PROT64:
878 def_op_bytes = 4;
879 def_ad_bytes = 8;
880 break;
881 #endif
882 default:
883 return -1;
884 }
885
886 c->op_bytes = def_op_bytes;
887 c->ad_bytes = def_ad_bytes;
888
889 /* Legacy prefixes. */
890 for (;;) {
891 switch (c->b = insn_fetch(u8, 1, c->eip)) {
892 case 0x66: /* operand-size override */
893 /* switch between 2/4 bytes */
894 c->op_bytes = def_op_bytes ^ 6;
895 break;
896 case 0x67: /* address-size override */
897 if (mode == X86EMUL_MODE_PROT64)
898 /* switch between 4/8 bytes */
899 c->ad_bytes = def_ad_bytes ^ 12;
900 else
901 /* switch between 2/4 bytes */
902 c->ad_bytes = def_ad_bytes ^ 6;
903 break;
904 case 0x26: /* ES override */
905 case 0x2e: /* CS override */
906 case 0x36: /* SS override */
907 case 0x3e: /* DS override */
908 set_seg_override(c, (c->b >> 3) & 3);
909 break;
910 case 0x64: /* FS override */
911 case 0x65: /* GS override */
912 set_seg_override(c, c->b & 7);
913 break;
914 case 0x40 ... 0x4f: /* REX */
915 if (mode != X86EMUL_MODE_PROT64)
916 goto done_prefixes;
917 c->rex_prefix = c->b;
918 continue;
919 case 0xf0: /* LOCK */
920 c->lock_prefix = 1;
921 break;
922 case 0xf2: /* REPNE/REPNZ */
923 c->rep_prefix = REPNE_PREFIX;
924 break;
925 case 0xf3: /* REP/REPE/REPZ */
926 c->rep_prefix = REPE_PREFIX;
927 break;
928 default:
929 goto done_prefixes;
930 }
931
932 /* Any legacy prefix after a REX prefix nullifies its effect. */
933
934 c->rex_prefix = 0;
935 }
936
937 done_prefixes:
938
939 /* REX prefix. */
940 if (c->rex_prefix)
941 if (c->rex_prefix & 8)
942 c->op_bytes = 8; /* REX.W */
943
944 /* Opcode byte(s). */
945 c->d = opcode_table[c->b];
946 if (c->d == 0) {
947 /* Two-byte opcode? */
948 if (c->b == 0x0f) {
949 c->twobyte = 1;
950 c->b = insn_fetch(u8, 1, c->eip);
951 c->d = twobyte_table[c->b];
952 }
953 }
954
955 if (c->d & Group) {
956 group = c->d & GroupMask;
957 c->modrm = insn_fetch(u8, 1, c->eip);
958 --c->eip;
959
960 group = (group << 3) + ((c->modrm >> 3) & 7);
961 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
962 c->d = group2_table[group];
963 else
964 c->d = group_table[group];
965 }
966
967 /* Unrecognised? */
968 if (c->d == 0) {
969 DPRINTF("Cannot emulate %02x\n", c->b);
970 return -1;
971 }
972
973 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
974 c->op_bytes = 8;
975
976 /* ModRM and SIB bytes. */
977 if (c->d & ModRM)
978 rc = decode_modrm(ctxt, ops);
979 else if (c->d & MemAbs)
980 rc = decode_abs(ctxt, ops);
981 if (rc)
982 goto done;
983
984 if (!c->has_seg_override)
985 set_seg_override(c, VCPU_SREG_DS);
986
987 if (!(!c->twobyte && c->b == 0x8d))
988 c->modrm_ea += seg_override_base(ctxt, c);
989
990 if (c->ad_bytes != 8)
991 c->modrm_ea = (u32)c->modrm_ea;
992 /*
993 * Decode and fetch the source operand: register, memory
994 * or immediate.
995 */
996 switch (c->d & SrcMask) {
997 case SrcNone:
998 break;
999 case SrcReg:
1000 decode_register_operand(&c->src, c, 0);
1001 break;
1002 case SrcMem16:
1003 c->src.bytes = 2;
1004 goto srcmem_common;
1005 case SrcMem32:
1006 c->src.bytes = 4;
1007 goto srcmem_common;
1008 case SrcMem:
1009 c->src.bytes = (c->d & ByteOp) ? 1 :
1010 c->op_bytes;
1011 /* Don't fetch the address for invlpg: it could be unmapped. */
1012 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1013 break;
1014 srcmem_common:
1015 /*
1016 * For instructions with a ModR/M byte, switch to register
1017 * access if Mod = 3.
1018 */
1019 if ((c->d & ModRM) && c->modrm_mod == 3) {
1020 c->src.type = OP_REG;
1021 c->src.val = c->modrm_val;
1022 c->src.ptr = c->modrm_ptr;
1023 break;
1024 }
1025 c->src.type = OP_MEM;
1026 break;
1027 case SrcImm:
1028 c->src.type = OP_IMM;
1029 c->src.ptr = (unsigned long *)c->eip;
1030 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1031 if (c->src.bytes == 8)
1032 c->src.bytes = 4;
1033 /* NB. Immediates are sign-extended as necessary. */
1034 switch (c->src.bytes) {
1035 case 1:
1036 c->src.val = insn_fetch(s8, 1, c->eip);
1037 break;
1038 case 2:
1039 c->src.val = insn_fetch(s16, 2, c->eip);
1040 break;
1041 case 4:
1042 c->src.val = insn_fetch(s32, 4, c->eip);
1043 break;
1044 }
1045 break;
1046 case SrcImmByte:
1047 c->src.type = OP_IMM;
1048 c->src.ptr = (unsigned long *)c->eip;
1049 c->src.bytes = 1;
1050 c->src.val = insn_fetch(s8, 1, c->eip);
1051 break;
1052 case SrcOne:
1053 c->src.bytes = 1;
1054 c->src.val = 1;
1055 break;
1056 }
1057
1058 /*
1059 * Decode and fetch the second source operand: register, memory
1060 * or immediate.
1061 */
1062 switch (c->d & Src2Mask) {
1063 case Src2None:
1064 break;
1065 case Src2CL:
1066 c->src2.bytes = 1;
1067 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1068 break;
1069 case Src2ImmByte:
1070 c->src2.type = OP_IMM;
1071 c->src2.ptr = (unsigned long *)c->eip;
1072 c->src2.bytes = 1;
1073 c->src2.val = insn_fetch(u8, 1, c->eip);
1074 break;
1075 case Src2One:
1076 c->src2.bytes = 1;
1077 c->src2.val = 1;
1078 break;
1079 }
1080
1081 /* Decode and fetch the destination operand: register or memory. */
1082 switch (c->d & DstMask) {
1083 case ImplicitOps:
1084 /* Special instructions do their own operand decoding. */
1085 return 0;
1086 case DstReg:
1087 decode_register_operand(&c->dst, c,
1088 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1089 break;
1090 case DstMem:
1091 if ((c->d & ModRM) && c->modrm_mod == 3) {
1092 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1093 c->dst.type = OP_REG;
1094 c->dst.val = c->dst.orig_val = c->modrm_val;
1095 c->dst.ptr = c->modrm_ptr;
1096 break;
1097 }
1098 c->dst.type = OP_MEM;
1099 break;
1100 case DstAcc:
1101 c->dst.type = OP_REG;
1102 c->dst.bytes = c->op_bytes;
1103 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1104 switch (c->op_bytes) {
1105 case 1:
1106 c->dst.val = *(u8 *)c->dst.ptr;
1107 break;
1108 case 2:
1109 c->dst.val = *(u16 *)c->dst.ptr;
1110 break;
1111 case 4:
1112 c->dst.val = *(u32 *)c->dst.ptr;
1113 break;
1114 }
1115 c->dst.orig_val = c->dst.val;
1116 break;
1117 }
1118
1119 if (c->rip_relative)
1120 c->modrm_ea += c->eip;
1121
1122 done:
1123 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1124 }
1125
1126 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1127 {
1128 struct decode_cache *c = &ctxt->decode;
1129
1130 c->dst.type = OP_MEM;
1131 c->dst.bytes = c->op_bytes;
1132 c->dst.val = c->src.val;
1133 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1134 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1135 c->regs[VCPU_REGS_RSP]);
1136 }
1137
1138 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops,
1140 void *dest, int len)
1141 {
1142 struct decode_cache *c = &ctxt->decode;
1143 int rc;
1144
1145 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1146 c->regs[VCPU_REGS_RSP]),
1147 dest, len, ctxt->vcpu);
1148 if (rc != 0)
1149 return rc;
1150
1151 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1152 return rc;
1153 }
1154
1155 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1156 struct x86_emulate_ops *ops)
1157 {
1158 struct decode_cache *c = &ctxt->decode;
1159 int rc;
1160
1161 rc = emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1162 if (rc != 0)
1163 return rc;
1164 return 0;
1165 }
1166
1167 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1168 {
1169 struct decode_cache *c = &ctxt->decode;
1170 switch (c->modrm_reg) {
1171 case 0: /* rol */
1172 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1173 break;
1174 case 1: /* ror */
1175 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1176 break;
1177 case 2: /* rcl */
1178 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1179 break;
1180 case 3: /* rcr */
1181 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1182 break;
1183 case 4: /* sal/shl */
1184 case 6: /* sal/shl */
1185 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1186 break;
1187 case 5: /* shr */
1188 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1189 break;
1190 case 7: /* sar */
1191 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1192 break;
1193 }
1194 }
1195
1196 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1197 struct x86_emulate_ops *ops)
1198 {
1199 struct decode_cache *c = &ctxt->decode;
1200 int rc = 0;
1201
1202 switch (c->modrm_reg) {
1203 case 0 ... 1: /* test */
1204 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1205 break;
1206 case 2: /* not */
1207 c->dst.val = ~c->dst.val;
1208 break;
1209 case 3: /* neg */
1210 emulate_1op("neg", c->dst, ctxt->eflags);
1211 break;
1212 default:
1213 DPRINTF("Cannot emulate %02x\n", c->b);
1214 rc = X86EMUL_UNHANDLEABLE;
1215 break;
1216 }
1217 return rc;
1218 }
1219
1220 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1221 struct x86_emulate_ops *ops)
1222 {
1223 struct decode_cache *c = &ctxt->decode;
1224
1225 switch (c->modrm_reg) {
1226 case 0: /* inc */
1227 emulate_1op("inc", c->dst, ctxt->eflags);
1228 break;
1229 case 1: /* dec */
1230 emulate_1op("dec", c->dst, ctxt->eflags);
1231 break;
1232 case 2: /* call near abs */ {
1233 long int old_eip;
1234 old_eip = c->eip;
1235 c->eip = c->src.val;
1236 c->src.val = old_eip;
1237 emulate_push(ctxt);
1238 break;
1239 }
1240 case 4: /* jmp abs */
1241 c->eip = c->src.val;
1242 break;
1243 case 6: /* push */
1244 emulate_push(ctxt);
1245 break;
1246 }
1247 return 0;
1248 }
1249
1250 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1251 struct x86_emulate_ops *ops,
1252 unsigned long memop)
1253 {
1254 struct decode_cache *c = &ctxt->decode;
1255 u64 old, new;
1256 int rc;
1257
1258 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1259 if (rc != 0)
1260 return rc;
1261
1262 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1263 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1264
1265 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1266 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1267 ctxt->eflags &= ~EFLG_ZF;
1268
1269 } else {
1270 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1271 (u32) c->regs[VCPU_REGS_RBX];
1272
1273 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1274 if (rc != 0)
1275 return rc;
1276 ctxt->eflags |= EFLG_ZF;
1277 }
1278 return 0;
1279 }
1280
1281 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1282 struct x86_emulate_ops *ops)
1283 {
1284 struct decode_cache *c = &ctxt->decode;
1285 int rc;
1286 unsigned long cs;
1287
1288 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1289 if (rc)
1290 return rc;
1291 if (c->op_bytes == 4)
1292 c->eip = (u32)c->eip;
1293 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1294 if (rc)
1295 return rc;
1296 rc = kvm_load_segment_descriptor(ctxt->vcpu, (u16)cs, 1, VCPU_SREG_CS);
1297 return rc;
1298 }
1299
1300 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1301 struct x86_emulate_ops *ops)
1302 {
1303 int rc;
1304 struct decode_cache *c = &ctxt->decode;
1305
1306 switch (c->dst.type) {
1307 case OP_REG:
1308 /* The 4-byte case *is* correct:
1309 * in 64-bit mode we zero-extend.
1310 */
1311 switch (c->dst.bytes) {
1312 case 1:
1313 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1314 break;
1315 case 2:
1316 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1317 break;
1318 case 4:
1319 *c->dst.ptr = (u32)c->dst.val;
1320 break; /* 64b: zero-ext */
1321 case 8:
1322 *c->dst.ptr = c->dst.val;
1323 break;
1324 }
1325 break;
1326 case OP_MEM:
1327 if (c->lock_prefix)
1328 rc = ops->cmpxchg_emulated(
1329 (unsigned long)c->dst.ptr,
1330 &c->dst.orig_val,
1331 &c->dst.val,
1332 c->dst.bytes,
1333 ctxt->vcpu);
1334 else
1335 rc = ops->write_emulated(
1336 (unsigned long)c->dst.ptr,
1337 &c->dst.val,
1338 c->dst.bytes,
1339 ctxt->vcpu);
1340 if (rc != 0)
1341 return rc;
1342 break;
1343 case OP_NONE:
1344 /* no writeback */
1345 break;
1346 default:
1347 break;
1348 }
1349 return 0;
1350 }
1351
1352 int
1353 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1354 {
1355 unsigned long memop = 0;
1356 u64 msr_data;
1357 unsigned long saved_eip = 0;
1358 struct decode_cache *c = &ctxt->decode;
1359 unsigned int port;
1360 int io_dir_in;
1361 int rc = 0;
1362
1363 /* Shadow copy of register state. Committed on successful emulation.
1364 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1365 * modify them.
1366 */
1367
1368 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1369 saved_eip = c->eip;
1370
1371 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1372 memop = c->modrm_ea;
1373
1374 if (c->rep_prefix && (c->d & String)) {
1375 /* All REP prefixes have the same first termination condition */
1376 if (c->regs[VCPU_REGS_RCX] == 0) {
1377 kvm_rip_write(ctxt->vcpu, c->eip);
1378 goto done;
1379 }
1380 /* The second termination condition only applies for REPE
1381 * and REPNE. Test if the repeat string operation prefix is
1382 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1383 * corresponding termination condition according to:
1384 * - if REPE/REPZ and ZF = 0 then done
1385 * - if REPNE/REPNZ and ZF = 1 then done
1386 */
1387 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1388 (c->b == 0xae) || (c->b == 0xaf)) {
1389 if ((c->rep_prefix == REPE_PREFIX) &&
1390 ((ctxt->eflags & EFLG_ZF) == 0)) {
1391 kvm_rip_write(ctxt->vcpu, c->eip);
1392 goto done;
1393 }
1394 if ((c->rep_prefix == REPNE_PREFIX) &&
1395 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1396 kvm_rip_write(ctxt->vcpu, c->eip);
1397 goto done;
1398 }
1399 }
1400 c->regs[VCPU_REGS_RCX]--;
1401 c->eip = kvm_rip_read(ctxt->vcpu);
1402 }
1403
1404 if (c->src.type == OP_MEM) {
1405 c->src.ptr = (unsigned long *)memop;
1406 c->src.val = 0;
1407 rc = ops->read_emulated((unsigned long)c->src.ptr,
1408 &c->src.val,
1409 c->src.bytes,
1410 ctxt->vcpu);
1411 if (rc != 0)
1412 goto done;
1413 c->src.orig_val = c->src.val;
1414 }
1415
1416 if ((c->d & DstMask) == ImplicitOps)
1417 goto special_insn;
1418
1419
1420 if (c->dst.type == OP_MEM) {
1421 c->dst.ptr = (unsigned long *)memop;
1422 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1423 c->dst.val = 0;
1424 if (c->d & BitOp) {
1425 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1426
1427 c->dst.ptr = (void *)c->dst.ptr +
1428 (c->src.val & mask) / 8;
1429 }
1430 if (!(c->d & Mov) &&
1431 /* optimisation - avoid slow emulated read */
1432 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1433 &c->dst.val,
1434 c->dst.bytes, ctxt->vcpu)) != 0))
1435 goto done;
1436 }
1437 c->dst.orig_val = c->dst.val;
1438
1439 special_insn:
1440
1441 if (c->twobyte)
1442 goto twobyte_insn;
1443
1444 switch (c->b) {
1445 case 0x00 ... 0x05:
1446 add: /* add */
1447 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1448 break;
1449 case 0x08 ... 0x0d:
1450 or: /* or */
1451 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1452 break;
1453 case 0x10 ... 0x15:
1454 adc: /* adc */
1455 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1456 break;
1457 case 0x18 ... 0x1d:
1458 sbb: /* sbb */
1459 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1460 break;
1461 case 0x20 ... 0x25:
1462 and: /* and */
1463 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1464 break;
1465 case 0x28 ... 0x2d:
1466 sub: /* sub */
1467 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1468 break;
1469 case 0x30 ... 0x35:
1470 xor: /* xor */
1471 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1472 break;
1473 case 0x38 ... 0x3d:
1474 cmp: /* cmp */
1475 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1476 break;
1477 case 0x40 ... 0x47: /* inc r16/r32 */
1478 emulate_1op("inc", c->dst, ctxt->eflags);
1479 break;
1480 case 0x48 ... 0x4f: /* dec r16/r32 */
1481 emulate_1op("dec", c->dst, ctxt->eflags);
1482 break;
1483 case 0x50 ... 0x57: /* push reg */
1484 emulate_push(ctxt);
1485 break;
1486 case 0x58 ... 0x5f: /* pop reg */
1487 pop_instruction:
1488 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
1489 if (rc != 0)
1490 goto done;
1491 break;
1492 case 0x63: /* movsxd */
1493 if (ctxt->mode != X86EMUL_MODE_PROT64)
1494 goto cannot_emulate;
1495 c->dst.val = (s32) c->src.val;
1496 break;
1497 case 0x68: /* push imm */
1498 case 0x6a: /* push imm8 */
1499 emulate_push(ctxt);
1500 break;
1501 case 0x6c: /* insb */
1502 case 0x6d: /* insw/insd */
1503 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1504 1,
1505 (c->d & ByteOp) ? 1 : c->op_bytes,
1506 c->rep_prefix ?
1507 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1508 (ctxt->eflags & EFLG_DF),
1509 register_address(c, es_base(ctxt),
1510 c->regs[VCPU_REGS_RDI]),
1511 c->rep_prefix,
1512 c->regs[VCPU_REGS_RDX]) == 0) {
1513 c->eip = saved_eip;
1514 return -1;
1515 }
1516 return 0;
1517 case 0x6e: /* outsb */
1518 case 0x6f: /* outsw/outsd */
1519 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1520 0,
1521 (c->d & ByteOp) ? 1 : c->op_bytes,
1522 c->rep_prefix ?
1523 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1524 (ctxt->eflags & EFLG_DF),
1525 register_address(c,
1526 seg_override_base(ctxt, c),
1527 c->regs[VCPU_REGS_RSI]),
1528 c->rep_prefix,
1529 c->regs[VCPU_REGS_RDX]) == 0) {
1530 c->eip = saved_eip;
1531 return -1;
1532 }
1533 return 0;
1534 case 0x70 ... 0x7f: /* jcc (short) */ {
1535 int rel = insn_fetch(s8, 1, c->eip);
1536
1537 if (test_cc(c->b, ctxt->eflags))
1538 jmp_rel(c, rel);
1539 break;
1540 }
1541 case 0x80 ... 0x83: /* Grp1 */
1542 switch (c->modrm_reg) {
1543 case 0:
1544 goto add;
1545 case 1:
1546 goto or;
1547 case 2:
1548 goto adc;
1549 case 3:
1550 goto sbb;
1551 case 4:
1552 goto and;
1553 case 5:
1554 goto sub;
1555 case 6:
1556 goto xor;
1557 case 7:
1558 goto cmp;
1559 }
1560 break;
1561 case 0x84 ... 0x85:
1562 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1563 break;
1564 case 0x86 ... 0x87: /* xchg */
1565 xchg:
1566 /* Write back the register source. */
1567 switch (c->dst.bytes) {
1568 case 1:
1569 *(u8 *) c->src.ptr = (u8) c->dst.val;
1570 break;
1571 case 2:
1572 *(u16 *) c->src.ptr = (u16) c->dst.val;
1573 break;
1574 case 4:
1575 *c->src.ptr = (u32) c->dst.val;
1576 break; /* 64b reg: zero-extend */
1577 case 8:
1578 *c->src.ptr = c->dst.val;
1579 break;
1580 }
1581 /*
1582 * Write back the memory destination with implicit LOCK
1583 * prefix.
1584 */
1585 c->dst.val = c->src.val;
1586 c->lock_prefix = 1;
1587 break;
1588 case 0x88 ... 0x8b: /* mov */
1589 goto mov;
1590 case 0x8c: { /* mov r/m, sreg */
1591 struct kvm_segment segreg;
1592
1593 if (c->modrm_reg <= 5)
1594 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1595 else {
1596 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1597 c->modrm);
1598 goto cannot_emulate;
1599 }
1600 c->dst.val = segreg.selector;
1601 break;
1602 }
1603 case 0x8d: /* lea r16/r32, m */
1604 c->dst.val = c->modrm_ea;
1605 break;
1606 case 0x8e: { /* mov seg, r/m16 */
1607 uint16_t sel;
1608 int type_bits;
1609 int err;
1610
1611 sel = c->src.val;
1612 if (c->modrm_reg <= 5) {
1613 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1614 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1615 type_bits, c->modrm_reg);
1616 } else {
1617 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1618 c->modrm);
1619 goto cannot_emulate;
1620 }
1621
1622 if (err < 0)
1623 goto cannot_emulate;
1624
1625 c->dst.type = OP_NONE; /* Disable writeback. */
1626 break;
1627 }
1628 case 0x8f: /* pop (sole member of Grp1a) */
1629 rc = emulate_grp1a(ctxt, ops);
1630 if (rc != 0)
1631 goto done;
1632 break;
1633 case 0x90: /* nop / xchg r8,rax */
1634 if (!(c->rex_prefix & 1)) { /* nop */
1635 c->dst.type = OP_NONE;
1636 break;
1637 }
1638 case 0x91 ... 0x97: /* xchg reg,rax */
1639 c->src.type = c->dst.type = OP_REG;
1640 c->src.bytes = c->dst.bytes = c->op_bytes;
1641 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1642 c->src.val = *(c->src.ptr);
1643 goto xchg;
1644 case 0x9c: /* pushf */
1645 c->src.val = (unsigned long) ctxt->eflags;
1646 emulate_push(ctxt);
1647 break;
1648 case 0x9d: /* popf */
1649 c->dst.type = OP_REG;
1650 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1651 c->dst.bytes = c->op_bytes;
1652 goto pop_instruction;
1653 case 0xa0 ... 0xa1: /* mov */
1654 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1655 c->dst.val = c->src.val;
1656 break;
1657 case 0xa2 ... 0xa3: /* mov */
1658 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1659 break;
1660 case 0xa4 ... 0xa5: /* movs */
1661 c->dst.type = OP_MEM;
1662 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1663 c->dst.ptr = (unsigned long *)register_address(c,
1664 es_base(ctxt),
1665 c->regs[VCPU_REGS_RDI]);
1666 if ((rc = ops->read_emulated(register_address(c,
1667 seg_override_base(ctxt, c),
1668 c->regs[VCPU_REGS_RSI]),
1669 &c->dst.val,
1670 c->dst.bytes, ctxt->vcpu)) != 0)
1671 goto done;
1672 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1673 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1674 : c->dst.bytes);
1675 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1676 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1677 : c->dst.bytes);
1678 break;
1679 case 0xa6 ... 0xa7: /* cmps */
1680 c->src.type = OP_NONE; /* Disable writeback. */
1681 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1682 c->src.ptr = (unsigned long *)register_address(c,
1683 seg_override_base(ctxt, c),
1684 c->regs[VCPU_REGS_RSI]);
1685 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1686 &c->src.val,
1687 c->src.bytes,
1688 ctxt->vcpu)) != 0)
1689 goto done;
1690
1691 c->dst.type = OP_NONE; /* Disable writeback. */
1692 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1693 c->dst.ptr = (unsigned long *)register_address(c,
1694 es_base(ctxt),
1695 c->regs[VCPU_REGS_RDI]);
1696 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1697 &c->dst.val,
1698 c->dst.bytes,
1699 ctxt->vcpu)) != 0)
1700 goto done;
1701
1702 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1703
1704 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1705
1706 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1707 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1708 : c->src.bytes);
1709 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1710 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1711 : c->dst.bytes);
1712
1713 break;
1714 case 0xaa ... 0xab: /* stos */
1715 c->dst.type = OP_MEM;
1716 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1717 c->dst.ptr = (unsigned long *)register_address(c,
1718 es_base(ctxt),
1719 c->regs[VCPU_REGS_RDI]);
1720 c->dst.val = c->regs[VCPU_REGS_RAX];
1721 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1722 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1723 : c->dst.bytes);
1724 break;
1725 case 0xac ... 0xad: /* lods */
1726 c->dst.type = OP_REG;
1727 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1728 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1729 if ((rc = ops->read_emulated(register_address(c,
1730 seg_override_base(ctxt, c),
1731 c->regs[VCPU_REGS_RSI]),
1732 &c->dst.val,
1733 c->dst.bytes,
1734 ctxt->vcpu)) != 0)
1735 goto done;
1736 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1737 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1738 : c->dst.bytes);
1739 break;
1740 case 0xae ... 0xaf: /* scas */
1741 DPRINTF("Urk! I don't handle SCAS.\n");
1742 goto cannot_emulate;
1743 case 0xb0 ... 0xbf: /* mov r, imm */
1744 goto mov;
1745 case 0xc0 ... 0xc1:
1746 emulate_grp2(ctxt);
1747 break;
1748 case 0xc3: /* ret */
1749 c->dst.type = OP_REG;
1750 c->dst.ptr = &c->eip;
1751 c->dst.bytes = c->op_bytes;
1752 goto pop_instruction;
1753 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1754 mov:
1755 c->dst.val = c->src.val;
1756 break;
1757 case 0xcb: /* ret far */
1758 rc = emulate_ret_far(ctxt, ops);
1759 if (rc)
1760 goto done;
1761 break;
1762 case 0xd0 ... 0xd1: /* Grp2 */
1763 c->src.val = 1;
1764 emulate_grp2(ctxt);
1765 break;
1766 case 0xd2 ... 0xd3: /* Grp2 */
1767 c->src.val = c->regs[VCPU_REGS_RCX];
1768 emulate_grp2(ctxt);
1769 break;
1770 case 0xe4: /* inb */
1771 case 0xe5: /* in */
1772 port = insn_fetch(u8, 1, c->eip);
1773 io_dir_in = 1;
1774 goto do_io;
1775 case 0xe6: /* outb */
1776 case 0xe7: /* out */
1777 port = insn_fetch(u8, 1, c->eip);
1778 io_dir_in = 0;
1779 goto do_io;
1780 case 0xe8: /* call (near) */ {
1781 long int rel;
1782 switch (c->op_bytes) {
1783 case 2:
1784 rel = insn_fetch(s16, 2, c->eip);
1785 break;
1786 case 4:
1787 rel = insn_fetch(s32, 4, c->eip);
1788 break;
1789 default:
1790 DPRINTF("Call: Invalid op_bytes\n");
1791 goto cannot_emulate;
1792 }
1793 c->src.val = (unsigned long) c->eip;
1794 jmp_rel(c, rel);
1795 c->op_bytes = c->ad_bytes;
1796 emulate_push(ctxt);
1797 break;
1798 }
1799 case 0xe9: /* jmp rel */
1800 goto jmp;
1801 case 0xea: /* jmp far */ {
1802 uint32_t eip;
1803 uint16_t sel;
1804
1805 switch (c->op_bytes) {
1806 case 2:
1807 eip = insn_fetch(u16, 2, c->eip);
1808 break;
1809 case 4:
1810 eip = insn_fetch(u32, 4, c->eip);
1811 break;
1812 default:
1813 DPRINTF("jmp far: Invalid op_bytes\n");
1814 goto cannot_emulate;
1815 }
1816 sel = insn_fetch(u16, 2, c->eip);
1817 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1818 DPRINTF("jmp far: Failed to load CS descriptor\n");
1819 goto cannot_emulate;
1820 }
1821
1822 c->eip = eip;
1823 break;
1824 }
1825 case 0xeb:
1826 jmp: /* jmp rel short */
1827 jmp_rel(c, c->src.val);
1828 c->dst.type = OP_NONE; /* Disable writeback. */
1829 break;
1830 case 0xec: /* in al,dx */
1831 case 0xed: /* in (e/r)ax,dx */
1832 port = c->regs[VCPU_REGS_RDX];
1833 io_dir_in = 1;
1834 goto do_io;
1835 case 0xee: /* out al,dx */
1836 case 0xef: /* out (e/r)ax,dx */
1837 port = c->regs[VCPU_REGS_RDX];
1838 io_dir_in = 0;
1839 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1840 (c->d & ByteOp) ? 1 : c->op_bytes,
1841 port) != 0) {
1842 c->eip = saved_eip;
1843 goto cannot_emulate;
1844 }
1845 break;
1846 case 0xf4: /* hlt */
1847 ctxt->vcpu->arch.halt_request = 1;
1848 break;
1849 case 0xf5: /* cmc */
1850 /* complement carry flag from eflags reg */
1851 ctxt->eflags ^= EFLG_CF;
1852 c->dst.type = OP_NONE; /* Disable writeback. */
1853 break;
1854 case 0xf6 ... 0xf7: /* Grp3 */
1855 rc = emulate_grp3(ctxt, ops);
1856 if (rc != 0)
1857 goto done;
1858 break;
1859 case 0xf8: /* clc */
1860 ctxt->eflags &= ~EFLG_CF;
1861 c->dst.type = OP_NONE; /* Disable writeback. */
1862 break;
1863 case 0xfa: /* cli */
1864 ctxt->eflags &= ~X86_EFLAGS_IF;
1865 c->dst.type = OP_NONE; /* Disable writeback. */
1866 break;
1867 case 0xfb: /* sti */
1868 ctxt->eflags |= X86_EFLAGS_IF;
1869 c->dst.type = OP_NONE; /* Disable writeback. */
1870 break;
1871 case 0xfc: /* cld */
1872 ctxt->eflags &= ~EFLG_DF;
1873 c->dst.type = OP_NONE; /* Disable writeback. */
1874 break;
1875 case 0xfd: /* std */
1876 ctxt->eflags |= EFLG_DF;
1877 c->dst.type = OP_NONE; /* Disable writeback. */
1878 break;
1879 case 0xfe ... 0xff: /* Grp4/Grp5 */
1880 rc = emulate_grp45(ctxt, ops);
1881 if (rc != 0)
1882 goto done;
1883 break;
1884 }
1885
1886 writeback:
1887 rc = writeback(ctxt, ops);
1888 if (rc != 0)
1889 goto done;
1890
1891 /* Commit shadow register state. */
1892 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1893 kvm_rip_write(ctxt->vcpu, c->eip);
1894
1895 done:
1896 if (rc == X86EMUL_UNHANDLEABLE) {
1897 c->eip = saved_eip;
1898 return -1;
1899 }
1900 return 0;
1901
1902 twobyte_insn:
1903 switch (c->b) {
1904 case 0x01: /* lgdt, lidt, lmsw */
1905 switch (c->modrm_reg) {
1906 u16 size;
1907 unsigned long address;
1908
1909 case 0: /* vmcall */
1910 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1911 goto cannot_emulate;
1912
1913 rc = kvm_fix_hypercall(ctxt->vcpu);
1914 if (rc)
1915 goto done;
1916
1917 /* Let the processor re-execute the fixed hypercall */
1918 c->eip = kvm_rip_read(ctxt->vcpu);
1919 /* Disable writeback. */
1920 c->dst.type = OP_NONE;
1921 break;
1922 case 2: /* lgdt */
1923 rc = read_descriptor(ctxt, ops, c->src.ptr,
1924 &size, &address, c->op_bytes);
1925 if (rc)
1926 goto done;
1927 realmode_lgdt(ctxt->vcpu, size, address);
1928 /* Disable writeback. */
1929 c->dst.type = OP_NONE;
1930 break;
1931 case 3: /* lidt/vmmcall */
1932 if (c->modrm_mod == 3) {
1933 switch (c->modrm_rm) {
1934 case 1:
1935 rc = kvm_fix_hypercall(ctxt->vcpu);
1936 if (rc)
1937 goto done;
1938 break;
1939 default:
1940 goto cannot_emulate;
1941 }
1942 } else {
1943 rc = read_descriptor(ctxt, ops, c->src.ptr,
1944 &size, &address,
1945 c->op_bytes);
1946 if (rc)
1947 goto done;
1948 realmode_lidt(ctxt->vcpu, size, address);
1949 }
1950 /* Disable writeback. */
1951 c->dst.type = OP_NONE;
1952 break;
1953 case 4: /* smsw */
1954 c->dst.bytes = 2;
1955 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
1956 break;
1957 case 6: /* lmsw */
1958 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1959 &ctxt->eflags);
1960 c->dst.type = OP_NONE;
1961 break;
1962 case 7: /* invlpg*/
1963 emulate_invlpg(ctxt->vcpu, memop);
1964 /* Disable writeback. */
1965 c->dst.type = OP_NONE;
1966 break;
1967 default:
1968 goto cannot_emulate;
1969 }
1970 break;
1971 case 0x06:
1972 emulate_clts(ctxt->vcpu);
1973 c->dst.type = OP_NONE;
1974 break;
1975 case 0x08: /* invd */
1976 case 0x09: /* wbinvd */
1977 case 0x0d: /* GrpP (prefetch) */
1978 case 0x18: /* Grp16 (prefetch/nop) */
1979 c->dst.type = OP_NONE;
1980 break;
1981 case 0x20: /* mov cr, reg */
1982 if (c->modrm_mod != 3)
1983 goto cannot_emulate;
1984 c->regs[c->modrm_rm] =
1985 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1986 c->dst.type = OP_NONE; /* no writeback */
1987 break;
1988 case 0x21: /* mov from dr to reg */
1989 if (c->modrm_mod != 3)
1990 goto cannot_emulate;
1991 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1992 if (rc)
1993 goto cannot_emulate;
1994 c->dst.type = OP_NONE; /* no writeback */
1995 break;
1996 case 0x22: /* mov reg, cr */
1997 if (c->modrm_mod != 3)
1998 goto cannot_emulate;
1999 realmode_set_cr(ctxt->vcpu,
2000 c->modrm_reg, c->modrm_val, &ctxt->eflags);
2001 c->dst.type = OP_NONE;
2002 break;
2003 case 0x23: /* mov from reg to dr */
2004 if (c->modrm_mod != 3)
2005 goto cannot_emulate;
2006 rc = emulator_set_dr(ctxt, c->modrm_reg,
2007 c->regs[c->modrm_rm]);
2008 if (rc)
2009 goto cannot_emulate;
2010 c->dst.type = OP_NONE; /* no writeback */
2011 break;
2012 case 0x30:
2013 /* wrmsr */
2014 msr_data = (u32)c->regs[VCPU_REGS_RAX]
2015 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
2016 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
2017 if (rc) {
2018 kvm_inject_gp(ctxt->vcpu, 0);
2019 c->eip = kvm_rip_read(ctxt->vcpu);
2020 }
2021 rc = X86EMUL_CONTINUE;
2022 c->dst.type = OP_NONE;
2023 break;
2024 case 0x32:
2025 /* rdmsr */
2026 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2027 if (rc) {
2028 kvm_inject_gp(ctxt->vcpu, 0);
2029 c->eip = kvm_rip_read(ctxt->vcpu);
2030 } else {
2031 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2032 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2033 }
2034 rc = X86EMUL_CONTINUE;
2035 c->dst.type = OP_NONE;
2036 break;
2037 case 0x40 ... 0x4f: /* cmov */
2038 c->dst.val = c->dst.orig_val = c->src.val;
2039 if (!test_cc(c->b, ctxt->eflags))
2040 c->dst.type = OP_NONE; /* no writeback */
2041 break;
2042 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
2043 long int rel;
2044
2045 switch (c->op_bytes) {
2046 case 2:
2047 rel = insn_fetch(s16, 2, c->eip);
2048 break;
2049 case 4:
2050 rel = insn_fetch(s32, 4, c->eip);
2051 break;
2052 case 8:
2053 rel = insn_fetch(s64, 8, c->eip);
2054 break;
2055 default:
2056 DPRINTF("jnz: Invalid op_bytes\n");
2057 goto cannot_emulate;
2058 }
2059 if (test_cc(c->b, ctxt->eflags))
2060 jmp_rel(c, rel);
2061 c->dst.type = OP_NONE;
2062 break;
2063 }
2064 case 0xa3:
2065 bt: /* bt */
2066 c->dst.type = OP_NONE;
2067 /* only subword offset */
2068 c->src.val &= (c->dst.bytes << 3) - 1;
2069 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
2070 break;
2071 case 0xa4: /* shld imm8, r, r/m */
2072 case 0xa5: /* shld cl, r, r/m */
2073 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2074 break;
2075 case 0xab:
2076 bts: /* bts */
2077 /* only subword offset */
2078 c->src.val &= (c->dst.bytes << 3) - 1;
2079 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
2080 break;
2081 case 0xac: /* shrd imm8, r, r/m */
2082 case 0xad: /* shrd cl, r, r/m */
2083 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2084 break;
2085 case 0xae: /* clflush */
2086 break;
2087 case 0xb0 ... 0xb1: /* cmpxchg */
2088 /*
2089 * Save real source value, then compare EAX against
2090 * destination.
2091 */
2092 c->src.orig_val = c->src.val;
2093 c->src.val = c->regs[VCPU_REGS_RAX];
2094 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2095 if (ctxt->eflags & EFLG_ZF) {
2096 /* Success: write back to memory. */
2097 c->dst.val = c->src.orig_val;
2098 } else {
2099 /* Failure: write the value we saw to EAX. */
2100 c->dst.type = OP_REG;
2101 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2102 }
2103 break;
2104 case 0xb3:
2105 btr: /* btr */
2106 /* only subword offset */
2107 c->src.val &= (c->dst.bytes << 3) - 1;
2108 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
2109 break;
2110 case 0xb6 ... 0xb7: /* movzx */
2111 c->dst.bytes = c->op_bytes;
2112 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2113 : (u16) c->src.val;
2114 break;
2115 case 0xba: /* Grp8 */
2116 switch (c->modrm_reg & 3) {
2117 case 0:
2118 goto bt;
2119 case 1:
2120 goto bts;
2121 case 2:
2122 goto btr;
2123 case 3:
2124 goto btc;
2125 }
2126 break;
2127 case 0xbb:
2128 btc: /* btc */
2129 /* only subword offset */
2130 c->src.val &= (c->dst.bytes << 3) - 1;
2131 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
2132 break;
2133 case 0xbe ... 0xbf: /* movsx */
2134 c->dst.bytes = c->op_bytes;
2135 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2136 (s16) c->src.val;
2137 break;
2138 case 0xc3: /* movnti */
2139 c->dst.bytes = c->op_bytes;
2140 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2141 (u64) c->src.val;
2142 break;
2143 case 0xc7: /* Grp9 (cmpxchg8b) */
2144 rc = emulate_grp9(ctxt, ops, memop);
2145 if (rc != 0)
2146 goto done;
2147 c->dst.type = OP_NONE;
2148 break;
2149 }
2150 goto writeback;
2151
2152 cannot_emulate:
2153 DPRINTF("Cannot emulate %02x\n", c->b);
2154 c->eip = saved_eip;
2155 return -1;
2156 }
linux 2.6 git repository for openrd