2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <asm/delay.h>
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <net/net_namespace.h>
42 #include "cxio_resource.h"
44 #include "cxgb3_offload.h"
47 static LIST_HEAD(rdev_list
);
48 static cxio_hal_ev_callback_func_t cxio_ev_cb
= NULL
;
50 static struct cxio_rdev
*cxio_hal_find_rdev_by_name(char *dev_name
)
52 struct cxio_rdev
*rdev
;
54 list_for_each_entry(rdev
, &rdev_list
, entry
)
55 if (!strcmp(rdev
->dev_name
, dev_name
))
60 static struct cxio_rdev
*cxio_hal_find_rdev_by_t3cdev(struct t3cdev
*tdev
)
62 struct cxio_rdev
*rdev
;
64 list_for_each_entry(rdev
, &rdev_list
, entry
)
65 if (rdev
->t3cdev_p
== tdev
)
70 int cxio_hal_cq_op(struct cxio_rdev
*rdev_p
, struct t3_cq
*cq
,
71 enum t3_cq_opcode op
, u32 credit
)
77 struct rdma_cq_op setup
;
79 setup
.credits
= (op
== CQ_CREDIT_UPDATE
) ? credit
: 0;
81 ret
= rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, RDMA_CQ_OP
, &setup
);
83 if ((ret
< 0) || (op
== CQ_CREDIT_UPDATE
))
87 * If the rearm returned an index other than our current index,
88 * then there might be CQE's in flight (being DMA'd). We must wait
89 * here for them to complete or the consumer can miss a notification.
91 if (Q_PTR2IDX((cq
->rptr
), cq
->size_log2
) != ret
) {
97 * Keep the generation correct by bumping rptr until it
98 * matches the index returned by the rearm - 1.
100 while (Q_PTR2IDX((rptr
+1), cq
->size_log2
) != ret
)
104 * Now rptr is the index for the (last) cqe that was
105 * in-flight at the time the HW rearmed the CQ. We
106 * spin until that CQE is valid.
108 cqe
= cq
->queue
+ Q_PTR2IDX(rptr
, cq
->size_log2
);
109 while (!CQ_VLD_ENTRY(rptr
, cq
->size_log2
, cqe
)) {
113 printk(KERN_ERR
"%s: stalled rnic\n",
125 static int cxio_hal_clear_cq_ctx(struct cxio_rdev
*rdev_p
, u32 cqid
)
127 struct rdma_cq_setup setup
;
129 setup
.base_addr
= 0; /* NULL address */
130 setup
.size
= 0; /* disaable the CQ */
132 setup
.credit_thres
= 0;
134 return (rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, RDMA_CQ_SETUP
, &setup
));
137 static int cxio_hal_clear_qp_ctx(struct cxio_rdev
*rdev_p
, u32 qpid
)
140 struct t3_modify_qp_wr
*wqe
;
141 struct sk_buff
*skb
= alloc_skb(sizeof(*wqe
), GFP_KERNEL
);
143 PDBG("%s alloc_skb failed\n", __func__
);
146 wqe
= (struct t3_modify_qp_wr
*) skb_put(skb
, sizeof(*wqe
));
147 memset(wqe
, 0, sizeof(*wqe
));
148 build_fw_riwrh((struct fw_riwrh
*) wqe
, T3_WR_QP_MOD
,
149 T3_COMPLETION_FLAG
| T3_NOTIFY_FLAG
, 0, qpid
, 7,
151 wqe
->flags
= cpu_to_be32(MODQP_WRITE_EC
);
152 sge_cmd
= qpid
<< 8 | 3;
153 wqe
->sge_cmd
= cpu_to_be64(sge_cmd
);
154 skb
->priority
= CPL_PRIORITY_CONTROL
;
155 return (cxgb3_ofld_send(rdev_p
->t3cdev_p
, skb
));
158 int cxio_create_cq(struct cxio_rdev
*rdev_p
, struct t3_cq
*cq
)
160 struct rdma_cq_setup setup
;
161 int size
= (1UL << (cq
->size_log2
)) * sizeof(struct t3_cqe
);
163 cq
->cqid
= cxio_hal_get_cqid(rdev_p
->rscp
);
166 cq
->sw_queue
= kzalloc(size
, GFP_KERNEL
);
169 cq
->queue
= dma_alloc_coherent(&(rdev_p
->rnic_info
.pdev
->dev
),
170 (1UL << (cq
->size_log2
)) *
171 sizeof(struct t3_cqe
),
172 &(cq
->dma_addr
), GFP_KERNEL
);
177 pci_unmap_addr_set(cq
, mapping
, cq
->dma_addr
);
178 memset(cq
->queue
, 0, size
);
180 setup
.base_addr
= (u64
) (cq
->dma_addr
);
181 setup
.size
= 1UL << cq
->size_log2
;
182 setup
.credits
= 65535;
183 setup
.credit_thres
= 1;
184 if (rdev_p
->t3cdev_p
->type
!= T3A
)
188 return (rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, RDMA_CQ_SETUP
, &setup
));
191 int cxio_resize_cq(struct cxio_rdev
*rdev_p
, struct t3_cq
*cq
)
193 struct rdma_cq_setup setup
;
195 setup
.base_addr
= (u64
) (cq
->dma_addr
);
196 setup
.size
= 1UL << cq
->size_log2
;
197 setup
.credits
= setup
.size
;
198 setup
.credit_thres
= setup
.size
; /* TBD: overflow recovery */
200 return (rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, RDMA_CQ_SETUP
, &setup
));
203 static u32
get_qpid(struct cxio_rdev
*rdev_p
, struct cxio_ucontext
*uctx
)
205 struct cxio_qpid_list
*entry
;
209 mutex_lock(&uctx
->lock
);
210 if (!list_empty(&uctx
->qpids
)) {
211 entry
= list_entry(uctx
->qpids
.next
, struct cxio_qpid_list
,
213 list_del(&entry
->entry
);
217 qpid
= cxio_hal_get_qpid(rdev_p
->rscp
);
220 for (i
= qpid
+1; i
& rdev_p
->qpmask
; i
++) {
221 entry
= kmalloc(sizeof *entry
, GFP_KERNEL
);
225 list_add_tail(&entry
->entry
, &uctx
->qpids
);
229 mutex_unlock(&uctx
->lock
);
230 PDBG("%s qpid 0x%x\n", __func__
, qpid
);
234 static void put_qpid(struct cxio_rdev
*rdev_p
, u32 qpid
,
235 struct cxio_ucontext
*uctx
)
237 struct cxio_qpid_list
*entry
;
239 entry
= kmalloc(sizeof *entry
, GFP_KERNEL
);
242 PDBG("%s qpid 0x%x\n", __func__
, qpid
);
244 mutex_lock(&uctx
->lock
);
245 list_add_tail(&entry
->entry
, &uctx
->qpids
);
246 mutex_unlock(&uctx
->lock
);
249 void cxio_release_ucontext(struct cxio_rdev
*rdev_p
, struct cxio_ucontext
*uctx
)
251 struct list_head
*pos
, *nxt
;
252 struct cxio_qpid_list
*entry
;
254 mutex_lock(&uctx
->lock
);
255 list_for_each_safe(pos
, nxt
, &uctx
->qpids
) {
256 entry
= list_entry(pos
, struct cxio_qpid_list
, entry
);
257 list_del_init(&entry
->entry
);
258 if (!(entry
->qpid
& rdev_p
->qpmask
))
259 cxio_hal_put_qpid(rdev_p
->rscp
, entry
->qpid
);
262 mutex_unlock(&uctx
->lock
);
265 void cxio_init_ucontext(struct cxio_rdev
*rdev_p
, struct cxio_ucontext
*uctx
)
267 INIT_LIST_HEAD(&uctx
->qpids
);
268 mutex_init(&uctx
->lock
);
271 int cxio_create_qp(struct cxio_rdev
*rdev_p
, u32 kernel_domain
,
272 struct t3_wq
*wq
, struct cxio_ucontext
*uctx
)
274 int depth
= 1UL << wq
->size_log2
;
275 int rqsize
= 1UL << wq
->rq_size_log2
;
277 wq
->qpid
= get_qpid(rdev_p
, uctx
);
281 wq
->rq
= kzalloc(depth
* sizeof(struct t3_swrq
), GFP_KERNEL
);
285 wq
->rq_addr
= cxio_hal_rqtpool_alloc(rdev_p
, rqsize
);
289 wq
->sq
= kzalloc(depth
* sizeof(struct t3_swsq
), GFP_KERNEL
);
293 wq
->queue
= dma_alloc_coherent(&(rdev_p
->rnic_info
.pdev
->dev
),
294 depth
* sizeof(union t3_wr
),
295 &(wq
->dma_addr
), GFP_KERNEL
);
299 memset(wq
->queue
, 0, depth
* sizeof(union t3_wr
));
300 pci_unmap_addr_set(wq
, mapping
, wq
->dma_addr
);
301 wq
->doorbell
= (void __iomem
*)rdev_p
->rnic_info
.kdb_addr
;
303 wq
->udb
= (u64
)rdev_p
->rnic_info
.udbell_physbase
+
304 (wq
->qpid
<< rdev_p
->qpshift
);
306 PDBG("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n", __func__
,
307 wq
->qpid
, wq
->doorbell
, (unsigned long long) wq
->udb
);
312 cxio_hal_rqtpool_free(rdev_p
, wq
->rq_addr
, rqsize
);
316 put_qpid(rdev_p
, wq
->qpid
, uctx
);
320 int cxio_destroy_cq(struct cxio_rdev
*rdev_p
, struct t3_cq
*cq
)
323 err
= cxio_hal_clear_cq_ctx(rdev_p
, cq
->cqid
);
325 dma_free_coherent(&(rdev_p
->rnic_info
.pdev
->dev
),
326 (1UL << (cq
->size_log2
))
327 * sizeof(struct t3_cqe
), cq
->queue
,
328 pci_unmap_addr(cq
, mapping
));
329 cxio_hal_put_cqid(rdev_p
->rscp
, cq
->cqid
);
333 int cxio_destroy_qp(struct cxio_rdev
*rdev_p
, struct t3_wq
*wq
,
334 struct cxio_ucontext
*uctx
)
336 dma_free_coherent(&(rdev_p
->rnic_info
.pdev
->dev
),
337 (1UL << (wq
->size_log2
))
338 * sizeof(union t3_wr
), wq
->queue
,
339 pci_unmap_addr(wq
, mapping
));
341 cxio_hal_rqtpool_free(rdev_p
, wq
->rq_addr
, (1UL << wq
->rq_size_log2
));
343 put_qpid(rdev_p
, wq
->qpid
, uctx
);
347 static void insert_recv_cqe(struct t3_wq
*wq
, struct t3_cq
*cq
)
351 PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__
,
352 wq
, cq
, cq
->sw_rptr
, cq
->sw_wptr
);
353 memset(&cqe
, 0, sizeof(cqe
));
354 cqe
.header
= cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH
) |
355 V_CQE_OPCODE(T3_SEND
) |
358 V_CQE_QPID(wq
->qpid
) |
359 V_CQE_GENBIT(Q_GENBIT(cq
->sw_wptr
,
361 *(cq
->sw_queue
+ Q_PTR2IDX(cq
->sw_wptr
, cq
->size_log2
)) = cqe
;
365 int cxio_flush_rq(struct t3_wq
*wq
, struct t3_cq
*cq
, int count
)
370 PDBG("%s wq %p cq %p\n", __func__
, wq
, cq
);
373 PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__
,
374 wq
->rq_rptr
, wq
->rq_wptr
, count
);
375 ptr
= wq
->rq_rptr
+ count
;
376 while (ptr
++ != wq
->rq_wptr
) {
377 insert_recv_cqe(wq
, cq
);
383 static void insert_sq_cqe(struct t3_wq
*wq
, struct t3_cq
*cq
,
388 PDBG("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__
,
389 wq
, cq
, cq
->sw_rptr
, cq
->sw_wptr
);
390 memset(&cqe
, 0, sizeof(cqe
));
391 cqe
.header
= cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH
) |
392 V_CQE_OPCODE(sqp
->opcode
) |
395 V_CQE_QPID(wq
->qpid
) |
396 V_CQE_GENBIT(Q_GENBIT(cq
->sw_wptr
,
398 cqe
.u
.scqe
.wrid_hi
= sqp
->sq_wptr
;
400 *(cq
->sw_queue
+ Q_PTR2IDX(cq
->sw_wptr
, cq
->size_log2
)) = cqe
;
404 int cxio_flush_sq(struct t3_wq
*wq
, struct t3_cq
*cq
, int count
)
408 struct t3_swsq
*sqp
= wq
->sq
+ Q_PTR2IDX(wq
->sq_rptr
, wq
->sq_size_log2
);
410 ptr
= wq
->sq_rptr
+ count
;
411 sqp
= wq
->sq
+ Q_PTR2IDX(ptr
, wq
->sq_size_log2
);
412 while (ptr
!= wq
->sq_wptr
) {
413 insert_sq_cqe(wq
, cq
, sqp
);
415 sqp
= wq
->sq
+ Q_PTR2IDX(ptr
, wq
->sq_size_log2
);
422 * Move all CQEs from the HWCQ into the SWCQ.
424 void cxio_flush_hw_cq(struct t3_cq
*cq
)
426 struct t3_cqe
*cqe
, *swcqe
;
428 PDBG("%s cq %p cqid 0x%x\n", __func__
, cq
, cq
->cqid
);
429 cqe
= cxio_next_hw_cqe(cq
);
431 PDBG("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
432 __func__
, cq
->rptr
, cq
->sw_wptr
);
433 swcqe
= cq
->sw_queue
+ Q_PTR2IDX(cq
->sw_wptr
, cq
->size_log2
);
435 swcqe
->header
|= cpu_to_be32(V_CQE_SWCQE(1));
438 cqe
= cxio_next_hw_cqe(cq
);
442 static int cqe_completes_wr(struct t3_cqe
*cqe
, struct t3_wq
*wq
)
444 if (CQE_OPCODE(*cqe
) == T3_TERMINATE
)
447 if ((CQE_OPCODE(*cqe
) == T3_RDMA_WRITE
) && RQ_TYPE(*cqe
))
450 if ((CQE_OPCODE(*cqe
) == T3_READ_RESP
) && SQ_TYPE(*cqe
))
453 if ((CQE_OPCODE(*cqe
) == T3_SEND
) && RQ_TYPE(*cqe
) &&
454 Q_EMPTY(wq
->rq_rptr
, wq
->rq_wptr
))
460 void cxio_count_scqes(struct t3_cq
*cq
, struct t3_wq
*wq
, int *count
)
467 while (!Q_EMPTY(ptr
, cq
->sw_wptr
)) {
468 cqe
= cq
->sw_queue
+ (Q_PTR2IDX(ptr
, cq
->size_log2
));
469 if ((SQ_TYPE(*cqe
) ||
470 ((CQE_OPCODE(*cqe
) == T3_READ_RESP
) && wq
->oldest_read
)) &&
471 (CQE_QPID(*cqe
) == wq
->qpid
))
475 PDBG("%s cq %p count %d\n", __func__
, cq
, *count
);
478 void cxio_count_rcqes(struct t3_cq
*cq
, struct t3_wq
*wq
, int *count
)
484 PDBG("%s count zero %d\n", __func__
, *count
);
486 while (!Q_EMPTY(ptr
, cq
->sw_wptr
)) {
487 cqe
= cq
->sw_queue
+ (Q_PTR2IDX(ptr
, cq
->size_log2
));
488 if (RQ_TYPE(*cqe
) && (CQE_OPCODE(*cqe
) != T3_READ_RESP
) &&
489 (CQE_QPID(*cqe
) == wq
->qpid
) && cqe_completes_wr(cqe
, wq
))
493 PDBG("%s cq %p count %d\n", __func__
, cq
, *count
);
496 static int cxio_hal_init_ctrl_cq(struct cxio_rdev
*rdev_p
)
498 struct rdma_cq_setup setup
;
500 setup
.base_addr
= 0; /* NULL address */
501 setup
.size
= 1; /* enable the CQ */
504 /* force SGE to redirect to RspQ and interrupt */
505 setup
.credit_thres
= 0;
507 return (rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, RDMA_CQ_SETUP
, &setup
));
510 static int cxio_hal_init_ctrl_qp(struct cxio_rdev
*rdev_p
)
513 u64 sge_cmd
, ctx0
, ctx1
;
515 struct t3_modify_qp_wr
*wqe
;
518 skb
= alloc_skb(sizeof(*wqe
), GFP_KERNEL
);
520 PDBG("%s alloc_skb failed\n", __func__
);
523 err
= cxio_hal_init_ctrl_cq(rdev_p
);
525 PDBG("%s err %d initializing ctrl_cq\n", __func__
, err
);
528 rdev_p
->ctrl_qp
.workq
= dma_alloc_coherent(
529 &(rdev_p
->rnic_info
.pdev
->dev
),
530 (1 << T3_CTRL_QP_SIZE_LOG2
) *
532 &(rdev_p
->ctrl_qp
.dma_addr
),
534 if (!rdev_p
->ctrl_qp
.workq
) {
535 PDBG("%s dma_alloc_coherent failed\n", __func__
);
539 pci_unmap_addr_set(&rdev_p
->ctrl_qp
, mapping
,
540 rdev_p
->ctrl_qp
.dma_addr
);
541 rdev_p
->ctrl_qp
.doorbell
= (void __iomem
*)rdev_p
->rnic_info
.kdb_addr
;
542 memset(rdev_p
->ctrl_qp
.workq
, 0,
543 (1 << T3_CTRL_QP_SIZE_LOG2
) * sizeof(union t3_wr
));
545 mutex_init(&rdev_p
->ctrl_qp
.lock
);
546 init_waitqueue_head(&rdev_p
->ctrl_qp
.waitq
);
548 /* update HW Ctrl QP context */
549 base_addr
= rdev_p
->ctrl_qp
.dma_addr
;
551 ctx0
= (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2
)) |
552 V_EC_BASE_LO((u32
) base_addr
& 0xffff));
554 ctx0
|= V_EC_CREDITS(FW_WR_NUM
);
556 ctx1
= (u32
) base_addr
;
558 ctx1
|= ((u64
) (V_EC_BASE_HI((u32
) base_addr
& 0xf) | V_EC_RESPQ(0) |
559 V_EC_TYPE(0) | V_EC_GEN(1) |
560 V_EC_UP_TOKEN(T3_CTL_QP_TID
) | F_EC_VALID
)) << 32;
561 wqe
= (struct t3_modify_qp_wr
*) skb_put(skb
, sizeof(*wqe
));
562 memset(wqe
, 0, sizeof(*wqe
));
563 build_fw_riwrh((struct fw_riwrh
*) wqe
, T3_WR_QP_MOD
, 0, 0,
564 T3_CTL_QP_TID
, 7, T3_SOPEOP
);
565 wqe
->flags
= cpu_to_be32(MODQP_WRITE_EC
);
566 sge_cmd
= (3ULL << 56) | FW_RI_SGEEC_START
<< 8 | 3;
567 wqe
->sge_cmd
= cpu_to_be64(sge_cmd
);
568 wqe
->ctx1
= cpu_to_be64(ctx1
);
569 wqe
->ctx0
= cpu_to_be64(ctx0
);
570 PDBG("CtrlQP dma_addr 0x%llx workq %p size %d\n",
571 (unsigned long long) rdev_p
->ctrl_qp
.dma_addr
,
572 rdev_p
->ctrl_qp
.workq
, 1 << T3_CTRL_QP_SIZE_LOG2
);
573 skb
->priority
= CPL_PRIORITY_CONTROL
;
574 return (cxgb3_ofld_send(rdev_p
->t3cdev_p
, skb
));
580 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev
*rdev_p
)
582 dma_free_coherent(&(rdev_p
->rnic_info
.pdev
->dev
),
583 (1UL << T3_CTRL_QP_SIZE_LOG2
)
584 * sizeof(union t3_wr
), rdev_p
->ctrl_qp
.workq
,
585 pci_unmap_addr(&rdev_p
->ctrl_qp
, mapping
));
586 return cxio_hal_clear_qp_ctx(rdev_p
, T3_CTRL_QP_ID
);
589 /* write len bytes of data into addr (32B aligned address)
590 * If data is NULL, clear len byte of memory to zero.
591 * caller aquires the ctrl_qp lock before the call
593 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev
*rdev_p
, u32 addr
,
596 u32 i
, nr_wqe
, copy_len
;
598 u8 wr_len
, utx_len
; /* length in 8 byte flit */
599 enum t3_wr_flags flag
;
603 nr_wqe
= len
% 96 ? len
/ 96 + 1 : len
/ 96; /* 96B max per WQE */
604 PDBG("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
605 __func__
, rdev_p
->ctrl_qp
.wptr
, rdev_p
->ctrl_qp
.rptr
, len
,
607 utx_len
= 3; /* in 32B unit */
608 for (i
= 0; i
< nr_wqe
; i
++) {
609 if (Q_FULL(rdev_p
->ctrl_qp
.rptr
, rdev_p
->ctrl_qp
.wptr
,
610 T3_CTRL_QP_SIZE_LOG2
)) {
611 PDBG("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, "
612 "wait for more space i %d\n", __func__
,
613 rdev_p
->ctrl_qp
.wptr
, rdev_p
->ctrl_qp
.rptr
, i
);
614 if (wait_event_interruptible(rdev_p
->ctrl_qp
.waitq
,
615 !Q_FULL(rdev_p
->ctrl_qp
.rptr
,
616 rdev_p
->ctrl_qp
.wptr
,
617 T3_CTRL_QP_SIZE_LOG2
))) {
618 PDBG("%s ctrl_qp workq interrupted\n",
622 PDBG("%s ctrl_qp wakeup, continue posting work request "
623 "i %d\n", __func__
, i
);
625 wqe
= (__be64
*)(rdev_p
->ctrl_qp
.workq
+ (rdev_p
->ctrl_qp
.wptr
%
626 (1 << T3_CTRL_QP_SIZE_LOG2
)));
628 if (i
== (nr_wqe
- 1)) {
630 flag
= T3_COMPLETION_FLAG
;
632 utx_len
= len
/ 32 + 1;
638 * Force a CQE to return the credit to the workq in case
639 * we posted more than half the max QP size of WRs
642 (i
% (((1 << T3_CTRL_QP_SIZE_LOG2
)) >> 1) == 0)) {
643 flag
= T3_COMPLETION_FLAG
;
644 PDBG("%s force completion at i %d\n", __func__
, i
);
647 /* build the utx mem command */
648 wqe
+= (sizeof(struct t3_bypass_wr
) >> 3);
649 utx_cmd
= (T3_UTX_MEM_WRITE
<< 28) | (addr
+ i
* 3);
651 utx_cmd
|= (utx_len
<< 28) | ((utx_len
<< 2) + 1);
652 *wqe
= cpu_to_be64(utx_cmd
);
654 copy_data
= (u8
*) data
+ i
* 96;
655 copy_len
= len
> 96 ? 96 : len
;
657 /* clear memory content if data is NULL */
659 memcpy(wqe
, copy_data
, copy_len
);
661 memset(wqe
, 0, copy_len
);
663 memset(((u8
*) wqe
) + copy_len
, 0,
664 32 - (copy_len
% 32));
665 wr_len
= ((sizeof(struct t3_bypass_wr
)) >> 3) + 1 +
667 wqe
= (__be64
*)(rdev_p
->ctrl_qp
.workq
+ (rdev_p
->ctrl_qp
.wptr
%
668 (1 << T3_CTRL_QP_SIZE_LOG2
)));
670 /* wptr in the WRID[31:0] */
671 ((union t3_wrid
*)(wqe
+1))->id0
.low
= rdev_p
->ctrl_qp
.wptr
;
674 * This must be the last write with a memory barrier
677 build_fw_riwrh((struct fw_riwrh
*) wqe
, T3_WR_BP
, flag
,
678 Q_GENBIT(rdev_p
->ctrl_qp
.wptr
,
679 T3_CTRL_QP_SIZE_LOG2
), T3_CTRL_QP_ID
,
681 if (flag
== T3_COMPLETION_FLAG
)
682 ring_doorbell(rdev_p
->ctrl_qp
.doorbell
, T3_CTRL_QP_ID
);
684 rdev_p
->ctrl_qp
.wptr
++;
689 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
691 * TBD: shared memory region support
693 static int __cxio_tpt_op(struct cxio_rdev
*rdev_p
, u32 reset_tpt_entry
,
694 u32
*stag
, u8 stag_state
, u32 pdid
,
695 enum tpt_mem_type type
, enum tpt_mem_perm perm
,
696 u32 zbva
, u64 to
, u32 len
, u8 page_size
,
697 u32 pbl_size
, u32 pbl_addr
)
700 struct tpt_entry tpt
;
707 stag_state
= stag_state
> 0;
708 stag_idx
= (*stag
) >> 8;
710 if ((!reset_tpt_entry
) && !(*stag
!= T3_STAG_UNSET
)) {
711 stag_idx
= cxio_hal_get_stag(rdev_p
->rscp
);
714 *stag
= (stag_idx
<< 8) | ((*stag
) & 0xFF);
716 PDBG("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
717 __func__
, stag_state
, type
, pdid
, stag_idx
);
719 mutex_lock(&rdev_p
->ctrl_qp
.lock
);
721 /* write TPT entry */
723 memset(&tpt
, 0, sizeof(tpt
));
725 tpt
.valid_stag_pdid
= cpu_to_be32(F_TPT_VALID
|
726 V_TPT_STAG_KEY((*stag
) & M_TPT_STAG_KEY
) |
727 V_TPT_STAG_STATE(stag_state
) |
728 V_TPT_STAG_TYPE(type
) | V_TPT_PDID(pdid
));
729 BUG_ON(page_size
>= 28);
730 tpt
.flags_pagesize_qpid
= cpu_to_be32(V_TPT_PERM(perm
) |
731 ((perm
& TPT_MW_BIND
) ? F_TPT_MW_BIND_ENABLE
: 0) |
732 V_TPT_ADDR_TYPE((zbva
? TPT_ZBTO
: TPT_VATO
)) |
733 V_TPT_PAGE_SIZE(page_size
));
734 tpt
.rsvd_pbl_addr
= reset_tpt_entry
? 0 :
735 cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p
, pbl_addr
)>>3));
736 tpt
.len
= cpu_to_be32(len
);
737 tpt
.va_hi
= cpu_to_be32((u32
) (to
>> 32));
738 tpt
.va_low_or_fbo
= cpu_to_be32((u32
) (to
& 0xFFFFFFFFULL
));
739 tpt
.rsvd_bind_cnt_or_pstag
= 0;
740 tpt
.rsvd_pbl_size
= reset_tpt_entry
? 0 :
741 cpu_to_be32(V_TPT_PBL_SIZE(pbl_size
>> 2));
743 err
= cxio_hal_ctrl_qp_write_mem(rdev_p
,
745 (rdev_p
->rnic_info
.tpt_base
>> 5),
748 /* release the stag index to free pool */
750 cxio_hal_put_stag(rdev_p
->rscp
, stag_idx
);
752 wptr
= rdev_p
->ctrl_qp
.wptr
;
753 mutex_unlock(&rdev_p
->ctrl_qp
.lock
);
755 if (wait_event_interruptible(rdev_p
->ctrl_qp
.waitq
,
756 SEQ32_GE(rdev_p
->ctrl_qp
.rptr
,
762 int cxio_write_pbl(struct cxio_rdev
*rdev_p
, __be64
*pbl
,
763 u32 pbl_addr
, u32 pbl_size
)
768 PDBG("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
769 __func__
, pbl_addr
, rdev_p
->rnic_info
.pbl_base
,
772 mutex_lock(&rdev_p
->ctrl_qp
.lock
);
773 err
= cxio_hal_ctrl_qp_write_mem(rdev_p
, pbl_addr
>> 5, pbl_size
<< 3,
775 wptr
= rdev_p
->ctrl_qp
.wptr
;
776 mutex_unlock(&rdev_p
->ctrl_qp
.lock
);
780 if (wait_event_interruptible(rdev_p
->ctrl_qp
.waitq
,
781 SEQ32_GE(rdev_p
->ctrl_qp
.rptr
,
788 int cxio_register_phys_mem(struct cxio_rdev
*rdev_p
, u32
*stag
, u32 pdid
,
789 enum tpt_mem_perm perm
, u32 zbva
, u64 to
, u32 len
,
790 u8 page_size
, u32 pbl_size
, u32 pbl_addr
)
792 *stag
= T3_STAG_UNSET
;
793 return __cxio_tpt_op(rdev_p
, 0, stag
, 1, pdid
, TPT_NON_SHARED_MR
, perm
,
794 zbva
, to
, len
, page_size
, pbl_size
, pbl_addr
);
797 int cxio_reregister_phys_mem(struct cxio_rdev
*rdev_p
, u32
*stag
, u32 pdid
,
798 enum tpt_mem_perm perm
, u32 zbva
, u64 to
, u32 len
,
799 u8 page_size
, u32 pbl_size
, u32 pbl_addr
)
801 return __cxio_tpt_op(rdev_p
, 0, stag
, 1, pdid
, TPT_NON_SHARED_MR
, perm
,
802 zbva
, to
, len
, page_size
, pbl_size
, pbl_addr
);
805 int cxio_dereg_mem(struct cxio_rdev
*rdev_p
, u32 stag
, u32 pbl_size
,
808 return __cxio_tpt_op(rdev_p
, 1, &stag
, 0, 0, 0, 0, 0, 0ULL, 0, 0,
812 int cxio_allocate_window(struct cxio_rdev
*rdev_p
, u32
* stag
, u32 pdid
)
814 *stag
= T3_STAG_UNSET
;
815 return __cxio_tpt_op(rdev_p
, 0, stag
, 0, pdid
, TPT_MW
, 0, 0, 0ULL, 0, 0,
819 int cxio_deallocate_window(struct cxio_rdev
*rdev_p
, u32 stag
)
821 return __cxio_tpt_op(rdev_p
, 1, &stag
, 0, 0, 0, 0, 0, 0ULL, 0, 0,
825 int cxio_allocate_stag(struct cxio_rdev
*rdev_p
, u32
*stag
, u32 pdid
, u32 pbl_size
, u32 pbl_addr
)
827 *stag
= T3_STAG_UNSET
;
828 return __cxio_tpt_op(rdev_p
, 0, stag
, 0, pdid
, TPT_NON_SHARED_MR
,
829 0, 0, 0ULL, 0, 0, pbl_size
, pbl_addr
);
832 int cxio_rdma_init(struct cxio_rdev
*rdev_p
, struct t3_rdma_init_attr
*attr
)
834 struct t3_rdma_init_wr
*wqe
;
835 struct sk_buff
*skb
= alloc_skb(sizeof(*wqe
), GFP_ATOMIC
);
838 PDBG("%s rdev_p %p\n", __func__
, rdev_p
);
839 wqe
= (struct t3_rdma_init_wr
*) __skb_put(skb
, sizeof(*wqe
));
840 wqe
->wrh
.op_seop_flags
= cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT
));
841 wqe
->wrh
.gen_tid_len
= cpu_to_be32(V_FW_RIWR_TID(attr
->tid
) |
842 V_FW_RIWR_LEN(sizeof(*wqe
) >> 3));
844 wqe
->qpid
= cpu_to_be32(attr
->qpid
);
845 wqe
->pdid
= cpu_to_be32(attr
->pdid
);
846 wqe
->scqid
= cpu_to_be32(attr
->scqid
);
847 wqe
->rcqid
= cpu_to_be32(attr
->rcqid
);
848 wqe
->rq_addr
= cpu_to_be32(attr
->rq_addr
- rdev_p
->rnic_info
.rqt_base
);
849 wqe
->rq_size
= cpu_to_be32(attr
->rq_size
);
850 wqe
->mpaattrs
= attr
->mpaattrs
;
851 wqe
->qpcaps
= attr
->qpcaps
;
852 wqe
->ulpdu_size
= cpu_to_be16(attr
->tcp_emss
);
853 wqe
->rqe_count
= cpu_to_be16(attr
->rqe_count
);
854 wqe
->flags_rtr_type
= cpu_to_be16(attr
->flags
|V_RTR_TYPE(attr
->rtr_type
));
855 wqe
->ord
= cpu_to_be32(attr
->ord
);
856 wqe
->ird
= cpu_to_be32(attr
->ird
);
857 wqe
->qp_dma_addr
= cpu_to_be64(attr
->qp_dma_addr
);
858 wqe
->qp_dma_size
= cpu_to_be32(attr
->qp_dma_size
);
859 wqe
->irs
= cpu_to_be32(attr
->irs
);
860 skb
->priority
= 0; /* 0=>ToeQ; 1=>CtrlQ */
861 return (cxgb3_ofld_send(rdev_p
->t3cdev_p
, skb
));
864 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb
)
869 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb
)
874 static int cxio_hal_ev_handler(struct t3cdev
*t3cdev_p
, struct sk_buff
*skb
)
877 struct cxio_rdev
*rdev_p
= NULL
;
878 struct respQ_msg_t
*rsp_msg
= (struct respQ_msg_t
*) skb
->data
;
879 PDBG("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x"
880 " se %0x notify %0x cqbranch %0x creditth %0x\n",
881 cnt
, __func__
, RSPQ_CQID(rsp_msg
), RSPQ_CQPTR(rsp_msg
),
882 RSPQ_GENBIT(rsp_msg
), RSPQ_OVERFLOW(rsp_msg
), RSPQ_AN(rsp_msg
),
883 RSPQ_SE(rsp_msg
), RSPQ_NOTIFY(rsp_msg
), RSPQ_CQBRANCH(rsp_msg
),
884 RSPQ_CREDIT_THRESH(rsp_msg
));
885 PDBG("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d "
886 "len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
887 CQE_QPID(rsp_msg
->cqe
), CQE_GENBIT(rsp_msg
->cqe
),
888 CQE_TYPE(rsp_msg
->cqe
), CQE_STATUS(rsp_msg
->cqe
),
889 CQE_OPCODE(rsp_msg
->cqe
), CQE_LEN(rsp_msg
->cqe
),
890 CQE_WRID_HI(rsp_msg
->cqe
), CQE_WRID_LOW(rsp_msg
->cqe
));
891 rdev_p
= (struct cxio_rdev
*)t3cdev_p
->ulp
;
893 PDBG("%s called by t3cdev %p with null ulp\n", __func__
,
897 if (CQE_QPID(rsp_msg
->cqe
) == T3_CTRL_QP_ID
) {
898 rdev_p
->ctrl_qp
.rptr
= CQE_WRID_LOW(rsp_msg
->cqe
) + 1;
899 wake_up_interruptible(&rdev_p
->ctrl_qp
.waitq
);
900 dev_kfree_skb_irq(skb
);
901 } else if (CQE_QPID(rsp_msg
->cqe
) == 0xfff8)
902 dev_kfree_skb_irq(skb
);
904 (*cxio_ev_cb
) (rdev_p
, skb
);
906 dev_kfree_skb_irq(skb
);
911 /* Caller takes care of locking if needed */
912 int cxio_rdev_open(struct cxio_rdev
*rdev_p
)
914 struct net_device
*netdev_p
= NULL
;
916 if (strlen(rdev_p
->dev_name
)) {
917 if (cxio_hal_find_rdev_by_name(rdev_p
->dev_name
)) {
920 netdev_p
= dev_get_by_name(&init_net
, rdev_p
->dev_name
);
925 } else if (rdev_p
->t3cdev_p
) {
926 if (cxio_hal_find_rdev_by_t3cdev(rdev_p
->t3cdev_p
)) {
929 netdev_p
= rdev_p
->t3cdev_p
->lldev
;
930 strncpy(rdev_p
->dev_name
, rdev_p
->t3cdev_p
->name
,
931 T3_MAX_DEV_NAME_LEN
);
933 PDBG("%s t3cdev_p or dev_name must be set\n", __func__
);
937 list_add_tail(&rdev_p
->entry
, &rdev_list
);
939 PDBG("%s opening rnic dev %s\n", __func__
, rdev_p
->dev_name
);
940 memset(&rdev_p
->ctrl_qp
, 0, sizeof(rdev_p
->ctrl_qp
));
941 if (!rdev_p
->t3cdev_p
)
942 rdev_p
->t3cdev_p
= dev2t3cdev(netdev_p
);
943 rdev_p
->t3cdev_p
->ulp
= (void *) rdev_p
;
944 err
= rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, RDMA_GET_PARAMS
,
945 &(rdev_p
->rnic_info
));
947 printk(KERN_ERR
"%s t3cdev_p(%p)->ctl returned error %d.\n",
948 __func__
, rdev_p
->t3cdev_p
, err
);
951 err
= rdev_p
->t3cdev_p
->ctl(rdev_p
->t3cdev_p
, GET_PORTS
,
952 &(rdev_p
->port_info
));
954 printk(KERN_ERR
"%s t3cdev_p(%p)->ctl returned error %d.\n",
955 __func__
, rdev_p
->t3cdev_p
, err
);
960 * qpshift is the number of bits to shift the qpid left in order
961 * to get the correct address of the doorbell for that qp.
963 cxio_init_ucontext(rdev_p
, &rdev_p
->uctx
);
964 rdev_p
->qpshift
= PAGE_SHIFT
-
966 ilog2(rdev_p
->rnic_info
.udbell_len
>>
968 rdev_p
->qpnr
= rdev_p
->rnic_info
.udbell_len
>> PAGE_SHIFT
;
969 rdev_p
->qpmask
= (65536 >> ilog2(rdev_p
->qpnr
)) - 1;
970 PDBG("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d "
971 "pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
972 __func__
, rdev_p
->dev_name
, rdev_p
->rnic_info
.tpt_base
,
973 rdev_p
->rnic_info
.tpt_top
, cxio_num_stags(rdev_p
),
974 rdev_p
->rnic_info
.pbl_base
,
975 rdev_p
->rnic_info
.pbl_top
, rdev_p
->rnic_info
.rqt_base
,
976 rdev_p
->rnic_info
.rqt_top
);
977 PDBG("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu "
978 "qpnr %d qpmask 0x%x\n",
979 rdev_p
->rnic_info
.udbell_len
,
980 rdev_p
->rnic_info
.udbell_physbase
, rdev_p
->rnic_info
.kdb_addr
,
981 rdev_p
->qpshift
, rdev_p
->qpnr
, rdev_p
->qpmask
);
983 err
= cxio_hal_init_ctrl_qp(rdev_p
);
985 printk(KERN_ERR
"%s error %d initializing ctrl_qp.\n",
989 err
= cxio_hal_init_resource(rdev_p
, cxio_num_stags(rdev_p
), 0,
990 0, T3_MAX_NUM_QP
, T3_MAX_NUM_CQ
,
993 printk(KERN_ERR
"%s error %d initializing hal resources.\n",
997 err
= cxio_hal_pblpool_create(rdev_p
);
999 printk(KERN_ERR
"%s error %d initializing pbl mem pool.\n",
1003 err
= cxio_hal_rqtpool_create(rdev_p
);
1005 printk(KERN_ERR
"%s error %d initializing rqt mem pool.\n",
1011 cxio_hal_pblpool_destroy(rdev_p
);
1013 cxio_hal_destroy_resource(rdev_p
->rscp
);
1015 cxio_hal_destroy_ctrl_qp(rdev_p
);
1017 list_del(&rdev_p
->entry
);
1021 void cxio_rdev_close(struct cxio_rdev
*rdev_p
)
1024 cxio_hal_pblpool_destroy(rdev_p
);
1025 cxio_hal_rqtpool_destroy(rdev_p
);
1026 list_del(&rdev_p
->entry
);
1027 rdev_p
->t3cdev_p
->ulp
= NULL
;
1028 cxio_hal_destroy_ctrl_qp(rdev_p
);
1029 cxio_hal_destroy_resource(rdev_p
->rscp
);
1033 int __init
cxio_hal_init(void)
1035 if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI
))
1037 t3_register_cpl_handler(CPL_ASYNC_NOTIF
, cxio_hal_ev_handler
);
1041 void __exit
cxio_hal_exit(void)
1043 struct cxio_rdev
*rdev
, *tmp
;
1045 t3_register_cpl_handler(CPL_ASYNC_NOTIF
, NULL
);
1046 list_for_each_entry_safe(rdev
, tmp
, &rdev_list
, entry
)
1047 cxio_rdev_close(rdev
);
1048 cxio_hal_destroy_rhdl_resource();
1051 static void flush_completed_wrs(struct t3_wq
*wq
, struct t3_cq
*cq
)
1053 struct t3_swsq
*sqp
;
1054 __u32 ptr
= wq
->sq_rptr
;
1055 int count
= Q_COUNT(wq
->sq_rptr
, wq
->sq_wptr
);
1057 sqp
= wq
->sq
+ Q_PTR2IDX(ptr
, wq
->sq_size_log2
);
1059 if (!sqp
->signaled
) {
1061 sqp
= wq
->sq
+ Q_PTR2IDX(ptr
, wq
->sq_size_log2
);
1062 } else if (sqp
->complete
) {
1065 * Insert this completed cqe into the swcq.
1067 PDBG("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1068 __func__
, Q_PTR2IDX(ptr
, wq
->sq_size_log2
),
1069 Q_PTR2IDX(cq
->sw_wptr
, cq
->size_log2
));
1070 sqp
->cqe
.header
|= htonl(V_CQE_SWCQE(1));
1071 *(cq
->sw_queue
+ Q_PTR2IDX(cq
->sw_wptr
, cq
->size_log2
))
1080 static void create_read_req_cqe(struct t3_wq
*wq
, struct t3_cqe
*hw_cqe
,
1081 struct t3_cqe
*read_cqe
)
1083 read_cqe
->u
.scqe
.wrid_hi
= wq
->oldest_read
->sq_wptr
;
1084 read_cqe
->len
= wq
->oldest_read
->read_len
;
1085 read_cqe
->header
= htonl(V_CQE_QPID(CQE_QPID(*hw_cqe
)) |
1086 V_CQE_SWCQE(SW_CQE(*hw_cqe
)) |
1087 V_CQE_OPCODE(T3_READ_REQ
) |
1092 * Return a ptr to the next read wr in the SWSQ or NULL.
1094 static void advance_oldest_read(struct t3_wq
*wq
)
1097 u32 rptr
= wq
->oldest_read
- wq
->sq
+ 1;
1098 u32 wptr
= Q_PTR2IDX(wq
->sq_wptr
, wq
->sq_size_log2
);
1100 while (Q_PTR2IDX(rptr
, wq
->sq_size_log2
) != wptr
) {
1101 wq
->oldest_read
= wq
->sq
+ Q_PTR2IDX(rptr
, wq
->sq_size_log2
);
1103 if (wq
->oldest_read
->opcode
== T3_READ_REQ
)
1107 wq
->oldest_read
= NULL
;
1114 * check the validity of the first CQE,
1115 * supply the wq assicated with the qpid.
1117 * credit: cq credit to return to sge.
1118 * cqe_flushed: 1 iff the CQE is flushed.
1119 * cqe: copy of the polled CQE.
1123 * -1 CQE skipped, try again.
1125 int cxio_poll_cq(struct t3_wq
*wq
, struct t3_cq
*cq
, struct t3_cqe
*cqe
,
1126 u8
*cqe_flushed
, u64
*cookie
, u32
*credit
)
1129 struct t3_cqe
*hw_cqe
, read_cqe
;
1133 hw_cqe
= cxio_next_cqe(cq
);
1135 PDBG("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x"
1136 " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1137 __func__
, CQE_OOO(*hw_cqe
), CQE_QPID(*hw_cqe
),
1138 CQE_GENBIT(*hw_cqe
), CQE_TYPE(*hw_cqe
), CQE_STATUS(*hw_cqe
),
1139 CQE_OPCODE(*hw_cqe
), CQE_LEN(*hw_cqe
), CQE_WRID_HI(*hw_cqe
),
1140 CQE_WRID_LOW(*hw_cqe
));
1143 * skip cqe's not affiliated with a QP.
1151 * Gotta tweak READ completions:
1152 * 1) the cqe doesn't contain the sq_wptr from the wr.
1153 * 2) opcode not reflected from the wr.
1154 * 3) read_len not reflected from the wr.
1155 * 4) cq_type is RQ_TYPE not SQ_TYPE.
1157 if (RQ_TYPE(*hw_cqe
) && (CQE_OPCODE(*hw_cqe
) == T3_READ_RESP
)) {
1160 * If this is an unsolicited read response, then the read
1161 * was generated by the kernel driver as part of peer-2-peer
1162 * connection setup. So ignore the completion.
1164 if (!wq
->oldest_read
) {
1165 if (CQE_STATUS(*hw_cqe
))
1172 * Don't write to the HWCQ, so create a new read req CQE
1175 create_read_req_cqe(wq
, hw_cqe
, &read_cqe
);
1177 advance_oldest_read(wq
);
1181 * T3A: Discard TERMINATE CQEs.
1183 if (CQE_OPCODE(*hw_cqe
) == T3_TERMINATE
) {
1189 if (CQE_STATUS(*hw_cqe
) || wq
->error
) {
1190 *cqe_flushed
= wq
->error
;
1194 * T3A inserts errors into the CQE. We cannot return
1195 * these as work completions.
1197 /* incoming write failures */
1198 if ((CQE_OPCODE(*hw_cqe
) == T3_RDMA_WRITE
)
1199 && RQ_TYPE(*hw_cqe
)) {
1203 /* incoming read request failures */
1204 if ((CQE_OPCODE(*hw_cqe
) == T3_READ_RESP
) && SQ_TYPE(*hw_cqe
)) {
1209 /* incoming SEND with no receive posted failures */
1210 if ((CQE_OPCODE(*hw_cqe
) == T3_SEND
) && RQ_TYPE(*hw_cqe
) &&
1211 Q_EMPTY(wq
->rq_rptr
, wq
->rq_wptr
)) {
1221 if (RQ_TYPE(*hw_cqe
)) {
1224 * HW only validates 4 bits of MSN. So we must validate that
1225 * the MSN in the SEND is the next expected MSN. If its not,
1226 * then we complete this with TPT_ERR_MSN and mark the wq in
1229 if (unlikely((CQE_WRID_MSN(*hw_cqe
) != (wq
->rq_rptr
+ 1)))) {
1231 hw_cqe
->header
|= htonl(V_CQE_STATUS(TPT_ERR_MSN
));
1238 * If we get here its a send completion.
1240 * Handle out of order completion. These get stuffed
1241 * in the SW SQ. Then the SW SQ is walked to move any
1242 * now in-order completions into the SW CQ. This handles
1244 * 1) reaping unsignaled WRs when the first subsequent
1245 * signaled WR is completed.
1246 * 2) out of order read completions.
1248 if (!SW_CQE(*hw_cqe
) && (CQE_WRID_SQ_WPTR(*hw_cqe
) != wq
->sq_rptr
)) {
1249 struct t3_swsq
*sqp
;
1251 PDBG("%s out of order completion going in swsq at idx %ld\n",
1253 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe
), wq
->sq_size_log2
));
1255 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe
), wq
->sq_size_log2
);
1266 * Reap the associated WR(s) that are freed up with this
1269 if (SQ_TYPE(*hw_cqe
)) {
1270 wq
->sq_rptr
= CQE_WRID_SQ_WPTR(*hw_cqe
);
1271 PDBG("%s completing sq idx %ld\n", __func__
,
1272 Q_PTR2IDX(wq
->sq_rptr
, wq
->sq_size_log2
));
1273 *cookie
= wq
->sq
[Q_PTR2IDX(wq
->sq_rptr
, wq
->sq_size_log2
)].wr_id
;
1276 PDBG("%s completing rq idx %ld\n", __func__
,
1277 Q_PTR2IDX(wq
->rq_rptr
, wq
->rq_size_log2
));
1278 *cookie
= wq
->rq
[Q_PTR2IDX(wq
->rq_rptr
, wq
->rq_size_log2
)].wr_id
;
1279 if (wq
->rq
[Q_PTR2IDX(wq
->rq_rptr
, wq
->rq_size_log2
)].pbl_addr
)
1280 cxio_hal_pblpool_free(wq
->rdev
,
1281 wq
->rq
[Q_PTR2IDX(wq
->rq_rptr
,
1282 wq
->rq_size_log2
)].pbl_addr
, T3_STAG0_PBL_SIZE
);
1288 * Flush any completed cqes that are now in-order.
1290 flush_completed_wrs(wq
, cq
);
1293 if (SW_CQE(*hw_cqe
)) {
1294 PDBG("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1295 __func__
, cq
, cq
->cqid
, cq
->sw_rptr
);
1298 PDBG("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1299 __func__
, cq
, cq
->cqid
, cq
->rptr
);
1303 * T3A: compute credits.
1305 if (((cq
->rptr
- cq
->wptr
) > (1 << (cq
->size_log2
- 1)))
1306 || ((cq
->rptr
- cq
->wptr
) >= 128)) {
1307 *credit
= cq
->rptr
- cq
->wptr
;
1308 cq
->wptr
= cq
->rptr
;