arch/x86/kernel/cpu/mcheck/mce_intel_64.c

   1 /*
   2  * Intel specific MCE features.
   3  * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
   4  * Copyright (C) 2008, 2009 Intel Corporation
   5  * Author: Andi Kleen
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/percpu.h>
  11 #include <asm/processor.h>
  12 #include <asm/apic.h>
  13 #include <asm/msr.h>
  14 #include <asm/mce.h>
  15 #include <asm/hw_irq.h>
  16 #include <asm/idle.h>
  17 #include <asm/therm_throt.h>
  18 #include <asm/apic.h>
  19
  20 #include "mce.h"
  21
  22 asmlinkage void smp_thermal_interrupt(void)
  23 {
  24         __u64 msr_val;
  25
  26         ack_APIC_irq();
  27
  28         exit_idle();
  29         irq_enter();
  30
  31         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  32         if (therm_throt_process(msr_val & 1))
  33                 mce_log_therm_throt_event(msr_val);
  34
  35         inc_irq_stat(irq_thermal_count);
  36         irq_exit();
  37 }
  38
  39 /*
  40  * Support for Intel Correct Machine Check Interrupts. This allows
  41  * the CPU to raise an interrupt when a corrected machine check happened.
  42  * Normally we pick those up using a regular polling timer.
  43  * Also supports reliable discovery of shared banks.
  44  */
  45
  46 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  47
  48 /*
  49  * cmci_discover_lock protects against parallel discovery attempts
  50  * which could race against each other.
  51  */
  52 static DEFINE_SPINLOCK(cmci_discover_lock);
  53
  54 #define CMCI_THRESHOLD 1
  55
  56 static int cmci_supported(int *banks)
  57 {
  58         u64 cap;
  59
  60         /*
  61          * Vendor check is not strictly needed, but the initial
  62          * initialization is vendor keyed and this
  63          * makes sure none of the backdoors are entered otherwise.
  64          */
  65         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  66                 return 0;
  67         if (!cpu_has_apic || lapic_get_maxlvt() < 6)
  68                 return 0;
  69         rdmsrl(MSR_IA32_MCG_CAP, cap);
  70         *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
  71         return !!(cap & MCG_CMCI_P);
  72 }
  73
  74 /*
  75  * The interrupt handler. This is called on every event.
  76  * Just call the poller directly to log any events.
  77  * This could in theory increase the threshold under high load,
  78  * but doesn't for now.
  79  */
  80 static void intel_threshold_interrupt(void)
  81 {
  82         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
  83         mce_notify_user();
  84 }
  85
  86 static void print_update(char *type, int *hdr, int num)
  87 {
  88         if (*hdr == 0)
  89                 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
  90         *hdr = 1;
  91         printk(KERN_CONT " %s:%d", type, num);
  92 }
  93
  94 /*
  95  * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
  96  * on this CPU. Use the algorithm recommended in the SDM to discover shared
  97  * banks.
  98  */
  99 static void cmci_discover(int banks, int boot)
 100 {
 101         unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
 102         unsigned long flags;
 103         int hdr = 0;
 104         int i;
 105
 106         spin_lock_irqsave(&cmci_discover_lock, flags);
 107         for (i = 0; i < banks; i++) {
 108                 u64 val;
 109
 110                 if (test_bit(i, owned))
 111                         continue;
 112
 113                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 114
 115                 /* Already owned by someone else? */
 116                 if (val & CMCI_EN) {
 117                         if (test_and_clear_bit(i, owned) || boot)
 118                                 print_update("SHD", &hdr, i);
 119                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 120                         continue;
 121                 }
 122
 123                 val |= CMCI_EN | CMCI_THRESHOLD;
 124                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 125                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 126
 127                 /* Did the enable bit stick? -- the bank supports CMCI */
 128                 if (val & CMCI_EN) {
 129                         if (!test_and_set_bit(i, owned) || boot)
 130                                 print_update("CMCI", &hdr, i);
 131                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 132                 } else {
 133                         WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
 134                 }
 135         }
 136         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 137         if (hdr)
 138                 printk(KERN_CONT "\n");
 139 }
 140
 141 /*
 142  * Just in case we missed an event during initialization check
 143  * all the CMCI owned banks.
 144  */
 145 void cmci_recheck(void)
 146 {
 147         unsigned long flags;
 148         int banks;
 149
 150         if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
 151                 return;
 152         local_irq_save(flags);
 153         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
 154         local_irq_restore(flags);
 155 }
 156
 157 /*
 158  * Disable CMCI on this CPU for all banks it owns when it goes down.
 159  * This allows other CPUs to claim the banks on rediscovery.
 160  */
 161 void cmci_clear(void)
 162 {
 163         unsigned long flags;
 164         int i;
 165         int banks;
 166         u64 val;
 167
 168         if (!cmci_supported(&banks))
 169                 return;
 170         spin_lock_irqsave(&cmci_discover_lock, flags);
 171         for (i = 0; i < banks; i++) {
 172                 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
 173                         continue;
 174                 /* Disable CMCI */
 175                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 176                 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
 177                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 178                 __clear_bit(i, __get_cpu_var(mce_banks_owned));
 179         }
 180         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 181 }
 182
 183 /*
 184  * After a CPU went down cycle through all the others and rediscover
 185  * Must run in process context.
 186  */
 187 void cmci_rediscover(int dying)
 188 {
 189         int banks;
 190         int cpu;
 191         cpumask_var_t old;
 192
 193         if (!cmci_supported(&banks))
 194                 return;
 195         if (!alloc_cpumask_var(&old, GFP_KERNEL))
 196                 return;
 197         cpumask_copy(old, &current->cpus_allowed);
 198
 199         for_each_online_cpu (cpu) {
 200                 if (cpu == dying)
 201                         continue;
 202                 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
 203                         continue;
 204                 /* Recheck banks in case CPUs don't all have the same */
 205                 if (cmci_supported(&banks))
 206                         cmci_discover(banks, 0);
 207         }
 208
 209         set_cpus_allowed_ptr(current, old);
 210         free_cpumask_var(old);
 211 }
 212
 213 /*
 214  * Reenable CMCI on this CPU in case a CPU down failed.
 215  */
 216 void cmci_reenable(void)
 217 {
 218         int banks;
 219         if (cmci_supported(&banks))
 220                 cmci_discover(banks, 0);
 221 }
 222
 223 static void intel_init_cmci(void)
 224 {
 225         int banks;
 226
 227         if (!cmci_supported(&banks))
 228                 return;
 229
 230         mce_threshold_vector = intel_threshold_interrupt;
 231         cmci_discover(banks, 1);
 232         /*
 233          * For CPU #0 this runs with still disabled APIC, but that's
 234          * ok because only the vector is set up. We still do another
 235          * check for the banks later for CPU #0 just to make sure
 236          * to not miss any events.
 237          */
 238         apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
 239         cmci_recheck();
 240 }
 241
 242 void mce_intel_feature_init(struct cpuinfo_x86 *c)
 243 {
 244         intel_init_thermal(c);
 245         intel_init_cmci();
 246 }