include/drm/drm_edid.h

   1 /*
   2  * Copyright © 2007-2008 Intel Corporation
   3  *   Jesse Barnes <jesse.barnes@intel.com>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #ifndef __DRM_EDID_H__
  24 #define __DRM_EDID_H__
  25
  26 #include <linux/types.h>
  27
  28 #define EDID_LENGTH 128
  29 #define DDC_ADDR 0x50
  30
  31 struct est_timings {
  32         u8 t1;
  33         u8 t2;
  34         u8 mfg_rsvd;
  35 } __attribute__((packed));
  36
  37 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
  38 #define EDID_TIMING_ASPECT_SHIFT 6
  39 #define EDID_TIMING_ASPECT_MASK  (0x3 << EDID_TIMING_ASPECT_SHIFT)
  40
  41 /* need to add 60 */
  42 #define EDID_TIMING_VFREQ_SHIFT  0
  43 #define EDID_TIMING_VFREQ_MASK   (0x3f << EDID_TIMING_VFREQ_SHIFT)
  44
  45 struct std_timing {
  46         u8 hsize; /* need to multiply by 8 then add 248 */
  47         u8 vfreq_aspect;
  48 } __attribute__((packed));
  49
  50 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
  51 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
  52 #define DRM_EDID_PT_SEPARATE_SYNC  (3 << 3)
  53 #define DRM_EDID_PT_STEREO         (1 << 5)
  54 #define DRM_EDID_PT_INTERLACED     (1 << 7)
  55
  56 /* If detailed data is pixel timing */
  57 struct detailed_pixel_timing {
  58         u8 hactive_lo;
  59         u8 hblank_lo;
  60         u8 hactive_hblank_hi;
  61         u8 vactive_lo;
  62         u8 vblank_lo;
  63         u8 vactive_vblank_hi;
  64         u8 hsync_offset_lo;
  65         u8 hsync_pulse_width_lo;
  66         u8 vsync_offset_pulse_width_lo;
  67         u8 hsync_vsync_offset_pulse_width_hi;
  68         u8 width_mm_lo;
  69         u8 height_mm_lo;
  70         u8 width_height_mm_hi;
  71         u8 hborder;
  72         u8 vborder;
  73         u8 misc;
  74 } __attribute__((packed));
  75
  76 /* If it's not pixel timing, it'll be one of the below */
  77 struct detailed_data_string {
  78         u8 str[13];
  79 } __attribute__((packed));
  80
  81 struct detailed_data_monitor_range {
  82         u8 min_vfreq;
  83         u8 max_vfreq;
  84         u8 min_hfreq_khz;
  85         u8 max_hfreq_khz;
  86         u8 pixel_clock_mhz; /* need to multiply by 10 */
  87         __le16 sec_gtf_toggle; /* A000=use above, 20=use below */
  88         u8 hfreq_start_khz; /* need to multiply by 2 */
  89         u8 c; /* need to divide by 2 */
  90         __le16 m;
  91         u8 k;
  92         u8 j; /* need to divide by 2 */
  93 } __attribute__((packed));
  94
  95 struct detailed_data_wpindex {
  96         u8 white_yx_lo; /* Lower 2 bits each */
  97         u8 white_x_hi;
  98         u8 white_y_hi;
  99         u8 gamma; /* need to divide by 100 then add 1 */
 100 } __attribute__((packed));
 101
 102 struct detailed_data_color_point {
 103         u8 windex1;
 104         u8 wpindex1[3];
 105         u8 windex2;
 106         u8 wpindex2[3];
 107 } __attribute__((packed));
 108
 109 struct cvt_timing {
 110         u8 code[3];
 111 } __attribute__((packed));
 112
 113 struct detailed_non_pixel {
 114         u8 pad1;
 115         u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
 116                     fb=color point data, fa=standard timing data,
 117                     f9=undefined, f8=mfg. reserved */
 118         u8 pad2;
 119         union {
 120                 struct detailed_data_string str;
 121                 struct detailed_data_monitor_range range;
 122                 struct detailed_data_wpindex color;
 123                 struct std_timing timings[5];
 124                 struct cvt_timing cvt[4];
 125         } data;
 126 } __attribute__((packed));
 127
 128 #define EDID_DETAIL_EST_TIMINGS 0xf7
 129 #define EDID_DETAIL_CVT_3BYTE 0xf8
 130 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
 131 #define EDID_DETAIL_STD_MODES 0xfa
 132 #define EDID_DETAIL_MONITOR_CPDATA 0xfb
 133 #define EDID_DETAIL_MONITOR_NAME 0xfc
 134 #define EDID_DETAIL_MONITOR_RANGE 0xfd
 135 #define EDID_DETAIL_MONITOR_STRING 0xfe
 136 #define EDID_DETAIL_MONITOR_SERIAL 0xff
 137
 138 struct detailed_timing {
 139         __le16 pixel_clock; /* need to multiply by 10 KHz */
 140         union {
 141                 struct detailed_pixel_timing pixel_data;
 142                 struct detailed_non_pixel other_data;
 143         } data;
 144 } __attribute__((packed));
 145
 146 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
 147 #define DRM_EDID_INPUT_SYNC_ON_GREEN   (1 << 1)
 148 #define DRM_EDID_INPUT_COMPOSITE_SYNC  (1 << 2)
 149 #define DRM_EDID_INPUT_SEPARATE_SYNCS  (1 << 3)
 150 #define DRM_EDID_INPUT_BLANK_TO_BLACK  (1 << 4)
 151 #define DRM_EDID_INPUT_VIDEO_LEVEL     (3 << 5)
 152 #define DRM_EDID_INPUT_DIGITAL         (1 << 7) /* bits below must be zero if set */
 153
 154 #define DRM_EDID_FEATURE_DEFAULT_GTF      (1 << 0)
 155 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
 156 #define DRM_EDID_FEATURE_STANDARD_COLOR   (1 << 2)
 157 #define DRM_EDID_FEATURE_DISPLAY_TYPE     (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
 158 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF    (1 << 5)
 159 #define DRM_EDID_FEATURE_PM_SUSPEND       (1 << 6)
 160 #define DRM_EDID_FEATURE_PM_STANDBY       (1 << 7)
 161
 162 struct edid {
 163         u8 header[8];
 164         /* Vendor & product info */
 165         u8 mfg_id[2];
 166         u8 prod_code[2];
 167         u32 serial; /* FIXME: byte order */
 168         u8 mfg_week;
 169         u8 mfg_year;
 170         /* EDID version */
 171         u8 version;
 172         u8 revision;
 173         /* Display info: */
 174         u8 input;
 175         u8 width_cm;
 176         u8 height_cm;
 177         u8 gamma;
 178         u8 features;
 179         /* Color characteristics */
 180         u8 red_green_lo;
 181         u8 black_white_lo;
 182         u8 red_x;
 183         u8 red_y;
 184         u8 green_x;
 185         u8 green_y;
 186         u8 blue_x;
 187         u8 blue_y;
 188         u8 white_x;
 189         u8 white_y;
 190         /* Est. timings and mfg rsvd timings*/
 191         struct est_timings established_timings;
 192         /* Standard timings 1-8*/
 193         struct std_timing standard_timings[8];
 194         /* Detailing timings 1-4 */
 195         struct detailed_timing detailed_timings[4];
 196         /* Number of 128 byte ext. blocks */
 197         u8 extensions;
 198         /* Checksum */
 199         u8 checksum;
 200 } __attribute__((packed));
 201
 202 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
 203
 204 #endif /* __DRM_EDID_H__ */