drivers/usb/otg/twl4030-usb.c

   1 /*
   2  * twl4030_usb - TWL4030 USB transceiver, talking to OMAP OTG controller
   3  *
   4  * Copyright (C) 2004-2007 Texas Instruments
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Contact: Felipe Balbi <felipe.balbi@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  *
  22  * Current status:
  23  *      - HS USB ULPI mode works.
  24  *      - 3-pin mode support may be added in future.
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/spinlock.h>
  32 #include <linux/workqueue.h>
  33 #include <linux/io.h>
  34 #include <linux/delay.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/i2c/twl.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/err.h>
  39
  40
  41 /* Register defines */
  42
  43 #define VENDOR_ID_LO                    0x00
  44 #define VENDOR_ID_HI                    0x01
  45 #define PRODUCT_ID_LO                   0x02
  46 #define PRODUCT_ID_HI                   0x03
  47
  48 #define FUNC_CTRL                       0x04
  49 #define FUNC_CTRL_SET                   0x05
  50 #define FUNC_CTRL_CLR                   0x06
  51 #define FUNC_CTRL_SUSPENDM              (1 << 6)
  52 #define FUNC_CTRL_RESET                 (1 << 5)
  53 #define FUNC_CTRL_OPMODE_MASK           (3 << 3) /* bits 3 and 4 */
  54 #define FUNC_CTRL_OPMODE_NORMAL         (0 << 3)
  55 #define FUNC_CTRL_OPMODE_NONDRIVING     (1 << 3)
  56 #define FUNC_CTRL_OPMODE_DISABLE_BIT_NRZI       (2 << 3)
  57 #define FUNC_CTRL_TERMSELECT            (1 << 2)
  58 #define FUNC_CTRL_XCVRSELECT_MASK       (3 << 0) /* bits 0 and 1 */
  59 #define FUNC_CTRL_XCVRSELECT_HS         (0 << 0)
  60 #define FUNC_CTRL_XCVRSELECT_FS         (1 << 0)
  61 #define FUNC_CTRL_XCVRSELECT_LS         (2 << 0)
  62 #define FUNC_CTRL_XCVRSELECT_FS4LS      (3 << 0)
  63
  64 #define IFC_CTRL                        0x07
  65 #define IFC_CTRL_SET                    0x08
  66 #define IFC_CTRL_CLR                    0x09
  67 #define IFC_CTRL_INTERFACE_PROTECT_DISABLE      (1 << 7)
  68 #define IFC_CTRL_AUTORESUME             (1 << 4)
  69 #define IFC_CTRL_CLOCKSUSPENDM          (1 << 3)
  70 #define IFC_CTRL_CARKITMODE             (1 << 2)
  71 #define IFC_CTRL_FSLSSERIALMODE_3PIN    (1 << 1)
  72
  73 #define TWL4030_OTG_CTRL                0x0A
  74 #define TWL4030_OTG_CTRL_SET            0x0B
  75 #define TWL4030_OTG_CTRL_CLR            0x0C
  76 #define TWL4030_OTG_CTRL_DRVVBUS        (1 << 5)
  77 #define TWL4030_OTG_CTRL_CHRGVBUS       (1 << 4)
  78 #define TWL4030_OTG_CTRL_DISCHRGVBUS    (1 << 3)
  79 #define TWL4030_OTG_CTRL_DMPULLDOWN     (1 << 2)
  80 #define TWL4030_OTG_CTRL_DPPULLDOWN     (1 << 1)
  81 #define TWL4030_OTG_CTRL_IDPULLUP       (1 << 0)
  82
  83 #define USB_INT_EN_RISE                 0x0D
  84 #define USB_INT_EN_RISE_SET             0x0E
  85 #define USB_INT_EN_RISE_CLR             0x0F
  86 #define USB_INT_EN_FALL                 0x10
  87 #define USB_INT_EN_FALL_SET             0x11
  88 #define USB_INT_EN_FALL_CLR             0x12
  89 #define USB_INT_STS                     0x13
  90 #define USB_INT_LATCH                   0x14
  91 #define USB_INT_IDGND                   (1 << 4)
  92 #define USB_INT_SESSEND                 (1 << 3)
  93 #define USB_INT_SESSVALID               (1 << 2)
  94 #define USB_INT_VBUSVALID               (1 << 1)
  95 #define USB_INT_HOSTDISCONNECT          (1 << 0)
  96
  97 #define CARKIT_CTRL                     0x19
  98 #define CARKIT_CTRL_SET                 0x1A
  99 #define CARKIT_CTRL_CLR                 0x1B
 100 #define CARKIT_CTRL_MICEN               (1 << 6)
 101 #define CARKIT_CTRL_SPKRIGHTEN          (1 << 5)
 102 #define CARKIT_CTRL_SPKLEFTEN           (1 << 4)
 103 #define CARKIT_CTRL_RXDEN               (1 << 3)
 104 #define CARKIT_CTRL_TXDEN               (1 << 2)
 105 #define CARKIT_CTRL_IDGNDDRV            (1 << 1)
 106 #define CARKIT_CTRL_CARKITPWR           (1 << 0)
 107 #define CARKIT_PLS_CTRL                 0x22
 108 #define CARKIT_PLS_CTRL_SET             0x23
 109 #define CARKIT_PLS_CTRL_CLR             0x24
 110 #define CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN        (1 << 3)
 111 #define CARKIT_PLS_CTRL_SPKRLEFT_BIASEN (1 << 2)
 112 #define CARKIT_PLS_CTRL_RXPLSEN         (1 << 1)
 113 #define CARKIT_PLS_CTRL_TXPLSEN         (1 << 0)
 114
 115 #define MCPC_CTRL                       0x30
 116 #define MCPC_CTRL_SET                   0x31
 117 #define MCPC_CTRL_CLR                   0x32
 118 #define MCPC_CTRL_RTSOL                 (1 << 7)
 119 #define MCPC_CTRL_EXTSWR                (1 << 6)
 120 #define MCPC_CTRL_EXTSWC                (1 << 5)
 121 #define MCPC_CTRL_VOICESW               (1 << 4)
 122 #define MCPC_CTRL_OUT64K                (1 << 3)
 123 #define MCPC_CTRL_RTSCTSSW              (1 << 2)
 124 #define MCPC_CTRL_HS_UART               (1 << 0)
 125
 126 #define MCPC_IO_CTRL                    0x33
 127 #define MCPC_IO_CTRL_SET                0x34
 128 #define MCPC_IO_CTRL_CLR                0x35
 129 #define MCPC_IO_CTRL_MICBIASEN          (1 << 5)
 130 #define MCPC_IO_CTRL_CTS_NPU            (1 << 4)
 131 #define MCPC_IO_CTRL_RXD_PU             (1 << 3)
 132 #define MCPC_IO_CTRL_TXDTYP             (1 << 2)
 133 #define MCPC_IO_CTRL_CTSTYP             (1 << 1)
 134 #define MCPC_IO_CTRL_RTSTYP             (1 << 0)
 135
 136 #define MCPC_CTRL2                      0x36
 137 #define MCPC_CTRL2_SET                  0x37
 138 #define MCPC_CTRL2_CLR                  0x38
 139 #define MCPC_CTRL2_MCPC_CK_EN           (1 << 0)
 140
 141 #define OTHER_FUNC_CTRL                 0x80
 142 #define OTHER_FUNC_CTRL_SET             0x81
 143 #define OTHER_FUNC_CTRL_CLR             0x82
 144 #define OTHER_FUNC_CTRL_BDIS_ACON_EN    (1 << 4)
 145 #define OTHER_FUNC_CTRL_FIVEWIRE_MODE   (1 << 2)
 146
 147 #define OTHER_IFC_CTRL                  0x83
 148 #define OTHER_IFC_CTRL_SET              0x84
 149 #define OTHER_IFC_CTRL_CLR              0x85
 150 #define OTHER_IFC_CTRL_OE_INT_EN        (1 << 6)
 151 #define OTHER_IFC_CTRL_CEA2011_MODE     (1 << 5)
 152 #define OTHER_IFC_CTRL_FSLSSERIALMODE_4PIN      (1 << 4)
 153 #define OTHER_IFC_CTRL_HIZ_ULPI_60MHZ_OUT       (1 << 3)
 154 #define OTHER_IFC_CTRL_HIZ_ULPI         (1 << 2)
 155 #define OTHER_IFC_CTRL_ALT_INT_REROUTE  (1 << 0)
 156
 157 #define OTHER_INT_EN_RISE               0x86
 158 #define OTHER_INT_EN_RISE_SET           0x87
 159 #define OTHER_INT_EN_RISE_CLR           0x88
 160 #define OTHER_INT_EN_FALL               0x89
 161 #define OTHER_INT_EN_FALL_SET           0x8A
 162 #define OTHER_INT_EN_FALL_CLR           0x8B
 163 #define OTHER_INT_STS                   0x8C
 164 #define OTHER_INT_LATCH                 0x8D
 165 #define OTHER_INT_VB_SESS_VLD           (1 << 7)
 166 #define OTHER_INT_DM_HI                 (1 << 6) /* not valid for "latch" reg */
 167 #define OTHER_INT_DP_HI                 (1 << 5) /* not valid for "latch" reg */
 168 #define OTHER_INT_BDIS_ACON             (1 << 3) /* not valid for "fall" regs */
 169 #define OTHER_INT_MANU                  (1 << 1)
 170 #define OTHER_INT_ABNORMAL_STRESS       (1 << 0)
 171
 172 #define ID_STATUS                       0x96
 173 #define ID_RES_FLOAT                    (1 << 4)
 174 #define ID_RES_440K                     (1 << 3)
 175 #define ID_RES_200K                     (1 << 2)
 176 #define ID_RES_102K                     (1 << 1)
 177 #define ID_RES_GND                      (1 << 0)
 178
 179 #define POWER_CTRL                      0xAC
 180 #define POWER_CTRL_SET                  0xAD
 181 #define POWER_CTRL_CLR                  0xAE
 182 #define POWER_CTRL_OTG_ENAB             (1 << 5)
 183
 184 #define OTHER_IFC_CTRL2                 0xAF
 185 #define OTHER_IFC_CTRL2_SET             0xB0
 186 #define OTHER_IFC_CTRL2_CLR             0xB1
 187 #define OTHER_IFC_CTRL2_ULPI_STP_LOW    (1 << 4)
 188 #define OTHER_IFC_CTRL2_ULPI_TXEN_POL   (1 << 3)
 189 #define OTHER_IFC_CTRL2_ULPI_4PIN_2430  (1 << 2)
 190 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_MASK     (3 << 0) /* bits 0 and 1 */
 191 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT1N    (0 << 0)
 192 #define OTHER_IFC_CTRL2_USB_INT_OUTSEL_INT2N    (1 << 0)
 193
 194 #define REG_CTRL_EN                     0xB2
 195 #define REG_CTRL_EN_SET                 0xB3
 196 #define REG_CTRL_EN_CLR                 0xB4
 197 #define REG_CTRL_ERROR                  0xB5
 198 #define ULPI_I2C_CONFLICT_INTEN         (1 << 0)
 199
 200 #define OTHER_FUNC_CTRL2                0xB8
 201 #define OTHER_FUNC_CTRL2_SET            0xB9
 202 #define OTHER_FUNC_CTRL2_CLR            0xBA
 203 #define OTHER_FUNC_CTRL2_VBAT_TIMER_EN  (1 << 0)
 204
 205 /* following registers do not have separate _clr and _set registers */
 206 #define VBUS_DEBOUNCE                   0xC0
 207 #define ID_DEBOUNCE                     0xC1
 208 #define VBAT_TIMER                      0xD3
 209 #define PHY_PWR_CTRL                    0xFD
 210 #define PHY_PWR_PHYPWD                  (1 << 0)
 211 #define PHY_CLK_CTRL                    0xFE
 212 #define PHY_CLK_CTRL_CLOCKGATING_EN     (1 << 2)
 213 #define PHY_CLK_CTRL_CLK32K_EN          (1 << 1)
 214 #define REQ_PHY_DPLL_CLK                (1 << 0)
 215 #define PHY_CLK_CTRL_STS                0xFF
 216 #define PHY_DPLL_CLK                    (1 << 0)
 217
 218 /* In module TWL4030_MODULE_PM_MASTER */
 219 #define PROTECT_KEY                     0x0E
 220 #define STS_HW_CONDITIONS               0x0F
 221
 222 /* In module TWL4030_MODULE_PM_RECEIVER */
 223 #define VUSB_DEDICATED1                 0x7D
 224 #define VUSB_DEDICATED2                 0x7E
 225 #define VUSB1V5_DEV_GRP                 0x71
 226 #define VUSB1V5_TYPE                    0x72
 227 #define VUSB1V5_REMAP                   0x73
 228 #define VUSB1V8_DEV_GRP                 0x74
 229 #define VUSB1V8_TYPE                    0x75
 230 #define VUSB1V8_REMAP                   0x76
 231 #define VUSB3V1_DEV_GRP                 0x77
 232 #define VUSB3V1_TYPE                    0x78
 233 #define VUSB3V1_REMAP                   0x79
 234
 235 /* In module TWL4030_MODULE_INTBR */
 236 #define PMBR1                           0x0D
 237 #define GPIO_USB_4PIN_ULPI_2430C        (3 << 0)
 238
 239
 240
 241 enum linkstat {
 242         USB_LINK_UNKNOWN = 0,
 243         USB_LINK_NONE,
 244         USB_LINK_VBUS,
 245         USB_LINK_ID,
 246 };
 247
 248 struct twl4030_usb {
 249         struct otg_transceiver  otg;
 250         struct device           *dev;
 251
 252         /* TWL4030 internal USB regulator supplies */
 253         struct regulator        *usb1v5;
 254         struct regulator        *usb1v8;
 255         struct regulator        *usb3v1;
 256
 257         /* for vbus reporting with irqs disabled */
 258         spinlock_t              lock;
 259
 260         /* pin configuration */
 261         enum twl4030_usb_mode   usb_mode;
 262
 263         int                     irq;
 264         u8                      linkstat;
 265         u8                      asleep;
 266         bool                    irq_enabled;
 267 };
 268
 269 /* internal define on top of container_of */
 270 #define xceiv_to_twl(x)         container_of((x), struct twl4030_usb, otg);
 271
 272 /*-------------------------------------------------------------------------*/
 273
 274 static int twl4030_i2c_write_u8_verify(struct twl4030_usb *twl,
 275                 u8 module, u8 data, u8 address)
 276 {
 277         u8 check;
 278
 279         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 280             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 281                                                 (check == data))
 282                 return 0;
 283         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 284                         1, module, address, check, data);
 285
 286         /* Failed once: Try again */
 287         if ((twl_i2c_write_u8(module, data, address) >= 0) &&
 288             (twl_i2c_read_u8(module, &check, address) >= 0) &&
 289                                                 (check == data))
 290                 return 0;
 291         dev_dbg(twl->dev, "Write%d[%d,0x%x] wrote %02x but read %02x\n",
 292                         2, module, address, check, data);
 293
 294         /* Failed again: Return error */
 295         return -EBUSY;
 296 }
 297
 298 #define twl4030_usb_write_verify(twl, address, data)    \
 299         twl4030_i2c_write_u8_verify(twl, TWL4030_MODULE_USB, (data), (address))
 300
 301 static inline int twl4030_usb_write(struct twl4030_usb *twl,
 302                 u8 address, u8 data)
 303 {
 304         int ret = 0;
 305
 306         ret = twl_i2c_write_u8(TWL4030_MODULE_USB, data, address);
 307         if (ret < 0)
 308                 dev_dbg(twl->dev,
 309                         "TWL4030:USB:Write[0x%x] Error %d\n", address, ret);
 310         return ret;
 311 }
 312
 313 static inline int twl4030_readb(struct twl4030_usb *twl, u8 module, u8 address)
 314 {
 315         u8 data;
 316         int ret = 0;
 317
 318         ret = twl_i2c_read_u8(module, &data, address);
 319         if (ret >= 0)
 320                 ret = data;
 321         else
 322                 dev_dbg(twl->dev,
 323                         "TWL4030:readb[0x%x,0x%x] Error %d\n",
 324                                         module, address, ret);
 325
 326         return ret;
 327 }
 328
 329 static inline int twl4030_usb_read(struct twl4030_usb *twl, u8 address)
 330 {
 331         return twl4030_readb(twl, TWL4030_MODULE_USB, address);
 332 }
 333
 334 /*-------------------------------------------------------------------------*/
 335
 336 static inline int
 337 twl4030_usb_set_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 338 {
 339         return twl4030_usb_write(twl, reg + 1, bits);
 340 }
 341
 342 static inline int
 343 twl4030_usb_clear_bits(struct twl4030_usb *twl, u8 reg, u8 bits)
 344 {
 345         return twl4030_usb_write(twl, reg + 2, bits);
 346 }
 347
 348 /*-------------------------------------------------------------------------*/
 349
 350 static enum linkstat twl4030_usb_linkstat(struct twl4030_usb *twl)
 351 {
 352         int     status;
 353         int     linkstat = USB_LINK_UNKNOWN;
 354
 355         /*
 356          * For ID/VBUS sensing, see manual section 15.4.8 ...
 357          * except when using only battery backup power, two
 358          * comparators produce VBUS_PRES and ID_PRES signals,
 359          * which don't match docs elsewhere.  But ... BIT(7)
 360          * and BIT(2) of STS_HW_CONDITIONS, respectively, do
 361          * seem to match up.  If either is true the USB_PRES
 362          * signal is active, the OTG module is activated, and
 363          * its interrupt may be raised (may wake the system).
 364          */
 365         status = twl4030_readb(twl, TWL4030_MODULE_PM_MASTER,
 366                         STS_HW_CONDITIONS);
 367         if (status < 0)
 368                 dev_err(twl->dev, "USB link status err %d\n", status);
 369         else if (status & (BIT(7) | BIT(2))) {
 370                 if (status & BIT(2))
 371                         linkstat = USB_LINK_ID;
 372                 else
 373                         linkstat = USB_LINK_VBUS;
 374         } else
 375                 linkstat = USB_LINK_NONE;
 376
 377         dev_dbg(twl->dev, "HW_CONDITIONS 0x%02x/%d; link %d\n",
 378                         status, status, linkstat);
 379
 380         /* REVISIT this assumes host and peripheral controllers
 381          * are registered, and that both are active...
 382          */
 383
 384         spin_lock_irq(&twl->lock);
 385         twl->linkstat = linkstat;
 386         if (linkstat == USB_LINK_ID) {
 387                 twl->otg.default_a = true;
 388                 twl->otg.state = OTG_STATE_A_IDLE;
 389         } else {
 390                 twl->otg.default_a = false;
 391                 twl->otg.state = OTG_STATE_B_IDLE;
 392         }
 393         spin_unlock_irq(&twl->lock);
 394
 395         return linkstat;
 396 }
 397
 398 static void twl4030_usb_set_mode(struct twl4030_usb *twl, int mode)
 399 {
 400         twl->usb_mode = mode;
 401
 402         switch (mode) {
 403         case T2_USB_MODE_ULPI:
 404                 twl4030_usb_clear_bits(twl, IFC_CTRL, IFC_CTRL_CARKITMODE);
 405                 twl4030_usb_set_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 406                 twl4030_usb_clear_bits(twl, FUNC_CTRL,
 407                                         FUNC_CTRL_XCVRSELECT_MASK |
 408                                         FUNC_CTRL_OPMODE_MASK);
 409                 break;
 410         case -1:
 411                 /* FIXME: power on defaults */
 412                 break;
 413         default:
 414                 dev_err(twl->dev, "unsupported T2 transceiver mode %d\n",
 415                                 mode);
 416                 break;
 417         };
 418 }
 419
 420 static void twl4030_i2c_access(struct twl4030_usb *twl, int on)
 421 {
 422         unsigned long timeout;
 423         int val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 424
 425         if (val >= 0) {
 426                 if (on) {
 427                         /* enable DPLL to access PHY registers over I2C */
 428                         val |= REQ_PHY_DPLL_CLK;
 429                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 430                                                 (u8)val) < 0);
 431
 432                         timeout = jiffies + HZ;
 433                         while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 434                                                         PHY_DPLL_CLK)
 435                                 && time_before(jiffies, timeout))
 436                                         udelay(10);
 437                         if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) &
 438                                                         PHY_DPLL_CLK))
 439                                 dev_err(twl->dev, "Timeout setting T2 HSUSB "
 440                                                 "PHY DPLL clock\n");
 441                 } else {
 442                         /* let ULPI control the DPLL clock */
 443                         val &= ~REQ_PHY_DPLL_CLK;
 444                         WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL,
 445                                                 (u8)val) < 0);
 446                 }
 447         }
 448 }
 449
 450 static void twl4030_phy_power(struct twl4030_usb *twl, int on)
 451 {
 452         u8 pwr;
 453
 454         pwr = twl4030_usb_read(twl, PHY_PWR_CTRL);
 455         if (on) {
 456                 regulator_enable(twl->usb3v1);
 457                 regulator_enable(twl->usb1v8);
 458                 /*
 459                  * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP
 460                  * in twl4030) resets the VUSB_DEDICATED2 register. This reset
 461                  * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to
 462                  * SLEEP. We work around this by clearing the bit after usv3v1
 463                  * is re-activated. This ensures that VUSB3V1 is really active.
 464                  */
 465                 twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0,
 466                                                         VUSB_DEDICATED2);
 467                 regulator_enable(twl->usb1v5);
 468                 pwr &= ~PHY_PWR_PHYPWD;
 469                 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 470                 twl4030_usb_write(twl, PHY_CLK_CTRL,
 471                                   twl4030_usb_read(twl, PHY_CLK_CTRL) |
 472                                         (PHY_CLK_CTRL_CLOCKGATING_EN |
 473                                                 PHY_CLK_CTRL_CLK32K_EN));
 474         } else  {
 475                 pwr |= PHY_PWR_PHYPWD;
 476                 WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0);
 477                 regulator_disable(twl->usb1v5);
 478                 regulator_disable(twl->usb1v8);
 479                 regulator_disable(twl->usb3v1);
 480         }
 481 }
 482
 483 static void twl4030_phy_suspend(struct twl4030_usb *twl, int controller_off)
 484 {
 485         if (twl->asleep)
 486                 return;
 487
 488         twl4030_phy_power(twl, 0);
 489         twl->asleep = 1;
 490 }
 491
 492 static void twl4030_phy_resume(struct twl4030_usb *twl)
 493 {
 494         if (!twl->asleep)
 495                 return;
 496
 497         twl4030_phy_power(twl, 1);
 498         twl4030_i2c_access(twl, 1);
 499         twl4030_usb_set_mode(twl, twl->usb_mode);
 500         if (twl->usb_mode == T2_USB_MODE_ULPI)
 501                 twl4030_i2c_access(twl, 0);
 502         twl->asleep = 0;
 503 }
 504
 505 static int twl4030_usb_ldo_init(struct twl4030_usb *twl)
 506 {
 507         /* Enable writing to power configuration registers */
 508         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0xC0, PROTECT_KEY);
 509         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0x0C, PROTECT_KEY);
 510
 511         /* put VUSB3V1 LDO in active state */
 512         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2);
 513
 514         /* input to VUSB3V1 LDO is from VBAT, not VBUS */
 515         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x14, VUSB_DEDICATED1);
 516
 517         /* Initialize 3.1V regulator */
 518         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_DEV_GRP);
 519
 520         twl->usb3v1 = regulator_get(twl->dev, "usb3v1");
 521         if (IS_ERR(twl->usb3v1))
 522                 return -ENODEV;
 523
 524         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB3V1_TYPE);
 525
 526         /* Initialize 1.5V regulator */
 527         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_DEV_GRP);
 528
 529         twl->usb1v5 = regulator_get(twl->dev, "usb1v5");
 530         if (IS_ERR(twl->usb1v5))
 531                 goto fail1;
 532
 533         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V5_TYPE);
 534
 535         /* Initialize 1.8V regulator */
 536         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_DEV_GRP);
 537
 538         twl->usb1v8 = regulator_get(twl->dev, "usb1v8");
 539         if (IS_ERR(twl->usb1v8))
 540                 goto fail2;
 541
 542         twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB1V8_TYPE);
 543
 544         /* disable access to power configuration registers */
 545         twl_i2c_write_u8(TWL4030_MODULE_PM_MASTER, 0, PROTECT_KEY);
 546
 547         return 0;
 548
 549 fail2:
 550         regulator_put(twl->usb1v5);
 551         twl->usb1v5 = NULL;
 552 fail1:
 553         regulator_put(twl->usb3v1);
 554         twl->usb3v1 = NULL;
 555         return -ENODEV;
 556 }
 557
 558 static ssize_t twl4030_usb_vbus_show(struct device *dev,
 559                 struct device_attribute *attr, char *buf)
 560 {
 561         struct twl4030_usb *twl = dev_get_drvdata(dev);
 562         unsigned long flags;
 563         int ret = -EINVAL;
 564
 565         spin_lock_irqsave(&twl->lock, flags);
 566         ret = sprintf(buf, "%s\n",
 567                         (twl->linkstat == USB_LINK_VBUS) ? "on" : "off");
 568         spin_unlock_irqrestore(&twl->lock, flags);
 569
 570         return ret;
 571 }
 572 static DEVICE_ATTR(vbus, 0444, twl4030_usb_vbus_show, NULL);
 573
 574 static irqreturn_t twl4030_usb_irq(int irq, void *_twl)
 575 {
 576         struct twl4030_usb *twl = _twl;
 577         int status;
 578
 579 #ifdef CONFIG_LOCKDEP
 580         /* WORKAROUND for lockdep forcing IRQF_DISABLED on us, which
 581          * we don't want and can't tolerate.  Although it might be
 582          * friendlier not to borrow this thread context...
 583          */
 584         local_irq_enable();
 585 #endif
 586
 587         status = twl4030_usb_linkstat(twl);
 588         if (status != USB_LINK_UNKNOWN) {
 589
 590                 /* FIXME add a set_power() method so that B-devices can
 591                  * configure the charger appropriately.  It's not always
 592                  * correct to consume VBUS power, and how much current to
 593                  * consume is a function of the USB configuration chosen
 594                  * by the host.
 595                  *
 596                  * REVISIT usb_gadget_vbus_connect(...) as needed, ditto
 597                  * its disconnect() sibling, when changing to/from the
 598                  * USB_LINK_VBUS state.  musb_hdrc won't care until it
 599                  * starts to handle softconnect right.
 600                  */
 601                 if (status == USB_LINK_NONE)
 602                         twl4030_phy_suspend(twl, 0);
 603                 else
 604                         twl4030_phy_resume(twl);
 605
 606                 twl4030charger_usb_en(status == USB_LINK_VBUS);
 607         }
 608         sysfs_notify(&twl->dev->kobj, NULL, "vbus");
 609
 610         return IRQ_HANDLED;
 611 }
 612
 613 static int twl4030_set_suspend(struct otg_transceiver *x, int suspend)
 614 {
 615         struct twl4030_usb *twl = xceiv_to_twl(x);
 616
 617         if (suspend)
 618                 twl4030_phy_suspend(twl, 1);
 619         else
 620                 twl4030_phy_resume(twl);
 621
 622         return 0;
 623 }
 624
 625 static int twl4030_set_peripheral(struct otg_transceiver *x,
 626                 struct usb_gadget *gadget)
 627 {
 628         struct twl4030_usb *twl;
 629
 630         if (!x)
 631                 return -ENODEV;
 632
 633         twl = xceiv_to_twl(x);
 634         twl->otg.gadget = gadget;
 635         if (!gadget)
 636                 twl->otg.state = OTG_STATE_UNDEFINED;
 637
 638         return 0;
 639 }
 640
 641 static int twl4030_set_host(struct otg_transceiver *x, struct usb_bus *host)
 642 {
 643         struct twl4030_usb *twl;
 644
 645         if (!x)
 646                 return -ENODEV;
 647
 648         twl = xceiv_to_twl(x);
 649         twl->otg.host = host;
 650         if (!host)
 651                 twl->otg.state = OTG_STATE_UNDEFINED;
 652
 653         return 0;
 654 }
 655
 656 static int __devinit twl4030_usb_probe(struct platform_device *pdev)
 657 {
 658         struct twl4030_usb_data *pdata = pdev->dev.platform_data;
 659         struct twl4030_usb      *twl;
 660         int                     status, err;
 661
 662         if (!pdata) {
 663                 dev_dbg(&pdev->dev, "platform_data not available\n");
 664                 return -EINVAL;
 665         }
 666
 667         twl = kzalloc(sizeof *twl, GFP_KERNEL);
 668         if (!twl)
 669                 return -ENOMEM;
 670
 671         twl->dev                = &pdev->dev;
 672         twl->irq                = platform_get_irq(pdev, 0);
 673         twl->otg.dev            = twl->dev;
 674         twl->otg.label          = "twl4030";
 675         twl->otg.set_host       = twl4030_set_host;
 676         twl->otg.set_peripheral = twl4030_set_peripheral;
 677         twl->otg.set_suspend    = twl4030_set_suspend;
 678         twl->usb_mode           = pdata->usb_mode;
 679         twl->asleep             = 1;
 680
 681         /* init spinlock for workqueue */
 682         spin_lock_init(&twl->lock);
 683
 684         err = twl4030_usb_ldo_init(twl);
 685         if (err) {
 686                 dev_err(&pdev->dev, "ldo init failed\n");
 687                 kfree(twl);
 688                 return err;
 689         }
 690         otg_set_transceiver(&twl->otg);
 691
 692         platform_set_drvdata(pdev, twl);
 693         if (device_create_file(&pdev->dev, &dev_attr_vbus))
 694                 dev_warn(&pdev->dev, "could not create sysfs file\n");
 695
 696         /* Our job is to use irqs and status from the power module
 697          * to keep the transceiver disabled when nothing's connected.
 698          *
 699          * FIXME we actually shouldn't start enabling it until the
 700          * USB controller drivers have said they're ready, by calling
 701          * set_host() and/or set_peripheral() ... OTG_capable boards
 702          * need both handles, otherwise just one suffices.
 703          */
 704         twl->irq_enabled = true;
 705         status = request_irq(twl->irq, twl4030_usb_irq,
 706                         IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 707                         "twl4030_usb", twl);
 708         if (status < 0) {
 709                 dev_dbg(&pdev->dev, "can't get IRQ %d, err %d\n",
 710                         twl->irq, status);
 711                 kfree(twl);
 712                 return status;
 713         }
 714
 715         /* The IRQ handler just handles changes from the previous states
 716          * of the ID and VBUS pins ... in probe() we must initialize that
 717          * previous state.  The easy way:  fake an IRQ.
 718          *
 719          * REVISIT:  a real IRQ might have happened already, if PREEMPT is
 720          * enabled.  Else the IRQ may not yet be configured or enabled,
 721          * because of scheduling delays.
 722          */
 723         twl4030_usb_irq(twl->irq, twl);
 724
 725         dev_info(&pdev->dev, "Initialized TWL4030 USB module\n");
 726         return 0;
 727 }
 728
 729 static int __exit twl4030_usb_remove(struct platform_device *pdev)
 730 {
 731         struct twl4030_usb *twl = platform_get_drvdata(pdev);
 732         int val;
 733
 734         free_irq(twl->irq, twl);
 735         device_remove_file(twl->dev, &dev_attr_vbus);
 736
 737         /* set transceiver mode to power on defaults */
 738         twl4030_usb_set_mode(twl, -1);
 739
 740         /* autogate 60MHz ULPI clock,
 741          * clear dpll clock request for i2c access,
 742          * disable 32KHz
 743          */
 744         val = twl4030_usb_read(twl, PHY_CLK_CTRL);
 745         if (val >= 0) {
 746                 val |= PHY_CLK_CTRL_CLOCKGATING_EN;
 747                 val &= ~(PHY_CLK_CTRL_CLK32K_EN | REQ_PHY_DPLL_CLK);
 748                 twl4030_usb_write(twl, PHY_CLK_CTRL, (u8)val);
 749         }
 750
 751         /* disable complete OTG block */
 752         twl4030_usb_clear_bits(twl, POWER_CTRL, POWER_CTRL_OTG_ENAB);
 753
 754         twl4030_phy_power(twl, 0);
 755         regulator_put(twl->usb1v5);
 756         regulator_put(twl->usb1v8);
 757         regulator_put(twl->usb3v1);
 758
 759         kfree(twl);
 760
 761         return 0;
 762 }
 763
 764 static struct platform_driver twl4030_usb_driver = {
 765         .probe          = twl4030_usb_probe,
 766         .remove         = __exit_p(twl4030_usb_remove),
 767         .driver         = {
 768                 .name   = "twl4030_usb",
 769                 .owner  = THIS_MODULE,
 770         },
 771 };
 772
 773 static int __init twl4030_usb_init(void)
 774 {
 775         return platform_driver_register(&twl4030_usb_driver);
 776 }
 777 subsys_initcall(twl4030_usb_init);
 778
 779 static void __exit twl4030_usb_exit(void)
 780 {
 781         platform_driver_unregister(&twl4030_usb_driver);
 782 }
 783 module_exit(twl4030_usb_exit);
 784
 785 MODULE_ALIAS("platform:twl4030_usb");
 786 MODULE_AUTHOR("Texas Instruments, Inc, Nokia Corporation");
 787 MODULE_DESCRIPTION("TWL4030 USB transceiver driver");
 788 MODULE_LICENSE("GPL");