drivers/net/wireless/wl12xx/wl1271_spi.h

   1 /*
   2  * This file is part of wl1271
   3  *
   4  * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
   5  * Copyright (C) 2008-2009 Nokia Corporation
   6  *
   7  * Contact: Luciano Coelho <luciano.coelho@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #ifndef __WL1271_SPI_H__
  26 #define __WL1271_SPI_H__
  27
  28 #include "wl1271_reg.h"
  29
  30 #define HW_ACCESS_MEMORY_MAX_RANGE              0x1FFC0
  31
  32 #define HW_PARTITION_REGISTERS_ADDR         0x1ffc0
  33 #define HW_PART0_SIZE_ADDR                  (HW_PARTITION_REGISTERS_ADDR)
  34 #define HW_PART0_START_ADDR                 (HW_PARTITION_REGISTERS_ADDR + 4)
  35 #define HW_PART1_SIZE_ADDR                  (HW_PARTITION_REGISTERS_ADDR + 8)
  36 #define HW_PART1_START_ADDR                 (HW_PARTITION_REGISTERS_ADDR + 12)
  37 #define HW_PART2_SIZE_ADDR                  (HW_PARTITION_REGISTERS_ADDR + 16)
  38 #define HW_PART2_START_ADDR                 (HW_PARTITION_REGISTERS_ADDR + 20)
  39 #define HW_PART3_START_ADDR                 (HW_PARTITION_REGISTERS_ADDR + 24)
  40
  41 #define HW_ACCESS_REGISTER_SIZE             4
  42
  43 #define HW_ACCESS_PRAM_MAX_RANGE                0x3c000
  44
  45 #define WSPI_CMD_READ                 0x40000000
  46 #define WSPI_CMD_WRITE                0x00000000
  47 #define WSPI_CMD_FIXED                0x20000000
  48 #define WSPI_CMD_BYTE_LENGTH          0x1FFE0000
  49 #define WSPI_CMD_BYTE_LENGTH_OFFSET   17
  50 #define WSPI_CMD_BYTE_ADDR            0x0001FFFF
  51
  52 #define WSPI_INIT_CMD_CRC_LEN       5
  53
  54 #define WSPI_INIT_CMD_START         0x00
  55 #define WSPI_INIT_CMD_TX            0x40
  56 /* the extra bypass bit is sampled by the TNET as '1' */
  57 #define WSPI_INIT_CMD_BYPASS_BIT    0x80
  58 #define WSPI_INIT_CMD_FIXEDBUSY_LEN 0x07
  59 #define WSPI_INIT_CMD_EN_FIXEDBUSY  0x80
  60 #define WSPI_INIT_CMD_DIS_FIXEDBUSY 0x00
  61 #define WSPI_INIT_CMD_IOD           0x40
  62 #define WSPI_INIT_CMD_IP            0x20
  63 #define WSPI_INIT_CMD_CS            0x10
  64 #define WSPI_INIT_CMD_WS            0x08
  65 #define WSPI_INIT_CMD_WSPI          0x01
  66 #define WSPI_INIT_CMD_END           0x01
  67
  68 #define WSPI_INIT_CMD_LEN           8
  69
  70 #define HW_ACCESS_WSPI_FIXED_BUSY_LEN \
  71                 ((WL1271_BUSY_WORD_LEN - 4) / sizeof(u32))
  72 #define HW_ACCESS_WSPI_INIT_CMD_MASK  0
  73
  74 #define OCP_CMD_LOOP  32
  75
  76 #define OCP_CMD_WRITE 0x1
  77 #define OCP_CMD_READ  0x2
  78
  79 #define OCP_READY_MASK  BIT(18)
  80 #define OCP_STATUS_MASK (BIT(16) | BIT(17))
  81
  82 #define OCP_STATUS_NO_RESP    0x00000
  83 #define OCP_STATUS_OK         0x10000
  84 #define OCP_STATUS_REQ_FAILED 0x20000
  85 #define OCP_STATUS_RESP_ERROR 0x30000
  86
  87 /* Raw target IO, address is not translated */
  88 void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
  89                       size_t len, bool fixed);
  90 void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
  91                      size_t len, bool fixed);
  92
  93 /* Translated target IO */
  94 void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
  95                      bool fixed);
  96 void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
  97                       bool fixed);
  98 u32 wl1271_spi_read32(struct wl1271 *wl, int addr);
  99 void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val);
 100
 101 /* Top Register IO */
 102 void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
 103 u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
 104
 105 /* INIT and RESET words */
 106 void wl1271_spi_reset(struct wl1271 *wl);
 107 void wl1271_spi_init(struct wl1271 *wl);
 108 int wl1271_set_partition(struct wl1271 *wl,
 109                          struct wl1271_partition_set *p);
 110
 111 static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr)
 112 {
 113         wl1271_spi_raw_read(wl, addr, &wl->buffer_32,
 114                             sizeof(wl->buffer_32), false);
 115
 116         return wl->buffer_32;
 117 }
 118
 119 static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
 120 {
 121         wl->buffer_32 = val;
 122         wl1271_spi_raw_write(wl, addr, &wl->buffer_32,
 123                              sizeof(wl->buffer_32), false);
 124 }
 125
 126 #endif /* __WL1271_SPI_H__ */