| blob | 1f237389d1c771b9e88f29e58f9db3cce0ce4285 |
1 /*
2 * This file is part of wl12xx
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
25 #ifndef __REG_H__
26 #define __REG_H__
28 #include <linux/bitops.h>
30 #define REGISTERS_BASE 0x00300000
31 #define DRPW_BASE 0x00310000
33 #define REGISTERS_DOWN_SIZE 0x00008800
34 #define REGISTERS_WORK_SIZE 0x0000b000
36 #define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
37 #define FW_STATUS_ADDR (0x14FC0 + 0xA000)
39 /* ELP register commands */
40 #define ELPCTRL_WAKE_UP 0x1
41 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
42 #define ELPCTRL_SLEEP 0x0
43 /* ELP WLAN_READY bit */
44 #define ELPCTRL_WLAN_READY 0x2
46 /*===============================================
47 Host Software Reset - 32bit RW
48 ------------------------------------------
49 [31:1] Reserved
50 0 SOFT_RESET Soft Reset - When this bit is set,
51 it holds the Wlan hardware in a soft reset state.
52 This reset disables all MAC and baseband processor
53 clocks except the CardBus/PCI interface clock.
54 It also initializes all MAC state machines except
55 the host interface. It does not reload the
56 contents of the EEPROM. When this bit is cleared
57 (not self-clearing), the Wlan hardware
58 exits the software reset state.
59 ===============================================*/
60 #define ACX_REG_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
62 #define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
63 #define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
64 #define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
65 /*
66 * Interrupt registers.
67 * 64 bit interrupt sources registers ws ced.
68 * sme interupts were removed and new ones were added.
69 * Order was changed.
70 */
71 #define FIQ_MASK (REGISTERS_BASE + 0x0400)
72 #define FIQ_MASK_L (REGISTERS_BASE + 0x0400)
73 #define FIQ_MASK_H (REGISTERS_BASE + 0x0404)
74 #define FIQ_MASK_SET (REGISTERS_BASE + 0x0408)
75 #define FIQ_MASK_SET_L (REGISTERS_BASE + 0x0408)
76 #define FIQ_MASK_SET_H (REGISTERS_BASE + 0x040C)
77 #define FIQ_MASK_CLR (REGISTERS_BASE + 0x0410)
78 #define FIQ_MASK_CLR_L (REGISTERS_BASE + 0x0410)
79 #define FIQ_MASK_CLR_H (REGISTERS_BASE + 0x0414)
80 #define IRQ_MASK (REGISTERS_BASE + 0x0418)
81 #define IRQ_MASK_L (REGISTERS_BASE + 0x0418)
82 #define IRQ_MASK_H (REGISTERS_BASE + 0x041C)
83 #define IRQ_MASK_SET (REGISTERS_BASE + 0x0420)
84 #define IRQ_MASK_SET_L (REGISTERS_BASE + 0x0420)
85 #define IRQ_MASK_SET_H (REGISTERS_BASE + 0x0424)
86 #define IRQ_MASK_CLR (REGISTERS_BASE + 0x0428)
87 #define IRQ_MASK_CLR_L (REGISTERS_BASE + 0x0428)
88 #define IRQ_MASK_CLR_H (REGISTERS_BASE + 0x042C)
89 #define ECPU_MASK (REGISTERS_BASE + 0x0448)
90 #define FIQ_STS_L (REGISTERS_BASE + 0x044C)
91 #define FIQ_STS_H (REGISTERS_BASE + 0x0450)
92 #define IRQ_STS_L (REGISTERS_BASE + 0x0454)
93 #define IRQ_STS_H (REGISTERS_BASE + 0x0458)
94 #define INT_STS_ND (REGISTERS_BASE + 0x0464)
95 #define INT_STS_RAW_L (REGISTERS_BASE + 0x0464)
96 #define INT_STS_RAW_H (REGISTERS_BASE + 0x0468)
97 #define INT_STS_CLR (REGISTERS_BASE + 0x04B4)
98 #define INT_STS_CLR_L (REGISTERS_BASE + 0x04B4)
99 #define INT_STS_CLR_H (REGISTERS_BASE + 0x04B8)
100 #define INT_ACK (REGISTERS_BASE + 0x046C)
101 #define INT_ACK_L (REGISTERS_BASE + 0x046C)
102 #define INT_ACK_H (REGISTERS_BASE + 0x0470)
103 #define INT_TRIG (REGISTERS_BASE + 0x0474)
104 #define INT_TRIG_L (REGISTERS_BASE + 0x0474)
105 #define INT_TRIG_H (REGISTERS_BASE + 0x0478)
106 #define HOST_STS_L (REGISTERS_BASE + 0x045C)
107 #define HOST_STS_H (REGISTERS_BASE + 0x0460)
108 #define HOST_MASK (REGISTERS_BASE + 0x0430)
109 #define HOST_MASK_L (REGISTERS_BASE + 0x0430)
110 #define HOST_MASK_H (REGISTERS_BASE + 0x0434)
111 #define HOST_MASK_SET (REGISTERS_BASE + 0x0438)
112 #define HOST_MASK_SET_L (REGISTERS_BASE + 0x0438)
113 #define HOST_MASK_SET_H (REGISTERS_BASE + 0x043C)
114 #define HOST_MASK_CLR (REGISTERS_BASE + 0x0440)
115 #define HOST_MASK_CLR_L (REGISTERS_BASE + 0x0440)
116 #define HOST_MASK_CLR_H (REGISTERS_BASE + 0x0444)
118 #define ACX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
119 #define ACX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
121 /* Host Interrupts*/
122 #define HINT_MASK (REGISTERS_BASE + 0x0494)
123 #define HINT_MASK_SET (REGISTERS_BASE + 0x0498)
124 #define HINT_MASK_CLR (REGISTERS_BASE + 0x049C)
125 #define HINT_STS_ND_MASKED (REGISTERS_BASE + 0x04A0)
126 /*1150 spec calls this HINT_STS_RAW*/
127 #define HINT_STS_ND (REGISTERS_BASE + 0x04B0)
128 #define HINT_STS_CLR (REGISTERS_BASE + 0x04A4)
129 #define HINT_ACK (REGISTERS_BASE + 0x04A8)
130 #define HINT_TRIG (REGISTERS_BASE + 0x04AC)
132 /*=============================================
133 Host Interrupt Mask Register - 32bit (RW)
134 ------------------------------------------
135 Setting a bit in this register masks the
136 corresponding interrupt to the host.
137 0 - RX0 - Rx first dubble buffer Data Interrupt
138 1 - TXD - Tx Data Interrupt
139 2 - TXXFR - Tx Transfer Interrupt
140 3 - RX1 - Rx second dubble buffer Data Interrupt
141 4 - RXXFR - Rx Transfer Interrupt
142 5 - EVENT_A - Event Mailbox interrupt
143 6 - EVENT_B - Event Mailbox interrupt
144 7 - WNONHST - Wake On Host Interrupt
145 8 - TRACE_A - Debug Trace interrupt
146 9 - TRACE_B - Debug Trace interrupt
147 10 - CDCMP - Command Complete Interrupt
148 11 -
149 12 -
150 13 -
151 14 - ICOMP - Initialization Complete Interrupt
152 16 - SG SE - Soft Gemini - Sense enable interrupt
153 17 - SG SD - Soft Gemini - Sense disable interrupt
154 18 - -
155 19 - -
156 20 - -
157 21- -
158 Default: 0x0001
159 *==============================================*/
160 #define ACX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
162 /*=============================================
163 Host Interrupt Mask Set 16bit, (Write only)
164 ------------------------------------------
165 Setting a bit in this register sets
166 the corresponding bin in ACX_HINT_MASK register
167 without effecting the mask
168 state of other bits (0 = no effect).
169 ==============================================*/
170 #define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
172 /*=============================================
173 Host Interrupt Mask Clear 16bit,(Write only)
174 ------------------------------------------
175 Setting a bit in this register clears
176 the corresponding bin in ACX_HINT_MASK register
177 without effecting the mask
178 state of other bits (0 = no effect).
179 =============================================*/
180 #define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
182 /*=============================================
183 Host Interrupt Status Nondestructive Read
184 16bit,(Read only)
185 ------------------------------------------
186 The host can read this register to determine
187 which interrupts are active.
188 Reading this register doesn't
189 effect its content.
190 =============================================*/
191 #define ACX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
193 /*=============================================
194 Host Interrupt Status Clear on Read Register
195 16bit,(Read only)
196 ------------------------------------------
197 The host can read this register to determine
198 which interrupts are active.
199 Reading this register clears it,
200 thus making all interrupts inactive.
201 ==============================================*/
202 #define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
204 /*=============================================
205 Host Interrupt Acknowledge Register
206 16bit,(Write only)
207 ------------------------------------------
208 The host can set individual bits in this
209 register to clear (acknowledge) the corresp.
210 interrupt status bits in the HINT_STS_CLR and
211 HINT_STS_ND registers, thus making the
212 assotiated interrupt inactive. (0-no effect)
213 ==============================================*/
214 #define ACX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
216 #define RX_DRIVER_COUNTER_ADDRESS (REGISTERS_BASE + 0x0538)
218 /* Device Configuration registers*/
219 #define SOR_CFG (REGISTERS_BASE + 0x0800)
221 /* Embedded ARM CPU Control */
223 /*===============================================
224 Halt eCPU - 32bit RW
225 ------------------------------------------
226 0 HALT_ECPU Halt Embedded CPU - This bit is the
227 compliment of bit 1 (MDATA2) in the SOR_CFG register.
228 During a hardware reset, this bit holds
229 the inverse of MDATA2.
230 When downloading firmware from the host,
231 set this bit (pull down MDATA2).
232 The host clears this bit after downloading the firmware into
233 zero-wait-state SSRAM.
234 When loading firmware from Flash, clear this bit (pull up MDATA2)
235 so that the eCPU can run the bootloader code in Flash
236 HALT_ECPU eCPU State
237 --------------------
238 1 halt eCPU
239 0 enable eCPU
240 ===============================================*/
241 #define ACX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
243 #define HI_CFG (REGISTERS_BASE + 0x0808)
245 /*===============================================
246 EEPROM Burst Read Start - 32bit RW
247 ------------------------------------------
248 [31:1] Reserved
249 0 ACX_EE_START - EEPROM Burst Read Start 0
250 Setting this bit starts a burst read from
251 the external EEPROM.
252 If this bit is set (after reset) before an EEPROM read/write,
253 the burst read starts at EEPROM address 0.
254 Otherwise, it starts at the address
255 following the address of the previous access.
256 TheWlan hardware hardware clears this bit automatically.
258 Default: 0x00000000
259 *================================================*/
260 #define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
262 #define OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
263 #define OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
264 #define OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
265 #define OCP_CMD (REGISTERS_BASE + 0x09C0)
267 #define WL1271_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
269 #define CHIP_ID_B (REGISTERS_BASE + 0x5674)
271 #define CHIP_ID_1271_PG10 (0x4030101)
272 #define CHIP_ID_1271_PG20 (0x4030111)
274 #define ENABLE (REGISTERS_BASE + 0x5450)
276 /* Power Management registers */
277 #define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
278 #define ELP_CMD (REGISTERS_BASE + 0x5808)
279 #define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
280 #define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
281 #define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
283 #define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
285 /* Scratch Pad registers*/
286 #define SCR_PAD0 (REGISTERS_BASE + 0x5608)
287 #define SCR_PAD1 (REGISTERS_BASE + 0x560C)
288 #define SCR_PAD2 (REGISTERS_BASE + 0x5610)
289 #define SCR_PAD3 (REGISTERS_BASE + 0x5614)
290 #define SCR_PAD4 (REGISTERS_BASE + 0x5618)
291 #define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
292 #define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
293 #define SCR_PAD5 (REGISTERS_BASE + 0x5624)
294 #define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
295 #define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
296 #define SCR_PAD6 (REGISTERS_BASE + 0x5630)
297 #define SCR_PAD7 (REGISTERS_BASE + 0x5634)
298 #define SCR_PAD8 (REGISTERS_BASE + 0x5638)
299 #define SCR_PAD9 (REGISTERS_BASE + 0x563C)
301 /* Spare registers*/
302 #define SPARE_A1 (REGISTERS_BASE + 0x0994)
303 #define SPARE_A2 (REGISTERS_BASE + 0x0998)
304 #define SPARE_A3 (REGISTERS_BASE + 0x099C)
305 #define SPARE_A4 (REGISTERS_BASE + 0x09A0)
306 #define SPARE_A5 (REGISTERS_BASE + 0x09A4)
307 #define SPARE_A6 (REGISTERS_BASE + 0x09A8)
308 #define SPARE_A7 (REGISTERS_BASE + 0x09AC)
309 #define SPARE_A8 (REGISTERS_BASE + 0x09B0)
310 #define SPARE_B1 (REGISTERS_BASE + 0x5420)
311 #define SPARE_B2 (REGISTERS_BASE + 0x5424)
312 #define SPARE_B3 (REGISTERS_BASE + 0x5428)
313 #define SPARE_B4 (REGISTERS_BASE + 0x542C)
314 #define SPARE_B5 (REGISTERS_BASE + 0x5430)
315 #define SPARE_B6 (REGISTERS_BASE + 0x5434)
316 #define SPARE_B7 (REGISTERS_BASE + 0x5438)
317 #define SPARE_B8 (REGISTERS_BASE + 0x543C)
319 #define PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
320 #define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
321 #define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
322 #define DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
325 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
326 #define ACX_REG_EEPROM_START_BIT BIT(1)
328 /* Command/Information Mailbox Pointers */
330 /*===============================================
331 Command Mailbox Pointer - 32bit RW
332 ------------------------------------------
333 This register holds the start address of
334 the command mailbox located in the Wlan hardware memory.
335 The host must read this pointer after a reset to
336 find the location of the command mailbox.
337 The Wlan hardware initializes the command mailbox
338 pointer with the default address of the command mailbox.
339 The command mailbox pointer is not valid until after
340 the host receives the Init Complete interrupt from
341 the Wlan hardware.
342 ===============================================*/
343 #define REG_COMMAND_MAILBOX_PTR (SCR_PAD0)
345 /*===============================================
346 Information Mailbox Pointer - 32bit RW
347 ------------------------------------------
348 This register holds the start address of
349 the information mailbox located in the Wlan hardware memory.
350 The host must read this pointer after a reset to find
351 the location of the information mailbox.
352 The Wlan hardware initializes the information mailbox pointer
353 with the default address of the information mailbox.
354 The information mailbox pointer is not valid
355 until after the host receives the Init Complete interrupt from
356 the Wlan hardware.
357 ===============================================*/
358 #define REG_EVENT_MAILBOX_PTR (SCR_PAD1)
361 /* Misc */
363 #define REG_ENABLE_TX_RX (ENABLE)
364 /*
365 * Rx configuration (filter) information element
366 * ---------------------------------------------
367 */
368 #define REG_RX_CONFIG (RX_CFG)
369 #define REG_RX_FILTER (RX_FILTER_CFG)
372 #define RX_CFG_ENABLE_PHY_HEADER_PLCP 0x0002
374 /* promiscuous - receives all valid frames */
375 #define RX_CFG_PROMISCUOUS 0x0008
377 /* receives frames from any BSSID */
378 #define RX_CFG_BSSID 0x0020
380 /* receives frames destined to any MAC address */
381 #define RX_CFG_MAC 0x0010
383 #define RX_CFG_ENABLE_ONLY_MY_DEST_MAC 0x0010
384 #define RX_CFG_ENABLE_ANY_DEST_MAC 0x0000
385 #define RX_CFG_ENABLE_ONLY_MY_BSSID 0x0020
386 #define RX_CFG_ENABLE_ANY_BSSID 0x0000
388 /* discards all broadcast frames */
389 #define RX_CFG_DISABLE_BCAST 0x0200
391 #define RX_CFG_ENABLE_ONLY_MY_SSID 0x0400
392 #define RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR 0x0800
393 #define RX_CFG_COPY_RX_STATUS 0x2000
394 #define RX_CFG_TSF 0x10000
396 #define RX_CONFIG_OPTION_ANY_DST_MY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
397 RX_CFG_ENABLE_ONLY_MY_BSSID)
399 #define RX_CONFIG_OPTION_MY_DST_ANY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
400 | RX_CFG_ENABLE_ANY_BSSID)
402 #define RX_CONFIG_OPTION_ANY_DST_ANY_BSS (RX_CFG_ENABLE_ANY_DEST_MAC | \
403 RX_CFG_ENABLE_ANY_BSSID)
405 #define RX_CONFIG_OPTION_MY_DST_MY_BSS (RX_CFG_ENABLE_ONLY_MY_DEST_MAC\
406 | RX_CFG_ENABLE_ONLY_MY_BSSID)
408 #define RX_CONFIG_OPTION_FOR_SCAN (RX_CFG_ENABLE_PHY_HEADER_PLCP \
409 | RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR \
410 | RX_CFG_COPY_RX_STATUS | RX_CFG_TSF)
412 #define RX_CONFIG_OPTION_FOR_MEASUREMENT (RX_CFG_ENABLE_ANY_DEST_MAC)
414 #define RX_CONFIG_OPTION_FOR_JOIN (RX_CFG_ENABLE_ONLY_MY_BSSID | \
415 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
417 #define RX_CONFIG_OPTION_FOR_IBSS_JOIN (RX_CFG_ENABLE_ONLY_MY_SSID | \
418 RX_CFG_ENABLE_ONLY_MY_DEST_MAC)
420 #define RX_FILTER_OPTION_DEF (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
421 | CFG_RX_CTL_EN | CFG_RX_BCN_EN\
422 | CFG_RX_AUTH_EN | CFG_RX_ASSOC_EN)
424 #define RX_FILTER_OPTION_FILTER_ALL 0
426 #define RX_FILTER_OPTION_DEF_PRSP_BCN (CFG_RX_PRSP_EN | CFG_RX_MGMT_EN\
427 | CFG_RX_RCTS_ACK | CFG_RX_BCN_EN)
429 #define RX_FILTER_OPTION_JOIN (CFG_RX_MGMT_EN | CFG_RX_DATA_EN\
430 | CFG_RX_BCN_EN | CFG_RX_AUTH_EN\
431 | CFG_RX_ASSOC_EN | CFG_RX_RCTS_ACK\
432 | CFG_RX_PRSP_EN)
435 /*===============================================
436 Phy regs
437 ===============================================*/
438 #define ACX_PHY_ADDR_REG SBB_ADDR
439 #define ACX_PHY_DATA_REG SBB_DATA
440 #define ACX_PHY_CTRL_REG SBB_CTL
441 #define ACX_PHY_REG_WR_MASK 0x00000001ul
442 #define ACX_PHY_REG_RD_MASK 0x00000002ul
445 /*===============================================
446 EEPROM Read/Write Request 32bit RW
447 ------------------------------------------
448 1 EE_READ - EEPROM Read Request 1 - Setting this bit
449 loads a single byte of data into the EE_DATA
450 register from the EEPROM location specified in
451 the EE_ADDR register.
452 The Wlan hardware hardware clears this bit automatically.
453 EE_DATA is valid when this bit is cleared.
455 0 EE_WRITE - EEPROM Write Request - Setting this bit
456 writes a single byte of data from the EE_DATA register into the
457 EEPROM location specified in the EE_ADDR register.
458 The Wlan hardware hardware clears this bit automatically.
459 *===============================================*/
460 #define ACX_EE_CTL_REG EE_CTL
461 #define EE_WRITE 0x00000001ul
462 #define EE_READ 0x00000002ul
464 /*===============================================
465 EEPROM Address - 32bit RW
466 ------------------------------------------
467 This register specifies the address
468 within the EEPROM from/to which to read/write data.
469 ===============================================*/
470 #define ACX_EE_ADDR_REG EE_ADDR
472 /*===============================================
473 EEPROM Data - 32bit RW
474 ------------------------------------------
475 This register either holds the read 8 bits of
476 data from the EEPROM or the write data
477 to be written to the EEPROM.
478 ===============================================*/
479 #define ACX_EE_DATA_REG EE_DATA
481 /*===============================================
482 EEPROM Base Address - 32bit RW
483 ------------------------------------------
484 This register holds the upper nine bits
485 [23:15] of the 24-bit Wlan hardware memory
486 address for burst reads from EEPROM accesses.
487 The EEPROM provides the lower 15 bits of this address.
488 The MSB of the address from the EEPROM is ignored.
489 ===============================================*/
490 #define ACX_EE_CFG EE_CFG
492 /*===============================================
493 GPIO Output Values -32bit, RW
494 ------------------------------------------
495 [31:16] Reserved
496 [15: 0] Specify the output values (at the output driver inputs) for
497 GPIO[15:0], respectively.
498 ===============================================*/
499 #define ACX_GPIO_OUT_REG GPIO_OUT
500 #define ACX_MAX_GPIO_LINES 15
502 /*===============================================
503 Contention window -32bit, RW
504 ------------------------------------------
505 [31:26] Reserved
506 [25:16] Max (0x3ff)
507 [15:07] Reserved
508 [06:00] Current contention window value - default is 0x1F
509 ===============================================*/
510 #define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
511 #define ACX_CONT_WIND_MIN_MASK 0x0000007f
512 #define ACX_CONT_WIND_MAX 0x03ff0000
514 /*
515 * Indirect slave register/memory registers
516 * ----------------------------------------
517 */
518 #define HW_SLAVE_REG_ADDR_REG 0x00000004
519 #define HW_SLAVE_REG_DATA_REG 0x00000008
520 #define HW_SLAVE_REG_CTRL_REG 0x0000000c
522 #define SLAVE_AUTO_INC 0x00010000
523 #define SLAVE_NO_AUTO_INC 0x00000000
524 #define SLAVE_HOST_LITTLE_ENDIAN 0x00000000
526 #define HW_SLAVE_MEM_ADDR_REG SLV_MEM_ADDR
527 #define HW_SLAVE_MEM_DATA_REG SLV_MEM_DATA
528 #define HW_SLAVE_MEM_CTRL_REG SLV_MEM_CTL
529 #define HW_SLAVE_MEM_ENDIAN_REG SLV_END_CTL
531 #define HW_FUNC_EVENT_INT_EN 0x8000
532 #define HW_FUNC_EVENT_MASK_REG 0x00000034
534 #define ACX_MAC_TIMESTAMP_REG (MAC_TIMESTAMP)
536 /*===============================================
537 HI_CFG Interface Configuration Register Values
538 ------------------------------------------
539 ===============================================*/
540 #define HI_CFG_UART_ENABLE 0x00000004
541 #define HI_CFG_RST232_ENABLE 0x00000008
542 #define HI_CFG_CLOCK_REQ_SELECT 0x00000010
543 #define HI_CFG_HOST_INT_ENABLE 0x00000020
544 #define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
545 #define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
546 #define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
547 #define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
548 #define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
550 /*
551 * NOTE: USE_ACTIVE_HIGH compilation flag should be defined in makefile
552 * for platforms using active high interrupt level
553 */
554 #ifdef USE_ACTIVE_HIGH
555 #define HI_CFG_DEF_VAL \
556 (HI_CFG_UART_ENABLE | \
557 HI_CFG_RST232_ENABLE | \
558 HI_CFG_CLOCK_REQ_SELECT | \
559 HI_CFG_HOST_INT_ENABLE)
560 #else
561 #define HI_CFG_DEF_VAL \
562 (HI_CFG_UART_ENABLE | \
563 HI_CFG_RST232_ENABLE | \
564 HI_CFG_CLOCK_REQ_SELECT | \
565 HI_CFG_HOST_INT_ENABLE)
567 #endif
569 #define REF_FREQ_19_2 0
570 #define REF_FREQ_26_0 1
571 #define REF_FREQ_38_4 2
572 #define REF_FREQ_40_0 3
573 #define REF_FREQ_33_6 4
574 #define REF_FREQ_NUM 5
576 #define LUT_PARAM_INTEGER_DIVIDER 0
577 #define LUT_PARAM_FRACTIONAL_DIVIDER 1
578 #define LUT_PARAM_ATTN_BB 2
579 #define LUT_PARAM_ALPHA_BB 3
580 #define LUT_PARAM_STOP_TIME_BB 4
581 #define LUT_PARAM_BB_PLL_LOOP_FILTER 5
582 #define LUT_PARAM_NUM 6
584 #define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
585 #define USE_EEPROM 0
586 #define SOFT_RESET_MAX_TIME 1000000
587 #define SOFT_RESET_STALL_TIME 1000
588 #define NVS_DATA_BUNDARY_ALIGNMENT 4
591 /* Firmware image load chunk size */
592 #define CHUNK_SIZE 512
594 /* Firmware image header size */
595 #define FW_HDR_SIZE 8
597 #define ECPU_CONTROL_HALT 0x00000101
600 /******************************************************************************
602 CHANNELS, BAND & REG DOMAINS definitions
604 ******************************************************************************/
614 };
617 #define OFDM_RATE_BIT BIT(6)
618 #define PBCC_RATE_BIT BIT(7)
625 OFDM = OFDM_RATE_BIT
626 };
628 /******************************************************************************
630 Transmit-Descriptor RATE-SET field definitions...
632 Define a new "Rate-Set" for TX path that incorporates the
633 Rate & Modulation info into a single 16-bit field.
635 TxdRateSet_t:
636 b15 - Indicates Preamble type (1=SHORT, 0=LONG).
637 Notes:
638 Must be LONG (0) for 1Mbps rate.
639 Does not apply (set to 0) for RevG-OFDM rates.
640 b14 - Indicates PBCC encoding (1=PBCC, 0=not).
641 Notes:
642 Does not apply (set to 0) for rates 1 and 2 Mbps.
643 Does not apply (set to 0) for RevG-OFDM rates.
644 b13 - Unused (set to 0).
645 b12-b0 - Supported Rate indicator bits as defined below.
647 ******************************************************************************/
650 #define TNETW1251_CHIP_ID_PG1_0 0x07010101
651 #define TNETW1251_CHIP_ID_PG1_1 0x07020101
652 #define TNETW1251_CHIP_ID_PG1_2 0x07030101
654 /*************************************************************************
656 Interrupt Trigger Register (Host -> WiLink)
658 **************************************************************************/
660 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
662 /*
663 * Host Command Interrupt. Setting this bit masks
664 * the interrupt that the host issues to inform
665 * the FW that it has sent a command
666 * to the Wlan hardware Command Mailbox.
667 */
668 #define INTR_TRIG_CMD BIT(0)
670 /*
671 * Host Event Acknowlegde Interrupt. The host
672 * sets this bit to acknowledge that it received
673 * the unsolicited information from the event
674 * mailbox.
675 */
676 #define INTR_TRIG_EVENT_ACK BIT(1)
678 /*
679 * The host sets this bit to inform the Wlan
680 * FW that a TX packet is in the XFER
681 * Buffer #0.
682 */
683 #define INTR_TRIG_TX_PROC0 BIT(2)
685 /*
686 * The host sets this bit to inform the FW
687 * that it read a packet from RX XFER
688 * Buffer #0.
689 */
690 #define INTR_TRIG_RX_PROC0 BIT(3)
692 #define INTR_TRIG_DEBUG_ACK BIT(4)
694 #define INTR_TRIG_STATE_CHANGED BIT(5)
697 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
699 /*
700 * The host sets this bit to inform the FW
701 * that it read a packet from RX XFER
702 * Buffer #1.
703 */
704 #define INTR_TRIG_RX_PROC1 BIT(17)
706 /*
707 * The host sets this bit to inform the Wlan
708 * hardware that a TX packet is in the XFER
709 * Buffer #1.
710 */
711 #define INTR_TRIG_TX_PROC1 BIT(18)
713 #endif