drivers/ide/slc90e66.c

   1 /*
   2  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
   3  *  Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
   6  * but this keeps the ISA-Bridge and slots alive.
   7  *
   8  */
   9
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/ide.h>
  15 #include <linux/init.h>
  16
  17 #define DRV_NAME "slc90e66"
  18
  19 static DEFINE_SPINLOCK(slc90e66_lock);
  20
  21 static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
  22 {
  23         ide_hwif_t *hwif        = drive->hwif;
  24         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  25         int is_slave            = drive->dn & 1;
  26         int master_port         = hwif->channel ? 0x42 : 0x40;
  27         int slave_port          = 0x44;
  28         unsigned long flags;
  29         u16 master_data;
  30         u8 slave_data;
  31         int control = 0;
  32                                      /* ISP  RTC */
  33         static const u8 timings[][2] = {
  34                                         { 0, 0 },
  35                                         { 0, 0 },
  36                                         { 1, 0 },
  37                                         { 2, 1 },
  38                                         { 2, 3 }, };
  39
  40         spin_lock_irqsave(&slc90e66_lock, flags);
  41         pci_read_config_word(dev, master_port, &master_data);
  42
  43         if (pio > 1)
  44                 control |= 1;   /* Programmable timing on */
  45         if (drive->media == ide_disk)
  46                 control |= 4;   /* Prefetch, post write */
  47         if (ide_pio_need_iordy(drive, pio))
  48                 control |= 2;   /* IORDY */
  49         if (is_slave) {
  50                 master_data |=  0x4000;
  51                 master_data &= ~0x0070;
  52                 if (pio > 1) {
  53                         /* Set PPE, IE and TIME */
  54                         master_data |= control << 4;
  55                 }
  56                 pci_read_config_byte(dev, slave_port, &slave_data);
  57                 slave_data &= hwif->channel ? 0x0f : 0xf0;
  58                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  59                                (hwif->channel ? 4 : 0);
  60         } else {
  61                 master_data &= ~0x3307;
  62                 if (pio > 1) {
  63                         /* enable PPE, IE and TIME */
  64                         master_data |= control;
  65                 }
  66                 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  67         }
  68         pci_write_config_word(dev, master_port, master_data);
  69         if (is_slave)
  70                 pci_write_config_byte(dev, slave_port, slave_data);
  71         spin_unlock_irqrestore(&slc90e66_lock, flags);
  72 }
  73
  74 static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
  75 {
  76         ide_hwif_t *hwif        = drive->hwif;
  77         struct pci_dev *dev     = to_pci_dev(hwif->dev);
  78         u8 maslave              = hwif->channel ? 0x42 : 0x40;
  79         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
  80         int u_speed = 0, u_flag = 1 << drive->dn;
  81         u16                     reg4042, reg44, reg48, reg4a;
  82
  83         pci_read_config_word(dev, maslave, &reg4042);
  84         sitre = (reg4042 & 0x4000) ? 1 : 0;
  85         pci_read_config_word(dev, 0x44, &reg44);
  86         pci_read_config_word(dev, 0x48, &reg48);
  87         pci_read_config_word(dev, 0x4a, &reg4a);
  88
  89         if (speed >= XFER_UDMA_0) {
  90                 u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
  91
  92                 if (!(reg48 & u_flag))
  93                         pci_write_config_word(dev, 0x48, reg48|u_flag);
  94                 if ((reg4a & a_speed) != u_speed) {
  95                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  96                         pci_read_config_word(dev, 0x4a, &reg4a);
  97                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
  98                 }
  99         } else {
 100                 const u8 mwdma_to_pio[] = { 0, 3, 4 };
 101                 u8 pio;
 102
 103                 if (reg48 & u_flag)
 104                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
 105                 if (reg4a & a_speed)
 106                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 107
 108                 if (speed >= XFER_MW_DMA_0)
 109                         pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
 110                 else
 111                         pio = 2; /* only SWDMA2 is allowed */
 112
 113                 slc90e66_set_pio_mode(drive, pio);
 114         }
 115 }
 116
 117 static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
 118 {
 119         struct pci_dev *dev = to_pci_dev(hwif->dev);
 120         u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
 121
 122         pci_read_config_byte(dev, 0x47, &reg47);
 123
 124         /* bit[0(1)]: 0:80, 1:40 */
 125         return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 126 }
 127
 128 static const struct ide_port_ops slc90e66_port_ops = {
 129         .set_pio_mode           = slc90e66_set_pio_mode,
 130         .set_dma_mode           = slc90e66_set_dma_mode,
 131         .cable_detect           = slc90e66_cable_detect,
 132 };
 133
 134 static const struct ide_port_info slc90e66_chipset __devinitdata = {
 135         .name           = DRV_NAME,
 136         .enablebits     = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
 137         .port_ops       = &slc90e66_port_ops,
 138         .pio_mask       = ATA_PIO4,
 139         .swdma_mask     = ATA_SWDMA2_ONLY,
 140         .mwdma_mask     = ATA_MWDMA12_ONLY,
 141         .udma_mask      = ATA_UDMA4,
 142 };
 143
 144 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 145 {
 146         return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
 147 }
 148
 149 static const struct pci_device_id slc90e66_pci_tbl[] = {
 150         { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
 151         { 0, },
 152 };
 153 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
 154
 155 static struct pci_driver slc90e66_pci_driver = {
 156         .name           = "SLC90e66_IDE",
 157         .id_table       = slc90e66_pci_tbl,
 158         .probe          = slc90e66_init_one,
 159         .remove         = ide_pci_remove,
 160         .suspend        = ide_pci_suspend,
 161         .resume         = ide_pci_resume,
 162 };
 163
 164 static int __init slc90e66_ide_init(void)
 165 {
 166         return ide_pci_register_driver(&slc90e66_pci_driver);
 167 }
 168
 169 static void __exit slc90e66_ide_exit(void)
 170 {
 171         pci_unregister_driver(&slc90e66_pci_driver);
 172 }
 173
 174 module_init(slc90e66_ide_init);
 175 module_exit(slc90e66_ide_exit);
 176
 177 MODULE_AUTHOR("Andre Hedrick");
 178 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
 179 MODULE_LICENSE("GPL");