arch/sparc/include/asm/system_64.h

   1 #ifndef __SPARC64_SYSTEM_H
   2 #define __SPARC64_SYSTEM_H
   3
   4 #include <asm/ptrace.h>
   5 #include <asm/processor.h>
   6 #include <asm/visasm.h>
   7
   8 #ifndef __ASSEMBLY__
   9
  10 #include <linux/irqflags.h>
  11 #include <asm-generic/cmpxchg-local.h>
  12
  13 /*
  14  * Sparc (general) CPU types
  15  */
  16 enum sparc_cpu {
  17   sun4        = 0x00,
  18   sun4c       = 0x01,
  19   sun4m       = 0x02,
  20   sun4d       = 0x03,
  21   sun4e       = 0x04,
  22   sun4u       = 0x05, /* V8 ploos ploos */
  23   sun_unknown = 0x06,
  24   ap1000      = 0x07, /* almost a sun4m */
  25 };
  26
  27 #define sparc_cpu_model sun4u
  28
  29 /* This cannot ever be a sun4c :) That's just history. */
  30 #define ARCH_SUN4C 0
  31
  32 extern const char *sparc_cpu_type;
  33 extern const char *sparc_fpu_type;
  34 extern const char *sparc_pmu_type;
  35
  36 extern char reboot_command[];
  37
  38 /* These are here in an effort to more fully work around Spitfire Errata
  39  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
  40  * branch, the chip can stop executing instructions until a trap occurs.
  41  * Therefore, if interrupts are disabled, the chip can hang forever.
  42  *
  43  * It used to be believed that the memory barrier had to be right in the
  44  * delay slot, but a case has been traced recently wherein the memory barrier
  45  * was one instruction after the branch delay slot and the chip still hung.
  46  * The offending sequence was the following in sym_wakeup_done() of the
  47  * sym53c8xx_2 driver:
  48  *
  49  *      call    sym_ccb_from_dsa, 0
  50  *       movge  %icc, 0, %l0
  51  *      brz,pn  %o0, .LL1303
  52  *       mov    %o0, %l2
  53  *      membar  #LoadLoad
  54  *
  55  * The branch has to be mispredicted for the bug to occur.  Therefore, we put
  56  * the memory barrier explicitly into a "branch always, predicted taken"
  57  * delay slot to avoid the problem case.
  58  */
  59 #define membar_safe(type) \
  60 do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
  61                              " membar   " type "\n" \
  62                              "1:\n" \
  63                              : : : "memory"); \
  64 } while (0)
  65
  66 /* The kernel always executes in TSO memory model these days,
  67  * and furthermore most sparc64 chips implement more stringent
  68  * memory ordering than required by the specifications.
  69  */
  70 #define mb()    membar_safe("#StoreLoad")
  71 #define rmb()   __asm__ __volatile__("":::"memory")
  72 #define wmb()   __asm__ __volatile__("":::"memory")
  73
  74 #endif
  75
  76 #define nop()           __asm__ __volatile__ ("nop")
  77
  78 #define read_barrier_depends()          do { } while(0)
  79 #define set_mb(__var, __value) \
  80         do { __var = __value; membar_safe("#StoreLoad"); } while(0)
  81
  82 #ifdef CONFIG_SMP
  83 #define smp_mb()        mb()
  84 #define smp_rmb()       rmb()
  85 #define smp_wmb()       wmb()
  86 #else
  87 #define smp_mb()        __asm__ __volatile__("":::"memory")
  88 #define smp_rmb()       __asm__ __volatile__("":::"memory")
  89 #define smp_wmb()       __asm__ __volatile__("":::"memory")
  90 #endif
  91
  92 #define smp_read_barrier_depends()      do { } while(0)
  93
  94 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
  95
  96 #define flushw_all()    __asm__ __volatile__("flushw")
  97
  98 /* Performance counter register access. */
  99 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
 100 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
 101 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
 102
 103 /* Blackbird errata workaround.  See commentary in
 104  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
 105  * for more information.
 106  */
 107 #define write_pic(__p)                                          \
 108         __asm__ __volatile__("ba,pt     %%xcc, 99f\n\t"         \
 109                              ".align    64\n"                   \
 110                           "99:wr        %0, 0x0, %%pic\n\t"     \
 111                              "rd        %%pic, %%g0" : : "r" (__p))
 112 #define reset_pic()     write_pic(0)
 113
 114 #ifndef __ASSEMBLY__
 115
 116 extern void sun_do_break(void);
 117 extern int stop_a_enabled;
 118 extern int scons_pwroff;
 119
 120 extern void fault_in_user_windows(void);
 121 extern void synchronize_user_stack(void);
 122
 123 extern void __flushw_user(void);
 124 #define flushw_user() __flushw_user()
 125
 126 #define flush_user_windows flushw_user
 127 #define flush_register_windows flushw_all
 128
 129 /* Don't hold the runqueue lock over context switch */
 130 #define __ARCH_WANT_UNLOCKED_CTXSW
 131 #define prepare_arch_switch(next)               \
 132 do {                                            \
 133         flushw_all();                           \
 134 } while (0)
 135
 136         /* See what happens when you design the chip correctly?
 137          *
 138          * We tell gcc we clobber all non-fixed-usage registers except
 139          * for l0/l1.  It will use one for 'next' and the other to hold
 140          * the output value of 'last'.  'next' is not referenced again
 141          * past the invocation of switch_to in the scheduler, so we need
 142          * not preserve it's value.  Hairy, but it lets us remove 2 loads
 143          * and 2 stores in this critical code path.  -DaveM
 144          */
 145 #define switch_to(prev, next, last)                                     \
 146 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
 147                 unsigned long __tmp;                                    \
 148                 read_pcr(__tmp);                                        \
 149                 current_thread_info()->pcr_reg = __tmp;                 \
 150                 read_pic(__tmp);                                        \
 151                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
 152                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
 153         }                                                               \
 154         flush_tlb_pending();                                            \
 155         save_and_clear_fpu();                                           \
 156         /* If you are tempted to conditionalize the following */        \
 157         /* so that ASI is only written if it changes, think again. */   \
 158         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
 159         : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
 160         trap_block[current_thread_info()->cpu].thread =                 \
 161                 task_thread_info(next);                                 \
 162         __asm__ __volatile__(                                           \
 163         "mov    %%g4, %%g7\n\t"                                         \
 164         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
 165         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
 166         "rdpr   %%wstate, %%o5\n\t"                                     \
 167         "stx    %%o6, [%%g6 + %6]\n\t"                                  \
 168         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
 169         "rdpr   %%cwp, %%o5\n\t"                                        \
 170         "stb    %%o5, [%%g6 + %8]\n\t"                                  \
 171         "wrpr   %%g0, 15, %%pil\n\t"                                    \
 172         "mov    %4, %%g6\n\t"                                           \
 173         "ldub   [%4 + %8], %%g1\n\t"                                    \
 174         "wrpr   %%g1, %%cwp\n\t"                                        \
 175         "ldx    [%%g6 + %6], %%o6\n\t"                                  \
 176         "ldub   [%%g6 + %5], %%o5\n\t"                                  \
 177         "ldub   [%%g6 + %7], %%o7\n\t"                                  \
 178         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
 179         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
 180         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
 181         "ldx    [%%g6 + %9], %%g4\n\t"                                  \
 182         "wrpr   %%g0, 14, %%pil\n\t"                                    \
 183         "brz,pt %%o7, switch_to_pc\n\t"                                 \
 184         " mov   %%g7, %0\n\t"                                           \
 185         "sethi  %%hi(ret_from_syscall), %%g1\n\t"                       \
 186         "jmpl   %%g1 + %%lo(ret_from_syscall), %%g0\n\t"                \
 187         " nop\n\t"                                                      \
 188         ".globl switch_to_pc\n\t"                                       \
 189         "switch_to_pc:\n\t"                                             \
 190         : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
 191           "=r" (__local_per_cpu_offset)                                 \
 192         : "0" (task_thread_info(next)),                                 \
 193           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
 194           "i" (TI_CWP), "i" (TI_TASK)                                   \
 195         : "cc",                                                         \
 196                 "g1", "g2", "g3",                   "g7",               \
 197                 "l1", "l2", "l3", "l4", "l5", "l6", "l7",               \
 198           "i0", "i1", "i2", "i3", "i4", "i5",                           \
 199           "o0", "o1", "o2", "o3", "o4", "o5",       "o7");              \
 200         /* If you fuck with this, update ret_from_syscall code too. */  \
 201         if (test_thread_flag(TIF_PERFCTR)) {                            \
 202                 write_pcr(current_thread_info()->pcr_reg);              \
 203                 reset_pic();                                            \
 204         }                                                               \
 205 } while(0)
 206
 207 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
 208 {
 209         unsigned long tmp1, tmp2;
 210
 211         __asm__ __volatile__(
 212 "       mov             %0, %1\n"
 213 "1:     lduw            [%4], %2\n"
 214 "       cas             [%4], %2, %0\n"
 215 "       cmp             %2, %0\n"
 216 "       bne,a,pn        %%icc, 1b\n"
 217 "        mov            %1, %0\n"
 218         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 219         : "0" (val), "r" (m)
 220         : "cc", "memory");
 221         return val;
 222 }
 223
 224 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
 225 {
 226         unsigned long tmp1, tmp2;
 227
 228         __asm__ __volatile__(
 229 "       mov             %0, %1\n"
 230 "1:     ldx             [%4], %2\n"
 231 "       casx            [%4], %2, %0\n"
 232 "       cmp             %2, %0\n"
 233 "       bne,a,pn        %%xcc, 1b\n"
 234 "        mov            %1, %0\n"
 235         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 236         : "0" (val), "r" (m)
 237         : "cc", "memory");
 238         return val;
 239 }
 240
 241 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 242
 243 extern void __xchg_called_with_bad_pointer(void);
 244
 245 static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
 246                                        int size)
 247 {
 248         switch (size) {
 249         case 4:
 250                 return xchg32(ptr, x);
 251         case 8:
 252                 return xchg64(ptr, x);
 253         };
 254         __xchg_called_with_bad_pointer();
 255         return x;
 256 }
 257
 258 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 259
 260 /*
 261  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 262  * store NEW in MEM.  Return the initial value in MEM.  Success is
 263  * indicated by comparing RETURN with OLD.
 264  */
 265
 266 #define __HAVE_ARCH_CMPXCHG 1
 267
 268 static inline unsigned long
 269 __cmpxchg_u32(volatile int *m, int old, int new)
 270 {
 271         __asm__ __volatile__("cas [%2], %3, %0"
 272                              : "=&r" (new)
 273                              : "0" (new), "r" (m), "r" (old)
 274                              : "memory");
 275
 276         return new;
 277 }
 278
 279 static inline unsigned long
 280 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
 281 {
 282         __asm__ __volatile__("casx [%2], %3, %0"
 283                              : "=&r" (new)
 284                              : "0" (new), "r" (m), "r" (old)
 285                              : "memory");
 286
 287         return new;
 288 }
 289
 290 /* This function doesn't exist, so you'll get a linker error
 291    if something tries to do an invalid cmpxchg().  */
 292 extern void __cmpxchg_called_with_bad_pointer(void);
 293
 294 static inline unsigned long
 295 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 296 {
 297         switch (size) {
 298                 case 4:
 299                         return __cmpxchg_u32(ptr, old, new);
 300                 case 8:
 301                         return __cmpxchg_u64(ptr, old, new);
 302         }
 303         __cmpxchg_called_with_bad_pointer();
 304         return old;
 305 }
 306
 307 #define cmpxchg(ptr,o,n)                                                 \
 308   ({                                                                     \
 309      __typeof__(*(ptr)) _o_ = (o);                                       \
 310      __typeof__(*(ptr)) _n_ = (n);                                       \
 311      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 312                                     (unsigned long)_n_, sizeof(*(ptr))); \
 313   })
 314
 315 /*
 316  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 317  * them available.
 318  */
 319
 320 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 321                                       unsigned long old,
 322                                       unsigned long new, int size)
 323 {
 324         switch (size) {
 325         case 4:
 326         case 8: return __cmpxchg(ptr, old, new, size);
 327         default:
 328                 return __cmpxchg_local_generic(ptr, old, new, size);
 329         }
 330
 331         return old;
 332 }
 333
 334 #define cmpxchg_local(ptr, o, n)                                        \
 335         ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
 336                         (unsigned long)(n), sizeof(*(ptr))))
 337 #define cmpxchg64_local(ptr, o, n)                                      \
 338   ({                                                                    \
 339         BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
 340         cmpxchg_local((ptr), (o), (n));                                 \
 341   })
 342
 343 #endif /* !(__ASSEMBLY__) */
 344
 345 #define arch_align_stack(x) (x)
 346
 347 #endif /* !(__SPARC64_SYSTEM_H) */