3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Derived from "arch/i386/mm/fault.c"
6 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
8 * Modified by Cort Dougan and Paul Mackerras.
10 * Modified for PPC64 by Dave Engebretsen (engebret@ibm.com)
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/signal.h>
19 #include <linux/sched.h>
20 #include <linux/kernel.h>
21 #include <linux/errno.h>
22 #include <linux/string.h>
23 #include <linux/types.h>
24 #include <linux/ptrace.h>
25 #include <linux/mman.h>
27 #include <linux/interrupt.h>
28 #include <linux/highmem.h>
29 #include <linux/module.h>
30 #include <linux/kprobes.h>
31 #include <linux/kdebug.h>
33 #include <asm/firmware.h>
35 #include <asm/pgtable.h>
37 #include <asm/mmu_context.h>
38 #include <asm/system.h>
39 #include <asm/uaccess.h>
40 #include <asm/tlbflush.h>
41 #include <asm/siginfo.h>
45 static inline int notify_page_fault(struct pt_regs
*regs
)
49 /* kprobe_running() needs smp_processor_id() */
50 if (!user_mode(regs
)) {
52 if (kprobe_running() && kprobe_fault_handler(regs
, 11))
60 static inline int notify_page_fault(struct pt_regs
*regs
)
67 * Check whether the instruction at regs->nip is a store using
68 * an update addressing form which will update r1.
70 static int store_updates_sp(struct pt_regs
*regs
)
74 if (get_user(inst
, (unsigned int __user
*)regs
->nip
))
76 /* check for 1 in the rA field */
77 if (((inst
>> 16) & 0x1f) != 1)
79 /* check major opcode */
87 case 62: /* std or stdu */
88 return (inst
& 3) == 1;
90 /* check minor opcode */
91 switch ((inst
>> 1) & 0x3ff) {
96 case 695: /* stfsux */
97 case 759: /* stfdux */
105 * For 600- and 800-family processors, the error_code parameter is DSISR
106 * for a data fault, SRR1 for an instruction fault. For 400-family processors
107 * the error_code parameter is ESR for a data fault, 0 for an instruction
109 * For 64-bit processors, the error_code parameter is
110 * - DSISR for a non-SLB data access fault,
111 * - SRR1 & 0x08000000 for a non-SLB instruction access fault
114 * The return value is 0 if the fault was handled, or the signal
115 * number if this is a kernel fault that can't be handled here.
117 int __kprobes
do_page_fault(struct pt_regs
*regs
, unsigned long address
,
118 unsigned long error_code
)
120 struct vm_area_struct
* vma
;
121 struct mm_struct
*mm
= current
->mm
;
123 int code
= SEGV_MAPERR
;
124 int is_write
= 0, ret
;
125 int trap
= TRAP(regs
);
126 int is_exec
= trap
== 0x400;
128 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
130 * Fortunately the bit assignments in SRR1 for an instruction
131 * fault and DSISR for a data fault are mostly the same for the
132 * bits we are interested in. But there are some bits which
133 * indicate errors in DSISR but can validly be set in SRR1.
136 error_code
&= 0x48200000;
138 is_write
= error_code
& DSISR_ISSTORE
;
140 is_write
= error_code
& ESR_DST
;
141 #endif /* CONFIG_4xx || CONFIG_BOOKE */
143 if (notify_page_fault(regs
))
146 if (unlikely(debugger_fault_handler(regs
)))
149 /* On a kernel SLB miss we can only check for a valid exception entry */
150 if (!user_mode(regs
) && (address
>= TASK_SIZE
))
153 #if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
154 if (error_code
& DSISR_DABRMATCH
) {
156 do_dabr(regs
, address
, error_code
);
159 #endif /* !(CONFIG_4xx || CONFIG_BOOKE)*/
161 if (in_atomic() || mm
== NULL
) {
162 if (!user_mode(regs
))
164 /* in_atomic() in user mode is really bad,
165 as is current->mm == NULL. */
166 printk(KERN_EMERG
"Page fault in user mode with "
167 "in_atomic() = %d mm = %p\n", in_atomic(), mm
);
168 printk(KERN_EMERG
"NIP = %lx MSR = %lx\n",
169 regs
->nip
, regs
->msr
);
170 die("Weird page fault", regs
, SIGSEGV
);
173 /* When running in the kernel we expect faults to occur only to
174 * addresses in user space. All other faults represent errors in the
175 * kernel and should generate an OOPS. Unfortunately, in the case of an
176 * erroneous fault occurring in a code path which already holds mmap_sem
177 * we will deadlock attempting to validate the fault against the
178 * address space. Luckily the kernel only validly references user
179 * space from well defined areas of code, which are listed in the
182 * As the vast majority of faults will be valid we will only perform
183 * the source reference check when there is a possibility of a deadlock.
184 * Attempt to lock the address space, if we cannot we then validate the
185 * source. If this is invalid we can skip the address space check,
186 * thus avoiding the deadlock.
188 if (!down_read_trylock(&mm
->mmap_sem
)) {
189 if (!user_mode(regs
) && !search_exception_tables(regs
->nip
))
190 goto bad_area_nosemaphore
;
192 down_read(&mm
->mmap_sem
);
195 vma
= find_vma(mm
, address
);
198 if (vma
->vm_start
<= address
)
200 if (!(vma
->vm_flags
& VM_GROWSDOWN
))
204 * N.B. The POWER/Open ABI allows programs to access up to
205 * 288 bytes below the stack pointer.
206 * The kernel signal delivery code writes up to about 1.5kB
207 * below the stack pointer (r1) before decrementing it.
208 * The exec code can write slightly over 640kB to the stack
209 * before setting the user r1. Thus we allow the stack to
210 * expand to 1MB without further checks.
212 if (address
+ 0x100000 < vma
->vm_end
) {
213 /* get user regs even if this fault is in kernel mode */
214 struct pt_regs
*uregs
= current
->thread
.regs
;
219 * A user-mode access to an address a long way below
220 * the stack pointer is only valid if the instruction
221 * is one which would update the stack pointer to the
222 * address accessed if the instruction completed,
223 * i.e. either stwu rs,n(r1) or stwux rs,r1,rb
224 * (or the byte, halfword, float or double forms).
226 * If we don't check this then any write to the area
227 * between the last mapped region and the stack will
228 * expand the stack rather than segfaulting.
230 if (address
+ 2048 < uregs
->gpr
[1]
231 && (!user_mode(regs
) || !store_updates_sp(regs
)))
234 if (expand_stack(vma
, address
))
239 #if defined(CONFIG_6xx)
240 if (error_code
& 0x95700000)
241 /* an error such as lwarx to I/O controller space,
242 address matching DABR, eciwx, etc. */
244 #endif /* CONFIG_6xx */
245 #if defined(CONFIG_8xx)
246 /* The MPC8xx seems to always set 0x80000000, which is
247 * "undefined". Of those that can be set, this is the only
248 * one which seems bad.
250 if (error_code
& 0x10000000)
251 /* Guarded storage error. */
253 #endif /* CONFIG_8xx */
256 #ifdef CONFIG_PPC_STD_MMU
257 /* Protection fault on exec go straight to failure on
258 * Hash based MMUs as they either don't support per-page
259 * execute permission, or if they do, it's handled already
260 * at the hash level. This test would probably have to
261 * be removed if we change the way this works to make hash
262 * processors use the same I/D cache coherency mechanism
265 if (error_code
& DSISR_PROTFAULT
)
267 #endif /* CONFIG_PPC_STD_MMU */
270 * Allow execution from readable areas if the MMU does not
271 * provide separate controls over reading and executing.
273 * Note: That code used to not be enabled for 4xx/BookE.
274 * It is now as I/D cache coherency for these is done at
275 * set_pte_at() time and I see no reason why the test
276 * below wouldn't be valid on those processors. This -may-
277 * break programs compiled with a really old ABI though.
279 if (!(vma
->vm_flags
& VM_EXEC
) &&
280 (cpu_has_feature(CPU_FTR_NOEXECUTE
) ||
281 !(vma
->vm_flags
& (VM_READ
| VM_WRITE
))))
284 } else if (is_write
) {
285 if (!(vma
->vm_flags
& VM_WRITE
))
289 /* protection fault */
290 if (error_code
& 0x08000000)
292 if (!(vma
->vm_flags
& (VM_READ
| VM_EXEC
| VM_WRITE
)))
297 * If for any reason at all we couldn't handle the fault,
298 * make sure we exit gracefully rather than endlessly redo
302 ret
= handle_mm_fault(mm
, vma
, address
, is_write
);
303 if (unlikely(ret
& VM_FAULT_ERROR
)) {
304 if (ret
& VM_FAULT_OOM
)
306 else if (ret
& VM_FAULT_SIGBUS
)
310 if (ret
& VM_FAULT_MAJOR
) {
312 #ifdef CONFIG_PPC_SMLPAR
313 if (firmware_has_feature(FW_FEATURE_CMO
)) {
315 get_lppaca()->page_ins
+= (1 << PAGE_FACTOR
);
321 up_read(&mm
->mmap_sem
);
325 up_read(&mm
->mmap_sem
);
327 bad_area_nosemaphore
:
328 /* User mode accesses cause a SIGSEGV */
329 if (user_mode(regs
)) {
330 _exception(SIGSEGV
, regs
, code
, address
);
334 if (is_exec
&& (error_code
& DSISR_PROTFAULT
)
335 && printk_ratelimit())
336 printk(KERN_CRIT
"kernel tried to execute NX-protected"
337 " page (%lx) - exploit attempt? (uid: %d)\n",
338 address
, current_uid());
343 * We ran out of memory, or some other thing happened to us that made
344 * us unable to handle the page fault gracefully.
347 up_read(&mm
->mmap_sem
);
348 if (is_global_init(current
)) {
350 down_read(&mm
->mmap_sem
);
353 printk("VM: killing process %s\n", current
->comm
);
355 do_group_exit(SIGKILL
);
359 up_read(&mm
->mmap_sem
);
360 if (user_mode(regs
)) {
361 info
.si_signo
= SIGBUS
;
363 info
.si_code
= BUS_ADRERR
;
364 info
.si_addr
= (void __user
*)address
;
365 force_sig_info(SIGBUS
, &info
, current
);
372 * bad_page_fault is called when we have a bad access from the kernel.
373 * It is called from the DSI and ISI handlers in head.S and from some
374 * of the procedures in traps.c.
376 void bad_page_fault(struct pt_regs
*regs
, unsigned long address
, int sig
)
378 const struct exception_table_entry
*entry
;
380 /* Are we prepared to handle this fault? */
381 if ((entry
= search_exception_tables(regs
->nip
)) != NULL
) {
382 regs
->nip
= entry
->fixup
;
386 /* kernel has accessed a bad area */
388 switch (regs
->trap
) {
391 printk(KERN_ALERT
"Unable to handle kernel paging request for "
392 "data at address 0x%08lx\n", regs
->dar
);
396 printk(KERN_ALERT
"Unable to handle kernel paging request for "
397 "instruction fetch\n");
400 printk(KERN_ALERT
"Unable to handle kernel paging request for "
404 printk(KERN_ALERT
"Faulting instruction address: 0x%08lx\n",
407 die("Kernel access of bad area", regs
, sig
);