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tty/serial: lay the foundations for the next set of reworks
[linux-2.6/linux-2.6-openrd.git] / drivers / char / synclink_gt.c
blob1a11717b1adc38ff519a7bfcd1ee919082003fe0
1 /*
2 * $Id: synclink_gt.c,v 4.50 2007/07/25 19:29:25 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink GT serial adapters.
5 *
6 * written by Paul Fulghum for Microgate Corporation
7 * paulkf@microgate.com
8 *
9 * Microgate and SyncLink are trademarks of Microgate Corporation
10 *
11 * This code is released under the GNU General Public License (GPL)
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
16 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
17 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
18 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
19 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
23 * OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 /*
27 * DEBUG OUTPUT DEFINITIONS
28 *
29 * uncomment lines below to enable specific types of debug output
30 *
31 * DBGINFO information - most verbose output
32 * DBGERR serious errors
33 * DBGBH bottom half service routine debugging
34 * DBGISR interrupt service routine debugging
35 * DBGDATA output receive and transmit data
36 * DBGTBUF output transmit DMA buffers and registers
37 * DBGRBUF output receive DMA buffers and registers
38 */
39
40 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
41 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
42 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
43 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
44 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
45 //#define DBGTBUF(info) dump_tbufs(info)
46 //#define DBGRBUF(info) dump_rbufs(info)
47
48
49 #include <linux/module.h>
50 #include <linux/version.h>
51 #include <linux/errno.h>
52 #include <linux/signal.h>
53 #include <linux/sched.h>
54 #include <linux/timer.h>
55 #include <linux/interrupt.h>
56 #include <linux/pci.h>
57 #include <linux/tty.h>
58 #include <linux/tty_flip.h>
59 #include <linux/serial.h>
60 #include <linux/major.h>
61 #include <linux/string.h>
62 #include <linux/fcntl.h>
63 #include <linux/ptrace.h>
64 #include <linux/ioport.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/netdevice.h>
68 #include <linux/vmalloc.h>
69 #include <linux/init.h>
70 #include <linux/delay.h>
71 #include <linux/ioctl.h>
72 #include <linux/termios.h>
73 #include <linux/bitops.h>
74 #include <linux/workqueue.h>
75 #include <linux/hdlc.h>
76 #include <linux/synclink.h>
77
78 #include <asm/system.h>
79 #include <asm/io.h>
80 #include <asm/irq.h>
81 #include <asm/dma.h>
82 #include <asm/types.h>
83 #include <asm/uaccess.h>
84
85 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
86 #define SYNCLINK_GENERIC_HDLC 1
87 #else
88 #define SYNCLINK_GENERIC_HDLC 0
89 #endif
90
91 /*
92 * module identification
93 */
94 static char *driver_name = "SyncLink GT";
95 static char *driver_version = "$Revision: 4.50 $";
96 static char *tty_driver_name = "synclink_gt";
97 static char *tty_dev_prefix = "ttySLG";
98 MODULE_LICENSE("GPL");
99 #define MGSL_MAGIC 0x5401
100 #define MAX_DEVICES 32
101
102 static struct pci_device_id pci_table[] = {
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
105 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
106 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
107 {0,}, /* terminate list */
108 };
109 MODULE_DEVICE_TABLE(pci, pci_table);
110
111 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
112 static void remove_one(struct pci_dev *dev);
113 static struct pci_driver pci_driver = {
114 .name = "synclink_gt",
115 .id_table = pci_table,
116 .probe = init_one,
117 .remove = __devexit_p(remove_one),
118 };
119
120 static bool pci_registered;
121
122 /*
123 * module configuration and status
124 */
125 static struct slgt_info *slgt_device_list;
126 static int slgt_device_count;
127
128 static int ttymajor;
129 static int debug_level;
130 static int maxframe[MAX_DEVICES];
131 static int dosyncppp[MAX_DEVICES];
132
133 module_param(ttymajor, int, 0);
134 module_param(debug_level, int, 0);
135 module_param_array(maxframe, int, NULL, 0);
136 module_param_array(dosyncppp, int, NULL, 0);
137
138 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
139 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
140 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
141 MODULE_PARM_DESC(dosyncppp, "Enable synchronous net device, 0=disable 1=enable");
142
143 /*
144 * tty support and callbacks
145 */
146 static struct tty_driver *serial_driver;
147
148 static int open(struct tty_struct *tty, struct file * filp);
149 static void close(struct tty_struct *tty, struct file * filp);
150 static void hangup(struct tty_struct *tty);
151 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
152
153 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
154 static void put_char(struct tty_struct *tty, unsigned char ch);
155 static void send_xchar(struct tty_struct *tty, char ch);
156 static void wait_until_sent(struct tty_struct *tty, int timeout);
157 static int write_room(struct tty_struct *tty);
158 static void flush_chars(struct tty_struct *tty);
159 static void flush_buffer(struct tty_struct *tty);
160 static void tx_hold(struct tty_struct *tty);
161 static void tx_release(struct tty_struct *tty);
162
163 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
164 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
165 static int chars_in_buffer(struct tty_struct *tty);
166 static void throttle(struct tty_struct * tty);
167 static void unthrottle(struct tty_struct * tty);
168 static void set_break(struct tty_struct *tty, int break_state);
169
170 /*
171 * generic HDLC support and callbacks
172 */
173 #if SYNCLINK_GENERIC_HDLC
174 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
175 static void hdlcdev_tx_done(struct slgt_info *info);
176 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
177 static int hdlcdev_init(struct slgt_info *info);
178 static void hdlcdev_exit(struct slgt_info *info);
179 #endif
180
181
182 /*
183 * device specific structures, macros and functions
184 */
185
186 #define SLGT_MAX_PORTS 4
187 #define SLGT_REG_SIZE 256
188
189 /*
190 * conditional wait facility
191 */
192 struct cond_wait {
193 struct cond_wait *next;
194 wait_queue_head_t q;
195 wait_queue_t wait;
196 unsigned int data;
197 };
198 static void init_cond_wait(struct cond_wait *w, unsigned int data);
199 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
200 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
201 static void flush_cond_wait(struct cond_wait **head);
202
203 /*
204 * DMA buffer descriptor and access macros
205 */
206 struct slgt_desc
207 {
208 __le16 count;
209 __le16 status;
210 __le32 pbuf; /* physical address of data buffer */
211 __le32 next; /* physical address of next descriptor */
212
213 /* driver book keeping */
214 char *buf; /* virtual address of data buffer */
215 unsigned int pdesc; /* physical address of this descriptor */
216 dma_addr_t buf_dma_addr;
217 };
218
219 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
220 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
221 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
222 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
223 #define desc_count(a) (le16_to_cpu((a).count))
224 #define desc_status(a) (le16_to_cpu((a).status))
225 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
226 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
227 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
228 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
229 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
230
231 struct _input_signal_events {
232 int ri_up;
233 int ri_down;
234 int dsr_up;
235 int dsr_down;
236 int dcd_up;
237 int dcd_down;
238 int cts_up;
239 int cts_down;
240 };
241
242 /*
243 * device instance data structure
244 */
245 struct slgt_info {
246 void *if_ptr; /* General purpose pointer (used by SPPP) */
247
248 struct slgt_info *next_device; /* device list link */
249
250 int magic;
251 int flags;
252
253 char device_name[25];
254 struct pci_dev *pdev;
255
256 int port_count; /* count of ports on adapter */
257 int adapter_num; /* adapter instance number */
258 int port_num; /* port instance number */
259
260 /* array of pointers to port contexts on this adapter */
261 struct slgt_info *port_array[SLGT_MAX_PORTS];
262
263 int count; /* count of opens */
264 int line; /* tty line instance number */
265 unsigned short close_delay;
266 unsigned short closing_wait; /* time to wait before closing */
267
268 struct mgsl_icount icount;
269
270 struct tty_struct *tty;
271 int timeout;
272 int x_char; /* xon/xoff character */
273 int blocked_open; /* # of blocked opens */
274 unsigned int read_status_mask;
275 unsigned int ignore_status_mask;
276
277 wait_queue_head_t open_wait;
278 wait_queue_head_t close_wait;
279
280 wait_queue_head_t status_event_wait_q;
281 wait_queue_head_t event_wait_q;
282 struct timer_list tx_timer;
283 struct timer_list rx_timer;
284
285 unsigned int gpio_present;
286 struct cond_wait *gpio_wait_q;
287
288 spinlock_t lock; /* spinlock for synchronizing with ISR */
289
290 struct work_struct task;
291 u32 pending_bh;
292 bool bh_requested;
293 bool bh_running;
294
295 int isr_overflow;
296 bool irq_requested; /* true if IRQ requested */
297 bool irq_occurred; /* for diagnostics use */
298
299 /* device configuration */
300
301 unsigned int bus_type;
302 unsigned int irq_level;
303 unsigned long irq_flags;
304
305 unsigned char __iomem * reg_addr; /* memory mapped registers address */
306 u32 phys_reg_addr;
307 bool reg_addr_requested;
308
309 MGSL_PARAMS params; /* communications parameters */
310 u32 idle_mode;
311 u32 max_frame_size; /* as set by device config */
312
313 unsigned int raw_rx_size;
314 unsigned int if_mode;
315
316 /* device status */
317
318 bool rx_enabled;
319 bool rx_restart;
320
321 bool tx_enabled;
322 bool tx_active;
323
324 unsigned char signals; /* serial signal states */
325 int init_error; /* initialization error */
326
327 unsigned char *tx_buf;
328 int tx_count;
329
330 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
331 char char_buf[MAX_ASYNC_BUFFER_SIZE];
332 bool drop_rts_on_tx_done;
333 struct _input_signal_events input_signal_events;
334
335 int dcd_chkcount; /* check counts to prevent */
336 int cts_chkcount; /* too many IRQs if a signal */
337 int dsr_chkcount; /* is floating */
338 int ri_chkcount;
339
340 char *bufs; /* virtual address of DMA buffer lists */
341 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
342
343 unsigned int rbuf_count;
344 struct slgt_desc *rbufs;
345 unsigned int rbuf_current;
346 unsigned int rbuf_index;
347
348 unsigned int tbuf_count;
349 struct slgt_desc *tbufs;
350 unsigned int tbuf_current;
351 unsigned int tbuf_start;
352
353 unsigned char *tmp_rbuf;
354 unsigned int tmp_rbuf_count;
355
356 /* SPPP/Cisco HDLC device parts */
357
358 int netcount;
359 int dosyncppp;
360 spinlock_t netlock;
361 #if SYNCLINK_GENERIC_HDLC
362 struct net_device *netdev;
363 #endif
364
365 };
366
367 static MGSL_PARAMS default_params = {
368 .mode = MGSL_MODE_HDLC,
369 .loopback = 0,
370 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
371 .encoding = HDLC_ENCODING_NRZI_SPACE,
372 .clock_speed = 0,
373 .addr_filter = 0xff,
374 .crc_type = HDLC_CRC_16_CCITT,
375 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
376 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
377 .data_rate = 9600,
378 .data_bits = 8,
379 .stop_bits = 1,
380 .parity = ASYNC_PARITY_NONE
381 };
382
383
384 #define BH_RECEIVE 1
385 #define BH_TRANSMIT 2
386 #define BH_STATUS 4
387 #define IO_PIN_SHUTDOWN_LIMIT 100
388
389 #define DMABUFSIZE 256
390 #define DESC_LIST_SIZE 4096
391
392 #define MASK_PARITY BIT1
393 #define MASK_FRAMING BIT0
394 #define MASK_BREAK BIT14
395 #define MASK_OVERRUN BIT4
396
397 #define GSR 0x00 /* global status */
398 #define JCR 0x04 /* JTAG control */
399 #define IODR 0x08 /* GPIO direction */
400 #define IOER 0x0c /* GPIO interrupt enable */
401 #define IOVR 0x10 /* GPIO value */
402 #define IOSR 0x14 /* GPIO interrupt status */
403 #define TDR 0x80 /* tx data */
404 #define RDR 0x80 /* rx data */
405 #define TCR 0x82 /* tx control */
406 #define TIR 0x84 /* tx idle */
407 #define TPR 0x85 /* tx preamble */
408 #define RCR 0x86 /* rx control */
409 #define VCR 0x88 /* V.24 control */
410 #define CCR 0x89 /* clock control */
411 #define BDR 0x8a /* baud divisor */
412 #define SCR 0x8c /* serial control */
413 #define SSR 0x8e /* serial status */
414 #define RDCSR 0x90 /* rx DMA control/status */
415 #define TDCSR 0x94 /* tx DMA control/status */
416 #define RDDAR 0x98 /* rx DMA descriptor address */
417 #define TDDAR 0x9c /* tx DMA descriptor address */
418
419 #define RXIDLE BIT14
420 #define RXBREAK BIT14
421 #define IRQ_TXDATA BIT13
422 #define IRQ_TXIDLE BIT12
423 #define IRQ_TXUNDER BIT11 /* HDLC */
424 #define IRQ_RXDATA BIT10
425 #define IRQ_RXIDLE BIT9 /* HDLC */
426 #define IRQ_RXBREAK BIT9 /* async */
427 #define IRQ_RXOVER BIT8
428 #define IRQ_DSR BIT7
429 #define IRQ_CTS BIT6
430 #define IRQ_DCD BIT5
431 #define IRQ_RI BIT4
432 #define IRQ_ALL 0x3ff0
433 #define IRQ_MASTER BIT0
434
435 #define slgt_irq_on(info, mask) \
436 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
437 #define slgt_irq_off(info, mask) \
438 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
439
440 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
441 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
442 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
443 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
444 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
445 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
446
447 static void msc_set_vcr(struct slgt_info *info);
448
449 static int startup(struct slgt_info *info);
450 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
451 static void shutdown(struct slgt_info *info);
452 static void program_hw(struct slgt_info *info);
453 static void change_params(struct slgt_info *info);
454
455 static int register_test(struct slgt_info *info);
456 static int irq_test(struct slgt_info *info);
457 static int loopback_test(struct slgt_info *info);
458 static int adapter_test(struct slgt_info *info);
459
460 static void reset_adapter(struct slgt_info *info);
461 static void reset_port(struct slgt_info *info);
462 static void async_mode(struct slgt_info *info);
463 static void sync_mode(struct slgt_info *info);
464
465 static void rx_stop(struct slgt_info *info);
466 static void rx_start(struct slgt_info *info);
467 static void reset_rbufs(struct slgt_info *info);
468 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
469 static void rdma_reset(struct slgt_info *info);
470 static bool rx_get_frame(struct slgt_info *info);
471 static bool rx_get_buf(struct slgt_info *info);
472
473 static void tx_start(struct slgt_info *info);
474 static void tx_stop(struct slgt_info *info);
475 static void tx_set_idle(struct slgt_info *info);
476 static unsigned int free_tbuf_count(struct slgt_info *info);
477 static void reset_tbufs(struct slgt_info *info);
478 static void tdma_reset(struct slgt_info *info);
479 static void tdma_start(struct slgt_info *info);
480 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
481
482 static void get_signals(struct slgt_info *info);
483 static void set_signals(struct slgt_info *info);
484 static void enable_loopback(struct slgt_info *info);
485 static void set_rate(struct slgt_info *info, u32 data_rate);
486
487 static int bh_action(struct slgt_info *info);
488 static void bh_handler(struct work_struct *work);
489 static void bh_transmit(struct slgt_info *info);
490 static void isr_serial(struct slgt_info *info);
491 static void isr_rdma(struct slgt_info *info);
492 static void isr_txeom(struct slgt_info *info, unsigned short status);
493 static void isr_tdma(struct slgt_info *info);
494
495 static int alloc_dma_bufs(struct slgt_info *info);
496 static void free_dma_bufs(struct slgt_info *info);
497 static int alloc_desc(struct slgt_info *info);
498 static void free_desc(struct slgt_info *info);
499 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
500 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
501
502 static int alloc_tmp_rbuf(struct slgt_info *info);
503 static void free_tmp_rbuf(struct slgt_info *info);
504
505 static void tx_timeout(unsigned long context);
506 static void rx_timeout(unsigned long context);
507
508 /*
509 * ioctl handlers
510 */
511 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
512 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
513 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
514 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
515 static int set_txidle(struct slgt_info *info, int idle_mode);
516 static int tx_enable(struct slgt_info *info, int enable);
517 static int tx_abort(struct slgt_info *info);
518 static int rx_enable(struct slgt_info *info, int enable);
519 static int modem_input_wait(struct slgt_info *info,int arg);
520 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
521 static int tiocmget(struct tty_struct *tty, struct file *file);
522 static int tiocmset(struct tty_struct *tty, struct file *file,
523 unsigned int set, unsigned int clear);
524 static void set_break(struct tty_struct *tty, int break_state);
525 static int get_interface(struct slgt_info *info, int __user *if_mode);
526 static int set_interface(struct slgt_info *info, int if_mode);
527 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
528 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
529 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
530
531 /*
532 * driver functions
533 */
534 static void add_device(struct slgt_info *info);
535 static void device_init(int adapter_num, struct pci_dev *pdev);
536 static int claim_resources(struct slgt_info *info);
537 static void release_resources(struct slgt_info *info);
538
539 /*
540 * DEBUG OUTPUT CODE
541 */
542 #ifndef DBGINFO
543 #define DBGINFO(fmt)
544 #endif
545 #ifndef DBGERR
546 #define DBGERR(fmt)
547 #endif
548 #ifndef DBGBH
549 #define DBGBH(fmt)
550 #endif
551 #ifndef DBGISR
552 #define DBGISR(fmt)
553 #endif
554
555 #ifdef DBGDATA
556 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
557 {
558 int i;
559 int linecount;
560 printk("%s %s data:\n",info->device_name, label);
561 while(count) {
562 linecount = (count > 16) ? 16 : count;
563 for(i=0; i < linecount; i++)
564 printk("%02X ",(unsigned char)data[i]);
565 for(;i<17;i++)
566 printk(" ");
567 for(i=0;i<linecount;i++) {
568 if (data[i]>=040 && data[i]<=0176)
569 printk("%c",data[i]);
570 else
571 printk(".");
572 }
573 printk("\n");
574 data += linecount;
575 count -= linecount;
576 }
577 }
578 #else
579 #define DBGDATA(info, buf, size, label)
580 #endif
581
582 #ifdef DBGTBUF
583 static void dump_tbufs(struct slgt_info *info)
584 {
585 int i;
586 printk("tbuf_current=%d\n", info->tbuf_current);
587 for (i=0 ; i < info->tbuf_count ; i++) {
588 printk("%d: count=%04X status=%04X\n",
589 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
590 }
591 }
592 #else
593 #define DBGTBUF(info)
594 #endif
595
596 #ifdef DBGRBUF
597 static void dump_rbufs(struct slgt_info *info)
598 {
599 int i;
600 printk("rbuf_current=%d\n", info->rbuf_current);
601 for (i=0 ; i < info->rbuf_count ; i++) {
602 printk("%d: count=%04X status=%04X\n",
603 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
604 }
605 }
606 #else
607 #define DBGRBUF(info)
608 #endif
609
610 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
611 {
612 #ifdef SANITY_CHECK
613 if (!info) {
614 printk("null struct slgt_info for (%s) in %s\n", devname, name);
615 return 1;
616 }
617 if (info->magic != MGSL_MAGIC) {
618 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
619 return 1;
620 }
621 #else
622 if (!info)
623 return 1;
624 #endif
625 return 0;
626 }
627
628 /**
629 * line discipline callback wrappers
630 *
631 * The wrappers maintain line discipline references
632 * while calling into the line discipline.
633 *
634 * ldisc_receive_buf - pass receive data to line discipline
635 */
636 static void ldisc_receive_buf(struct tty_struct *tty,
637 const __u8 *data, char *flags, int count)
638 {
639 struct tty_ldisc *ld;
640 if (!tty)
641 return;
642 ld = tty_ldisc_ref(tty);
643 if (ld) {
644 if (ld->receive_buf)
645 ld->receive_buf(tty, data, flags, count);
646 tty_ldisc_deref(ld);
647 }
648 }
649
650 /* tty callbacks */
651
652 static int open(struct tty_struct *tty, struct file *filp)
653 {
654 struct slgt_info *info;
655 int retval, line;
656 unsigned long flags;
657
658 line = tty->index;
659 if ((line < 0) || (line >= slgt_device_count)) {
660 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
661 return -ENODEV;
662 }
663
664 info = slgt_device_list;
665 while(info && info->line != line)
666 info = info->next_device;
667 if (sanity_check(info, tty->name, "open"))
668 return -ENODEV;
669 if (info->init_error) {
670 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
671 return -ENODEV;
672 }
673
674 tty->driver_data = info;
675 info->tty = tty;
676
677 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->count));
678
679 /* If port is closing, signal caller to try again */
680 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
681 if (info->flags & ASYNC_CLOSING)
682 interruptible_sleep_on(&info->close_wait);
683 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
684 -EAGAIN : -ERESTARTSYS);
685 goto cleanup;
686 }
687
688 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
689
690 spin_lock_irqsave(&info->netlock, flags);
691 if (info->netcount) {
692 retval = -EBUSY;
693 spin_unlock_irqrestore(&info->netlock, flags);
694 goto cleanup;
695 }
696 info->count++;
697 spin_unlock_irqrestore(&info->netlock, flags);
698
699 if (info->count == 1) {
700 /* 1st open on this device, init hardware */
701 retval = startup(info);
702 if (retval < 0)
703 goto cleanup;
704 }
705
706 retval = block_til_ready(tty, filp, info);
707 if (retval) {
708 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
709 goto cleanup;
710 }
711
712 retval = 0;
713
714 cleanup:
715 if (retval) {
716 if (tty->count == 1)
717 info->tty = NULL; /* tty layer will release tty struct */
718 if(info->count)
719 info->count--;
720 }
721
722 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
723 return retval;
724 }
725
726 static void close(struct tty_struct *tty, struct file *filp)
727 {
728 struct slgt_info *info = tty->driver_data;
729
730 if (sanity_check(info, tty->name, "close"))
731 return;
732 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->count));
733
734 if (!info->count)
735 return;
736
737 if (tty_hung_up_p(filp))
738 goto cleanup;
739
740 if ((tty->count == 1) && (info->count != 1)) {
741 /*
742 * tty->count is 1 and the tty structure will be freed.
743 * info->count should be one in this case.
744 * if it's not, correct it so that the port is shutdown.
745 */
746 DBGERR(("%s close: bad refcount; tty->count=1, "
747 "info->count=%d\n", info->device_name, info->count));
748 info->count = 1;
749 }
750
751 info->count--;
752
753 /* if at least one open remaining, leave hardware active */
754 if (info->count)
755 goto cleanup;
756
757 info->flags |= ASYNC_CLOSING;
758
759 /* set tty->closing to notify line discipline to
760 * only process XON/XOFF characters. Only the N_TTY
761 * discipline appears to use this (ppp does not).
762 */
763 tty->closing = 1;
764
765 /* wait for transmit data to clear all layers */
766
767 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
768 DBGINFO(("%s call tty_wait_until_sent\n", info->device_name));
769 tty_wait_until_sent(tty, info->closing_wait);
770 }
771
772 if (info->flags & ASYNC_INITIALIZED)
773 wait_until_sent(tty, info->timeout);
774 flush_buffer(tty);
775 tty_ldisc_flush(tty);
776
777 shutdown(info);
778
779 tty->closing = 0;
780 info->tty = NULL;
781
782 if (info->blocked_open) {
783 if (info->close_delay) {
784 msleep_interruptible(jiffies_to_msecs(info->close_delay));
785 }
786 wake_up_interruptible(&info->open_wait);
787 }
788
789 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
790
791 wake_up_interruptible(&info->close_wait);
792
793 cleanup:
794 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->count));
795 }
796
797 static void hangup(struct tty_struct *tty)
798 {
799 struct slgt_info *info = tty->driver_data;
800
801 if (sanity_check(info, tty->name, "hangup"))
802 return;
803 DBGINFO(("%s hangup\n", info->device_name));
804
805 flush_buffer(tty);
806 shutdown(info);
807
808 info->count = 0;
809 info->flags &= ~ASYNC_NORMAL_ACTIVE;
810 info->tty = NULL;
811
812 wake_up_interruptible(&info->open_wait);
813 }
814
815 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
816 {
817 struct slgt_info *info = tty->driver_data;
818 unsigned long flags;
819
820 DBGINFO(("%s set_termios\n", tty->driver->name));
821
822 change_params(info);
823
824 /* Handle transition to B0 status */
825 if (old_termios->c_cflag & CBAUD &&
826 !(tty->termios->c_cflag & CBAUD)) {
827 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
828 spin_lock_irqsave(&info->lock,flags);
829 set_signals(info);
830 spin_unlock_irqrestore(&info->lock,flags);
831 }
832
833 /* Handle transition away from B0 status */
834 if (!(old_termios->c_cflag & CBAUD) &&
835 tty->termios->c_cflag & CBAUD) {
836 info->signals |= SerialSignal_DTR;
837 if (!(tty->termios->c_cflag & CRTSCTS) ||
838 !test_bit(TTY_THROTTLED, &tty->flags)) {
839 info->signals |= SerialSignal_RTS;
840 }
841 spin_lock_irqsave(&info->lock,flags);
842 set_signals(info);
843 spin_unlock_irqrestore(&info->lock,flags);
844 }
845
846 /* Handle turning off CRTSCTS */
847 if (old_termios->c_cflag & CRTSCTS &&
848 !(tty->termios->c_cflag & CRTSCTS)) {
849 tty->hw_stopped = 0;
850 tx_release(tty);
851 }
852 }
853
854 static int write(struct tty_struct *tty,
855 const unsigned char *buf, int count)
856 {
857 int ret = 0;
858 struct slgt_info *info = tty->driver_data;
859 unsigned long flags;
860
861 if (sanity_check(info, tty->name, "write"))
862 goto cleanup;
863 DBGINFO(("%s write count=%d\n", info->device_name, count));
864
865 if (!info->tx_buf)
866 goto cleanup;
867
868 if (count > info->max_frame_size) {
869 ret = -EIO;
870 goto cleanup;
871 }
872
873 if (!count)
874 goto cleanup;
875
876 if (info->params.mode == MGSL_MODE_RAW ||
877 info->params.mode == MGSL_MODE_MONOSYNC ||
878 info->params.mode == MGSL_MODE_BISYNC) {
879 unsigned int bufs_needed = (count/DMABUFSIZE);
880 unsigned int bufs_free = free_tbuf_count(info);
881 if (count % DMABUFSIZE)
882 ++bufs_needed;
883 if (bufs_needed > bufs_free)
884 goto cleanup;
885 } else {
886 if (info->tx_active)
887 goto cleanup;
888 if (info->tx_count) {
889 /* send accumulated data from send_char() calls */
890 /* as frame and wait before accepting more data. */
891 tx_load(info, info->tx_buf, info->tx_count);
892 goto start;
893 }
894 }
895
896 ret = info->tx_count = count;
897 tx_load(info, buf, count);
898 goto start;
899
900 start:
901 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
902 spin_lock_irqsave(&info->lock,flags);
903 if (!info->tx_active)
904 tx_start(info);
905 else
906 tdma_start(info);
907 spin_unlock_irqrestore(&info->lock,flags);
908 }
909
910 cleanup:
911 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
912 return ret;
913 }
914
915 static void put_char(struct tty_struct *tty, unsigned char ch)
916 {
917 struct slgt_info *info = tty->driver_data;
918 unsigned long flags;
919
920 if (sanity_check(info, tty->name, "put_char"))
921 return;
922 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
923 if (!info->tx_buf)
924 return;
925 spin_lock_irqsave(&info->lock,flags);
926 if (!info->tx_active && (info->tx_count < info->max_frame_size))
927 info->tx_buf[info->tx_count++] = ch;
928 spin_unlock_irqrestore(&info->lock,flags);
929 }
930
931 static void send_xchar(struct tty_struct *tty, char ch)
932 {
933 struct slgt_info *info = tty->driver_data;
934 unsigned long flags;
935
936 if (sanity_check(info, tty->name, "send_xchar"))
937 return;
938 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
939 info->x_char = ch;
940 if (ch) {
941 spin_lock_irqsave(&info->lock,flags);
942 if (!info->tx_enabled)
943 tx_start(info);
944 spin_unlock_irqrestore(&info->lock,flags);
945 }
946 }
947
948 static void wait_until_sent(struct tty_struct *tty, int timeout)
949 {
950 struct slgt_info *info = tty->driver_data;
951 unsigned long orig_jiffies, char_time;
952
953 if (!info )
954 return;
955 if (sanity_check(info, tty->name, "wait_until_sent"))
956 return;
957 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
958 if (!(info->flags & ASYNC_INITIALIZED))
959 goto exit;
960
961 orig_jiffies = jiffies;
962
963 /* Set check interval to 1/5 of estimated time to
964 * send a character, and make it at least 1. The check
965 * interval should also be less than the timeout.
966 * Note: use tight timings here to satisfy the NIST-PCTS.
967 */
968
969 lock_kernel();
970
971 if (info->params.data_rate) {
972 char_time = info->timeout/(32 * 5);
973 if (!char_time)
974 char_time++;
975 } else
976 char_time = 1;
977
978 if (timeout)
979 char_time = min_t(unsigned long, char_time, timeout);
980
981 while (info->tx_active) {
982 msleep_interruptible(jiffies_to_msecs(char_time));
983 if (signal_pending(current))
984 break;
985 if (timeout && time_after(jiffies, orig_jiffies + timeout))
986 break;
987 }
988 unlock_kernel();
989
990 exit:
991 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
992 }
993
994 static int write_room(struct tty_struct *tty)
995 {
996 struct slgt_info *info = tty->driver_data;
997 int ret;
998
999 if (sanity_check(info, tty->name, "write_room"))
1000 return 0;
1001 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1002 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
1003 return ret;
1004 }
1005
1006 static void flush_chars(struct tty_struct *tty)
1007 {
1008 struct slgt_info *info = tty->driver_data;
1009 unsigned long flags;
1010
1011 if (sanity_check(info, tty->name, "flush_chars"))
1012 return;
1013 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
1014
1015 if (info->tx_count <= 0 || tty->stopped ||
1016 tty->hw_stopped || !info->tx_buf)
1017 return;
1018
1019 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
1020
1021 spin_lock_irqsave(&info->lock,flags);
1022 if (!info->tx_active && info->tx_count) {
1023 tx_load(info, info->tx_buf,info->tx_count);
1024 tx_start(info);
1025 }
1026 spin_unlock_irqrestore(&info->lock,flags);
1027 }
1028
1029 static void flush_buffer(struct tty_struct *tty)
1030 {
1031 struct slgt_info *info = tty->driver_data;
1032 unsigned long flags;
1033
1034 if (sanity_check(info, tty->name, "flush_buffer"))
1035 return;
1036 DBGINFO(("%s flush_buffer\n", info->device_name));
1037
1038 spin_lock_irqsave(&info->lock,flags);
1039 if (!info->tx_active)
1040 info->tx_count = 0;
1041 spin_unlock_irqrestore(&info->lock,flags);
1042
1043 tty_wakeup(tty);
1044 }
1045
1046 /*
1047 * throttle (stop) transmitter
1048 */
1049 static void tx_hold(struct tty_struct *tty)
1050 {
1051 struct slgt_info *info = tty->driver_data;
1052 unsigned long flags;
1053
1054 if (sanity_check(info, tty->name, "tx_hold"))
1055 return;
1056 DBGINFO(("%s tx_hold\n", info->device_name));
1057 spin_lock_irqsave(&info->lock,flags);
1058 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1059 tx_stop(info);
1060 spin_unlock_irqrestore(&info->lock,flags);
1061 }
1062
1063 /*
1064 * release (start) transmitter
1065 */
1066 static void tx_release(struct tty_struct *tty)
1067 {
1068 struct slgt_info *info = tty->driver_data;
1069 unsigned long flags;
1070
1071 if (sanity_check(info, tty->name, "tx_release"))
1072 return;
1073 DBGINFO(("%s tx_release\n", info->device_name));
1074 spin_lock_irqsave(&info->lock,flags);
1075 if (!info->tx_active && info->tx_count) {
1076 tx_load(info, info->tx_buf, info->tx_count);
1077 tx_start(info);
1078 }
1079 spin_unlock_irqrestore(&info->lock,flags);
1080 }
1081
1082 /*
1083 * Service an IOCTL request
1084 *
1085 * Arguments
1086 *
1087 * tty pointer to tty instance data
1088 * file pointer to associated file object for device
1089 * cmd IOCTL command code
1090 * arg command argument/context
1091 *
1092 * Return 0 if success, otherwise error code
1093 */
1094 static int ioctl(struct tty_struct *tty, struct file *file,
1095 unsigned int cmd, unsigned long arg)
1096 {
1097 struct slgt_info *info = tty->driver_data;
1098 struct mgsl_icount cnow; /* kernel counter temps */
1099 struct serial_icounter_struct __user *p_cuser; /* user space */
1100 unsigned long flags;
1101 void __user *argp = (void __user *)arg;
1102 int ret;
1103
1104 if (sanity_check(info, tty->name, "ioctl"))
1105 return -ENODEV;
1106 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1107
1108 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1109 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1110 if (tty->flags & (1 << TTY_IO_ERROR))
1111 return -EIO;
1112 }
1113
1114 lock_kernel();
1115
1116 switch (cmd) {
1117 case MGSL_IOCGPARAMS:
1118 ret = get_params(info, argp);
1119 break;
1120 case MGSL_IOCSPARAMS:
1121 ret = set_params(info, argp);
1122 break;
1123 case MGSL_IOCGTXIDLE:
1124 ret = get_txidle(info, argp);
1125 break;
1126 case MGSL_IOCSTXIDLE:
1127 ret = set_txidle(info, (int)arg);
1128 break;
1129 case MGSL_IOCTXENABLE:
1130 ret = tx_enable(info, (int)arg);
1131 break;
1132 case MGSL_IOCRXENABLE:
1133 ret = rx_enable(info, (int)arg);
1134 break;
1135 case MGSL_IOCTXABORT:
1136 ret = tx_abort(info);
1137 break;
1138 case MGSL_IOCGSTATS:
1139 ret = get_stats(info, argp);
1140 break;
1141 case MGSL_IOCWAITEVENT:
1142 ret = wait_mgsl_event(info, argp);
1143 break;
1144 case TIOCMIWAIT:
1145 ret = modem_input_wait(info,(int)arg);
1146 break;
1147 case MGSL_IOCGIF:
1148 ret = get_interface(info, argp);
1149 break;
1150 case MGSL_IOCSIF:
1151 ret = set_interface(info,(int)arg);
1152 break;
1153 case MGSL_IOCSGPIO:
1154 ret = set_gpio(info, argp);
1155 break;
1156 case MGSL_IOCGGPIO:
1157 ret = get_gpio(info, argp);
1158 break;
1159 case MGSL_IOCWAITGPIO:
1160 ret = wait_gpio(info, argp);
1161 break;
1162 case TIOCGICOUNT:
1163 spin_lock_irqsave(&info->lock,flags);
1164 cnow = info->icount;
1165 spin_unlock_irqrestore(&info->lock,flags);
1166 p_cuser = argp;
1167 if (put_user(cnow.cts, &p_cuser->cts) ||
1168 put_user(cnow.dsr, &p_cuser->dsr) ||
1169 put_user(cnow.rng, &p_cuser->rng) ||
1170 put_user(cnow.dcd, &p_cuser->dcd) ||
1171 put_user(cnow.rx, &p_cuser->rx) ||
1172 put_user(cnow.tx, &p_cuser->tx) ||
1173 put_user(cnow.frame, &p_cuser->frame) ||
1174 put_user(cnow.overrun, &p_cuser->overrun) ||
1175 put_user(cnow.parity, &p_cuser->parity) ||
1176 put_user(cnow.brk, &p_cuser->brk) ||
1177 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1178 ret = -EFAULT;
1179 ret = 0;
1180 break;
1181 default:
1182 ret = -ENOIOCTLCMD;
1183 }
1184 unlock_kernel();
1185 return ret;
1186 }
1187
1188 /*
1189 * support for 32 bit ioctl calls on 64 bit systems
1190 */
1191 #ifdef CONFIG_COMPAT
1192 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1193 {
1194 struct MGSL_PARAMS32 tmp_params;
1195
1196 DBGINFO(("%s get_params32\n", info->device_name));
1197 tmp_params.mode = (compat_ulong_t)info->params.mode;
1198 tmp_params.loopback = info->params.loopback;
1199 tmp_params.flags = info->params.flags;
1200 tmp_params.encoding = info->params.encoding;
1201 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1202 tmp_params.addr_filter = info->params.addr_filter;
1203 tmp_params.crc_type = info->params.crc_type;
1204 tmp_params.preamble_length = info->params.preamble_length;
1205 tmp_params.preamble = info->params.preamble;
1206 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1207 tmp_params.data_bits = info->params.data_bits;
1208 tmp_params.stop_bits = info->params.stop_bits;
1209 tmp_params.parity = info->params.parity;
1210 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1211 return -EFAULT;
1212 return 0;
1213 }
1214
1215 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1216 {
1217 struct MGSL_PARAMS32 tmp_params;
1218
1219 DBGINFO(("%s set_params32\n", info->device_name));
1220 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1221 return -EFAULT;
1222
1223 spin_lock(&info->lock);
1224 info->params.mode = tmp_params.mode;
1225 info->params.loopback = tmp_params.loopback;
1226 info->params.flags = tmp_params.flags;
1227 info->params.encoding = tmp_params.encoding;
1228 info->params.clock_speed = tmp_params.clock_speed;
1229 info->params.addr_filter = tmp_params.addr_filter;
1230 info->params.crc_type = tmp_params.crc_type;
1231 info->params.preamble_length = tmp_params.preamble_length;
1232 info->params.preamble = tmp_params.preamble;
1233 info->params.data_rate = tmp_params.data_rate;
1234 info->params.data_bits = tmp_params.data_bits;
1235 info->params.stop_bits = tmp_params.stop_bits;
1236 info->params.parity = tmp_params.parity;
1237 spin_unlock(&info->lock);
1238
1239 change_params(info);
1240
1241 return 0;
1242 }
1243
1244 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1245 unsigned int cmd, unsigned long arg)
1246 {
1247 struct slgt_info *info = tty->driver_data;
1248 int rc = -ENOIOCTLCMD;
1249
1250 if (sanity_check(info, tty->name, "compat_ioctl"))
1251 return -ENODEV;
1252 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1253
1254 switch (cmd) {
1255
1256 case MGSL_IOCSPARAMS32:
1257 rc = set_params32(info, compat_ptr(arg));
1258 break;
1259
1260 case MGSL_IOCGPARAMS32:
1261 rc = get_params32(info, compat_ptr(arg));
1262 break;
1263
1264 case MGSL_IOCGPARAMS:
1265 case MGSL_IOCSPARAMS:
1266 case MGSL_IOCGTXIDLE:
1267 case MGSL_IOCGSTATS:
1268 case MGSL_IOCWAITEVENT:
1269 case MGSL_IOCGIF:
1270 case MGSL_IOCSGPIO:
1271 case MGSL_IOCGGPIO:
1272 case MGSL_IOCWAITGPIO:
1273 case TIOCGICOUNT:
1274 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1275 break;
1276
1277 case MGSL_IOCSTXIDLE:
1278 case MGSL_IOCTXENABLE:
1279 case MGSL_IOCRXENABLE:
1280 case MGSL_IOCTXABORT:
1281 case TIOCMIWAIT:
1282 case MGSL_IOCSIF:
1283 rc = ioctl(tty, file, cmd, arg);
1284 break;
1285 }
1286
1287 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1288 return rc;
1289 }
1290 #else
1291 #define slgt_compat_ioctl NULL
1292 #endif /* ifdef CONFIG_COMPAT */
1293
1294 /*
1295 * proc fs support
1296 */
1297 static inline int line_info(char *buf, struct slgt_info *info)
1298 {
1299 char stat_buf[30];
1300 int ret;
1301 unsigned long flags;
1302
1303 ret = sprintf(buf, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1304 info->device_name, info->phys_reg_addr,
1305 info->irq_level, info->max_frame_size);
1306
1307 /* output current serial signal states */
1308 spin_lock_irqsave(&info->lock,flags);
1309 get_signals(info);
1310 spin_unlock_irqrestore(&info->lock,flags);
1311
1312 stat_buf[0] = 0;
1313 stat_buf[1] = 0;
1314 if (info->signals & SerialSignal_RTS)
1315 strcat(stat_buf, "|RTS");
1316 if (info->signals & SerialSignal_CTS)
1317 strcat(stat_buf, "|CTS");
1318 if (info->signals & SerialSignal_DTR)
1319 strcat(stat_buf, "|DTR");
1320 if (info->signals & SerialSignal_DSR)
1321 strcat(stat_buf, "|DSR");
1322 if (info->signals & SerialSignal_DCD)
1323 strcat(stat_buf, "|CD");
1324 if (info->signals & SerialSignal_RI)
1325 strcat(stat_buf, "|RI");
1326
1327 if (info->params.mode != MGSL_MODE_ASYNC) {
1328 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1329 info->icount.txok, info->icount.rxok);
1330 if (info->icount.txunder)
1331 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1332 if (info->icount.txabort)
1333 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1334 if (info->icount.rxshort)
1335 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1336 if (info->icount.rxlong)
1337 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1338 if (info->icount.rxover)
1339 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1340 if (info->icount.rxcrc)
1341 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
1342 } else {
1343 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1344 info->icount.tx, info->icount.rx);
1345 if (info->icount.frame)
1346 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1347 if (info->icount.parity)
1348 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1349 if (info->icount.brk)
1350 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1351 if (info->icount.overrun)
1352 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1353 }
1354
1355 /* Append serial signal status to end */
1356 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1357
1358 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1359 info->tx_active,info->bh_requested,info->bh_running,
1360 info->pending_bh);
1361
1362 return ret;
1363 }
1364
1365 /* Called to print information about devices
1366 */
1367 static int read_proc(char *page, char **start, off_t off, int count,
1368 int *eof, void *data)
1369 {
1370 int len = 0, l;
1371 off_t begin = 0;
1372 struct slgt_info *info;
1373
1374 len += sprintf(page, "synclink_gt driver:%s\n", driver_version);
1375
1376 info = slgt_device_list;
1377 while( info ) {
1378 l = line_info(page + len, info);
1379 len += l;
1380 if (len+begin > off+count)
1381 goto done;
1382 if (len+begin < off) {
1383 begin += len;
1384 len = 0;
1385 }
1386 info = info->next_device;
1387 }
1388
1389 *eof = 1;
1390 done:
1391 if (off >= len+begin)
1392 return 0;
1393 *start = page + (off-begin);
1394 return ((count < begin+len-off) ? count : begin+len-off);
1395 }
1396
1397 /*
1398 * return count of bytes in transmit buffer
1399 */
1400 static int chars_in_buffer(struct tty_struct *tty)
1401 {
1402 struct slgt_info *info = tty->driver_data;
1403 if (sanity_check(info, tty->name, "chars_in_buffer"))
1404 return 0;
1405 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, info->tx_count));
1406 return info->tx_count;
1407 }
1408
1409 /*
1410 * signal remote device to throttle send data (our receive data)
1411 */
1412 static void throttle(struct tty_struct * tty)
1413 {
1414 struct slgt_info *info = tty->driver_data;
1415 unsigned long flags;
1416
1417 if (sanity_check(info, tty->name, "throttle"))
1418 return;
1419 DBGINFO(("%s throttle\n", info->device_name));
1420 if (I_IXOFF(tty))
1421 send_xchar(tty, STOP_CHAR(tty));
1422 if (tty->termios->c_cflag & CRTSCTS) {
1423 spin_lock_irqsave(&info->lock,flags);
1424 info->signals &= ~SerialSignal_RTS;
1425 set_signals(info);
1426 spin_unlock_irqrestore(&info->lock,flags);
1427 }
1428 }
1429
1430 /*
1431 * signal remote device to stop throttling send data (our receive data)
1432 */
1433 static void unthrottle(struct tty_struct * tty)
1434 {
1435 struct slgt_info *info = tty->driver_data;
1436 unsigned long flags;
1437
1438 if (sanity_check(info, tty->name, "unthrottle"))
1439 return;
1440 DBGINFO(("%s unthrottle\n", info->device_name));
1441 if (I_IXOFF(tty)) {
1442 if (info->x_char)
1443 info->x_char = 0;
1444 else
1445 send_xchar(tty, START_CHAR(tty));
1446 }
1447 if (tty->termios->c_cflag & CRTSCTS) {
1448 spin_lock_irqsave(&info->lock,flags);
1449 info->signals |= SerialSignal_RTS;
1450 set_signals(info);
1451 spin_unlock_irqrestore(&info->lock,flags);
1452 }
1453 }
1454
1455 /*
1456 * set or clear transmit break condition
1457 * break_state -1=set break condition, 0=clear
1458 */
1459 static void set_break(struct tty_struct *tty, int break_state)
1460 {
1461 struct slgt_info *info = tty->driver_data;
1462 unsigned short value;
1463 unsigned long flags;
1464
1465 if (sanity_check(info, tty->name, "set_break"))
1466 return;
1467 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1468
1469 spin_lock_irqsave(&info->lock,flags);
1470 value = rd_reg16(info, TCR);
1471 if (break_state == -1)
1472 value |= BIT6;
1473 else
1474 value &= ~BIT6;
1475 wr_reg16(info, TCR, value);
1476 spin_unlock_irqrestore(&info->lock,flags);
1477 }
1478
1479 #if SYNCLINK_GENERIC_HDLC
1480
1481 /**
1482 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1483 * set encoding and frame check sequence (FCS) options
1484 *
1485 * dev pointer to network device structure
1486 * encoding serial encoding setting
1487 * parity FCS setting
1488 *
1489 * returns 0 if success, otherwise error code
1490 */
1491 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1492 unsigned short parity)
1493 {
1494 struct slgt_info *info = dev_to_port(dev);
1495 unsigned char new_encoding;
1496 unsigned short new_crctype;
1497
1498 /* return error if TTY interface open */
1499 if (info->count)
1500 return -EBUSY;
1501
1502 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1503
1504 switch (encoding)
1505 {
1506 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1507 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1508 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1509 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1510 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1511 default: return -EINVAL;
1512 }
1513
1514 switch (parity)
1515 {
1516 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1517 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1518 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1519 default: return -EINVAL;
1520 }
1521
1522 info->params.encoding = new_encoding;
1523 info->params.crc_type = new_crctype;
1524
1525 /* if network interface up, reprogram hardware */
1526 if (info->netcount)
1527 program_hw(info);
1528
1529 return 0;
1530 }
1531
1532 /**
1533 * called by generic HDLC layer to send frame
1534 *
1535 * skb socket buffer containing HDLC frame
1536 * dev pointer to network device structure
1537 *
1538 * returns 0 if success, otherwise error code
1539 */
1540 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1541 {
1542 struct slgt_info *info = dev_to_port(dev);
1543 struct net_device_stats *stats = hdlc_stats(dev);
1544 unsigned long flags;
1545
1546 DBGINFO(("%s hdlc_xmit\n", dev->name));
1547
1548 /* stop sending until this frame completes */
1549 netif_stop_queue(dev);
1550
1551 /* copy data to device buffers */
1552 info->tx_count = skb->len;
1553 tx_load(info, skb->data, skb->len);
1554
1555 /* update network statistics */
1556 stats->tx_packets++;
1557 stats->tx_bytes += skb->len;
1558
1559 /* done with socket buffer, so free it */
1560 dev_kfree_skb(skb);
1561
1562 /* save start time for transmit timeout detection */
1563 dev->trans_start = jiffies;
1564
1565 /* start hardware transmitter if necessary */
1566 spin_lock_irqsave(&info->lock,flags);
1567 if (!info->tx_active)
1568 tx_start(info);
1569 spin_unlock_irqrestore(&info->lock,flags);
1570
1571 return 0;
1572 }
1573
1574 /**
1575 * called by network layer when interface enabled
1576 * claim resources and initialize hardware
1577 *
1578 * dev pointer to network device structure
1579 *
1580 * returns 0 if success, otherwise error code
1581 */
1582 static int hdlcdev_open(struct net_device *dev)
1583 {
1584 struct slgt_info *info = dev_to_port(dev);
1585 int rc;
1586 unsigned long flags;
1587
1588 if (!try_module_get(THIS_MODULE))
1589 return -EBUSY;
1590
1591 DBGINFO(("%s hdlcdev_open\n", dev->name));
1592
1593 /* generic HDLC layer open processing */
1594 if ((rc = hdlc_open(dev)))
1595 return rc;
1596
1597 /* arbitrate between network and tty opens */
1598 spin_lock_irqsave(&info->netlock, flags);
1599 if (info->count != 0 || info->netcount != 0) {
1600 DBGINFO(("%s hdlc_open busy\n", dev->name));
1601 spin_unlock_irqrestore(&info->netlock, flags);
1602 return -EBUSY;
1603 }
1604 info->netcount=1;
1605 spin_unlock_irqrestore(&info->netlock, flags);
1606
1607 /* claim resources and init adapter */
1608 if ((rc = startup(info)) != 0) {
1609 spin_lock_irqsave(&info->netlock, flags);
1610 info->netcount=0;
1611 spin_unlock_irqrestore(&info->netlock, flags);
1612 return rc;
1613 }
1614
1615 /* assert DTR and RTS, apply hardware settings */
1616 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1617 program_hw(info);
1618
1619 /* enable network layer transmit */
1620 dev->trans_start = jiffies;
1621 netif_start_queue(dev);
1622
1623 /* inform generic HDLC layer of current DCD status */
1624 spin_lock_irqsave(&info->lock, flags);
1625 get_signals(info);
1626 spin_unlock_irqrestore(&info->lock, flags);
1627 if (info->signals & SerialSignal_DCD)
1628 netif_carrier_on(dev);
1629 else
1630 netif_carrier_off(dev);
1631 return 0;
1632 }
1633
1634 /**
1635 * called by network layer when interface is disabled
1636 * shutdown hardware and release resources
1637 *
1638 * dev pointer to network device structure
1639 *
1640 * returns 0 if success, otherwise error code
1641 */
1642 static int hdlcdev_close(struct net_device *dev)
1643 {
1644 struct slgt_info *info = dev_to_port(dev);
1645 unsigned long flags;
1646
1647 DBGINFO(("%s hdlcdev_close\n", dev->name));
1648
1649 netif_stop_queue(dev);
1650
1651 /* shutdown adapter and release resources */
1652 shutdown(info);
1653
1654 hdlc_close(dev);
1655
1656 spin_lock_irqsave(&info->netlock, flags);
1657 info->netcount=0;
1658 spin_unlock_irqrestore(&info->netlock, flags);
1659
1660 module_put(THIS_MODULE);
1661 return 0;
1662 }
1663
1664 /**
1665 * called by network layer to process IOCTL call to network device
1666 *
1667 * dev pointer to network device structure
1668 * ifr pointer to network interface request structure
1669 * cmd IOCTL command code
1670 *
1671 * returns 0 if success, otherwise error code
1672 */
1673 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1674 {
1675 const size_t size = sizeof(sync_serial_settings);
1676 sync_serial_settings new_line;
1677 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1678 struct slgt_info *info = dev_to_port(dev);
1679 unsigned int flags;
1680
1681 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1682
1683 /* return error if TTY interface open */
1684 if (info->count)
1685 return -EBUSY;
1686
1687 if (cmd != SIOCWANDEV)
1688 return hdlc_ioctl(dev, ifr, cmd);
1689
1690 switch(ifr->ifr_settings.type) {
1691 case IF_GET_IFACE: /* return current sync_serial_settings */
1692
1693 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1694 if (ifr->ifr_settings.size < size) {
1695 ifr->ifr_settings.size = size; /* data size wanted */
1696 return -ENOBUFS;
1697 }
1698
1699 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1700 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1701 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1702 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1703
1704 switch (flags){
1705 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1706 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1707 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1708 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1709 default: new_line.clock_type = CLOCK_DEFAULT;
1710 }
1711
1712 new_line.clock_rate = info->params.clock_speed;
1713 new_line.loopback = info->params.loopback ? 1:0;
1714
1715 if (copy_to_user(line, &new_line, size))
1716 return -EFAULT;
1717 return 0;
1718
1719 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1720
1721 if(!capable(CAP_NET_ADMIN))
1722 return -EPERM;
1723 if (copy_from_user(&new_line, line, size))
1724 return -EFAULT;
1725
1726 switch (new_line.clock_type)
1727 {
1728 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1729 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1730 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1731 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1732 case CLOCK_DEFAULT: flags = info->params.flags &
1733 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1734 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1735 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1736 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1737 default: return -EINVAL;
1738 }
1739
1740 if (new_line.loopback != 0 && new_line.loopback != 1)
1741 return -EINVAL;
1742
1743 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1744 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1745 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1746 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1747 info->params.flags |= flags;
1748
1749 info->params.loopback = new_line.loopback;
1750
1751 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1752 info->params.clock_speed = new_line.clock_rate;
1753 else
1754 info->params.clock_speed = 0;
1755
1756 /* if network interface up, reprogram hardware */
1757 if (info->netcount)
1758 program_hw(info);
1759 return 0;
1760
1761 default:
1762 return hdlc_ioctl(dev, ifr, cmd);
1763 }
1764 }
1765
1766 /**
1767 * called by network layer when transmit timeout is detected
1768 *
1769 * dev pointer to network device structure
1770 */
1771 static void hdlcdev_tx_timeout(struct net_device *dev)
1772 {
1773 struct slgt_info *info = dev_to_port(dev);
1774 struct net_device_stats *stats = hdlc_stats(dev);
1775 unsigned long flags;
1776
1777 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1778
1779 stats->tx_errors++;
1780 stats->tx_aborted_errors++;
1781
1782 spin_lock_irqsave(&info->lock,flags);
1783 tx_stop(info);
1784 spin_unlock_irqrestore(&info->lock,flags);
1785
1786 netif_wake_queue(dev);
1787 }
1788
1789 /**
1790 * called by device driver when transmit completes
1791 * reenable network layer transmit if stopped
1792 *
1793 * info pointer to device instance information
1794 */
1795 static void hdlcdev_tx_done(struct slgt_info *info)
1796 {
1797 if (netif_queue_stopped(info->netdev))
1798 netif_wake_queue(info->netdev);
1799 }
1800
1801 /**
1802 * called by device driver when frame received
1803 * pass frame to network layer
1804 *
1805 * info pointer to device instance information
1806 * buf pointer to buffer contianing frame data
1807 * size count of data bytes in buf
1808 */
1809 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1810 {
1811 struct sk_buff *skb = dev_alloc_skb(size);
1812 struct net_device *dev = info->netdev;
1813 struct net_device_stats *stats = hdlc_stats(dev);
1814
1815 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1816
1817 if (skb == NULL) {
1818 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1819 stats->rx_dropped++;
1820 return;
1821 }
1822
1823 memcpy(skb_put(skb, size),buf,size);
1824
1825 skb->protocol = hdlc_type_trans(skb, info->netdev);
1826
1827 stats->rx_packets++;
1828 stats->rx_bytes += size;
1829
1830 netif_rx(skb);
1831
1832 info->netdev->last_rx = jiffies;
1833 }
1834
1835 /**
1836 * called by device driver when adding device instance
1837 * do generic HDLC initialization
1838 *
1839 * info pointer to device instance information
1840 *
1841 * returns 0 if success, otherwise error code
1842 */
1843 static int hdlcdev_init(struct slgt_info *info)
1844 {
1845 int rc;
1846 struct net_device *dev;
1847 hdlc_device *hdlc;
1848
1849 /* allocate and initialize network and HDLC layer objects */
1850
1851 if (!(dev = alloc_hdlcdev(info))) {
1852 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1853 return -ENOMEM;
1854 }
1855
1856 /* for network layer reporting purposes only */
1857 dev->mem_start = info->phys_reg_addr;
1858 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1859 dev->irq = info->irq_level;
1860
1861 /* network layer callbacks and settings */
1862 dev->do_ioctl = hdlcdev_ioctl;
1863 dev->open = hdlcdev_open;
1864 dev->stop = hdlcdev_close;
1865 dev->tx_timeout = hdlcdev_tx_timeout;
1866 dev->watchdog_timeo = 10*HZ;
1867 dev->tx_queue_len = 50;
1868
1869 /* generic HDLC layer callbacks and settings */
1870 hdlc = dev_to_hdlc(dev);
1871 hdlc->attach = hdlcdev_attach;
1872 hdlc->xmit = hdlcdev_xmit;
1873
1874 /* register objects with HDLC layer */
1875 if ((rc = register_hdlc_device(dev))) {
1876 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1877 free_netdev(dev);
1878 return rc;
1879 }
1880
1881 info->netdev = dev;
1882 return 0;
1883 }
1884
1885 /**
1886 * called by device driver when removing device instance
1887 * do generic HDLC cleanup
1888 *
1889 * info pointer to device instance information
1890 */
1891 static void hdlcdev_exit(struct slgt_info *info)
1892 {
1893 unregister_hdlc_device(info->netdev);
1894 free_netdev(info->netdev);
1895 info->netdev = NULL;
1896 }
1897
1898 #endif /* ifdef CONFIG_HDLC */
1899
1900 /*
1901 * get async data from rx DMA buffers
1902 */
1903 static void rx_async(struct slgt_info *info)
1904 {
1905 struct tty_struct *tty = info->tty;
1906 struct mgsl_icount *icount = &info->icount;
1907 unsigned int start, end;
1908 unsigned char *p;
1909 unsigned char status;
1910 struct slgt_desc *bufs = info->rbufs;
1911 int i, count;
1912 int chars = 0;
1913 int stat;
1914 unsigned char ch;
1915
1916 start = end = info->rbuf_current;
1917
1918 while(desc_complete(bufs[end])) {
1919 count = desc_count(bufs[end]) - info->rbuf_index;
1920 p = bufs[end].buf + info->rbuf_index;
1921
1922 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1923 DBGDATA(info, p, count, "rx");
1924
1925 for(i=0 ; i < count; i+=2, p+=2) {
1926 ch = *p;
1927 icount->rx++;
1928
1929 stat = 0;
1930
1931 if ((status = *(p+1) & (BIT1 + BIT0))) {
1932 if (status & BIT1)
1933 icount->parity++;
1934 else if (status & BIT0)
1935 icount->frame++;
1936 /* discard char if tty control flags say so */
1937 if (status & info->ignore_status_mask)
1938 continue;
1939 if (status & BIT1)
1940 stat = TTY_PARITY;
1941 else if (status & BIT0)
1942 stat = TTY_FRAME;
1943 }
1944 if (tty) {
1945 tty_insert_flip_char(tty, ch, stat);
1946 chars++;
1947 }
1948 }
1949
1950 if (i < count) {
1951 /* receive buffer not completed */
1952 info->rbuf_index += i;
1953 mod_timer(&info->rx_timer, jiffies + 1);
1954 break;
1955 }
1956
1957 info->rbuf_index = 0;
1958 free_rbufs(info, end, end);
1959
1960 if (++end == info->rbuf_count)
1961 end = 0;
1962
1963 /* if entire list searched then no frame available */
1964 if (end == start)
1965 break;
1966 }
1967
1968 if (tty && chars)
1969 tty_flip_buffer_push(tty);
1970 }
1971
1972 /*
1973 * return next bottom half action to perform
1974 */
1975 static int bh_action(struct slgt_info *info)
1976 {
1977 unsigned long flags;
1978 int rc;
1979
1980 spin_lock_irqsave(&info->lock,flags);
1981
1982 if (info->pending_bh & BH_RECEIVE) {
1983 info->pending_bh &= ~BH_RECEIVE;
1984 rc = BH_RECEIVE;
1985 } else if (info->pending_bh & BH_TRANSMIT) {
1986 info->pending_bh &= ~BH_TRANSMIT;
1987 rc = BH_TRANSMIT;
1988 } else if (info->pending_bh & BH_STATUS) {
1989 info->pending_bh &= ~BH_STATUS;
1990 rc = BH_STATUS;
1991 } else {
1992 /* Mark BH routine as complete */
1993 info->bh_running = false;
1994 info->bh_requested = false;
1995 rc = 0;
1996 }
1997
1998 spin_unlock_irqrestore(&info->lock,flags);
1999
2000 return rc;
2001 }
2002
2003 /*
2004 * perform bottom half processing
2005 */
2006 static void bh_handler(struct work_struct *work)
2007 {
2008 struct slgt_info *info = container_of(work, struct slgt_info, task);
2009 int action;
2010
2011 if (!info)
2012 return;
2013 info->bh_running = true;
2014
2015 while((action = bh_action(info))) {
2016 switch (action) {
2017 case BH_RECEIVE:
2018 DBGBH(("%s bh receive\n", info->device_name));
2019 switch(info->params.mode) {
2020 case MGSL_MODE_ASYNC:
2021 rx_async(info);
2022 break;
2023 case MGSL_MODE_HDLC:
2024 while(rx_get_frame(info));
2025 break;
2026 case MGSL_MODE_RAW:
2027 case MGSL_MODE_MONOSYNC:
2028 case MGSL_MODE_BISYNC:
2029 while(rx_get_buf(info));
2030 break;
2031 }
2032 /* restart receiver if rx DMA buffers exhausted */
2033 if (info->rx_restart)
2034 rx_start(info);
2035 break;
2036 case BH_TRANSMIT:
2037 bh_transmit(info);
2038 break;
2039 case BH_STATUS:
2040 DBGBH(("%s bh status\n", info->device_name));
2041 info->ri_chkcount = 0;
2042 info->dsr_chkcount = 0;
2043 info->dcd_chkcount = 0;
2044 info->cts_chkcount = 0;
2045 break;
2046 default:
2047 DBGBH(("%s unknown action\n", info->device_name));
2048 break;
2049 }
2050 }
2051 DBGBH(("%s bh_handler exit\n", info->device_name));
2052 }
2053
2054 static void bh_transmit(struct slgt_info *info)
2055 {
2056 struct tty_struct *tty = info->tty;
2057
2058 DBGBH(("%s bh_transmit\n", info->device_name));
2059 if (tty)
2060 tty_wakeup(tty);
2061 }
2062
2063 static void dsr_change(struct slgt_info *info, unsigned short status)
2064 {
2065 if (status & BIT3) {
2066 info->signals |= SerialSignal_DSR;
2067 info->input_signal_events.dsr_up++;
2068 } else {
2069 info->signals &= ~SerialSignal_DSR;
2070 info->input_signal_events.dsr_down++;
2071 }
2072 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2073 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2074 slgt_irq_off(info, IRQ_DSR);
2075 return;
2076 }
2077 info->icount.dsr++;
2078 wake_up_interruptible(&info->status_event_wait_q);
2079 wake_up_interruptible(&info->event_wait_q);
2080 info->pending_bh |= BH_STATUS;
2081 }
2082
2083 static void cts_change(struct slgt_info *info, unsigned short status)
2084 {
2085 if (status & BIT2) {
2086 info->signals |= SerialSignal_CTS;
2087 info->input_signal_events.cts_up++;
2088 } else {
2089 info->signals &= ~SerialSignal_CTS;
2090 info->input_signal_events.cts_down++;
2091 }
2092 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2093 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2094 slgt_irq_off(info, IRQ_CTS);
2095 return;
2096 }
2097 info->icount.cts++;
2098 wake_up_interruptible(&info->status_event_wait_q);
2099 wake_up_interruptible(&info->event_wait_q);
2100 info->pending_bh |= BH_STATUS;
2101
2102 if (info->flags & ASYNC_CTS_FLOW) {
2103 if (info->tty) {
2104 if (info->tty->hw_stopped) {
2105 if (info->signals & SerialSignal_CTS) {
2106 info->tty->hw_stopped = 0;
2107 info->pending_bh |= BH_TRANSMIT;
2108 return;
2109 }
2110 } else {
2111 if (!(info->signals & SerialSignal_CTS))
2112 info->tty->hw_stopped = 1;
2113 }
2114 }
2115 }
2116 }
2117
2118 static void dcd_change(struct slgt_info *info, unsigned short status)
2119 {
2120 if (status & BIT1) {
2121 info->signals |= SerialSignal_DCD;
2122 info->input_signal_events.dcd_up++;
2123 } else {
2124 info->signals &= ~SerialSignal_DCD;
2125 info->input_signal_events.dcd_down++;
2126 }
2127 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2128 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2129 slgt_irq_off(info, IRQ_DCD);
2130 return;
2131 }
2132 info->icount.dcd++;
2133 #if SYNCLINK_GENERIC_HDLC
2134 if (info->netcount) {
2135 if (info->signals & SerialSignal_DCD)
2136 netif_carrier_on(info->netdev);
2137 else
2138 netif_carrier_off(info->netdev);
2139 }
2140 #endif
2141 wake_up_interruptible(&info->status_event_wait_q);
2142 wake_up_interruptible(&info->event_wait_q);
2143 info->pending_bh |= BH_STATUS;
2144
2145 if (info->flags & ASYNC_CHECK_CD) {
2146 if (info->signals & SerialSignal_DCD)
2147 wake_up_interruptible(&info->open_wait);
2148 else {
2149 if (info->tty)
2150 tty_hangup(info->tty);
2151 }
2152 }
2153 }
2154
2155 static void ri_change(struct slgt_info *info, unsigned short status)
2156 {
2157 if (status & BIT0) {
2158 info->signals |= SerialSignal_RI;
2159 info->input_signal_events.ri_up++;
2160 } else {
2161 info->signals &= ~SerialSignal_RI;
2162 info->input_signal_events.ri_down++;
2163 }
2164 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2165 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2166 slgt_irq_off(info, IRQ_RI);
2167 return;
2168 }
2169 info->icount.rng++;
2170 wake_up_interruptible(&info->status_event_wait_q);
2171 wake_up_interruptible(&info->event_wait_q);
2172 info->pending_bh |= BH_STATUS;
2173 }
2174
2175 static void isr_serial(struct slgt_info *info)
2176 {
2177 unsigned short status = rd_reg16(info, SSR);
2178
2179 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2180
2181 wr_reg16(info, SSR, status); /* clear pending */
2182
2183 info->irq_occurred = true;
2184
2185 if (info->params.mode == MGSL_MODE_ASYNC) {
2186 if (status & IRQ_TXIDLE) {
2187 if (info->tx_count)
2188 isr_txeom(info, status);
2189 }
2190 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2191 info->icount.brk++;
2192 /* process break detection if tty control allows */
2193 if (info->tty) {
2194 if (!(status & info->ignore_status_mask)) {
2195 if (info->read_status_mask & MASK_BREAK) {
2196 tty_insert_flip_char(info->tty, 0, TTY_BREAK);
2197 if (info->flags & ASYNC_SAK)
2198 do_SAK(info->tty);
2199 }
2200 }
2201 }
2202 }
2203 } else {
2204 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2205 isr_txeom(info, status);
2206
2207 if (status & IRQ_RXIDLE) {
2208 if (status & RXIDLE)
2209 info->icount.rxidle++;
2210 else
2211 info->icount.exithunt++;
2212 wake_up_interruptible(&info->event_wait_q);
2213 }
2214
2215 if (status & IRQ_RXOVER)
2216 rx_start(info);
2217 }
2218
2219 if (status & IRQ_DSR)
2220 dsr_change(info, status);
2221 if (status & IRQ_CTS)
2222 cts_change(info, status);
2223 if (status & IRQ_DCD)
2224 dcd_change(info, status);
2225 if (status & IRQ_RI)
2226 ri_change(info, status);
2227 }
2228
2229 static void isr_rdma(struct slgt_info *info)
2230 {
2231 unsigned int status = rd_reg32(info, RDCSR);
2232
2233 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2234
2235 /* RDCSR (rx DMA control/status)
2236 *
2237 * 31..07 reserved
2238 * 06 save status byte to DMA buffer
2239 * 05 error
2240 * 04 eol (end of list)
2241 * 03 eob (end of buffer)
2242 * 02 IRQ enable
2243 * 01 reset
2244 * 00 enable
2245 */
2246 wr_reg32(info, RDCSR, status); /* clear pending */
2247
2248 if (status & (BIT5 + BIT4)) {
2249 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2250 info->rx_restart = true;
2251 }
2252 info->pending_bh |= BH_RECEIVE;
2253 }
2254
2255 static void isr_tdma(struct slgt_info *info)
2256 {
2257 unsigned int status = rd_reg32(info, TDCSR);
2258
2259 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2260
2261 /* TDCSR (tx DMA control/status)
2262 *
2263 * 31..06 reserved
2264 * 05 error
2265 * 04 eol (end of list)
2266 * 03 eob (end of buffer)
2267 * 02 IRQ enable
2268 * 01 reset
2269 * 00 enable
2270 */
2271 wr_reg32(info, TDCSR, status); /* clear pending */
2272
2273 if (status & (BIT5 + BIT4 + BIT3)) {
2274 // another transmit buffer has completed
2275 // run bottom half to get more send data from user
2276 info->pending_bh |= BH_TRANSMIT;
2277 }
2278 }
2279
2280 static void isr_txeom(struct slgt_info *info, unsigned short status)
2281 {
2282 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2283
2284 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2285 tdma_reset(info);
2286 reset_tbufs(info);
2287 if (status & IRQ_TXUNDER) {
2288 unsigned short val = rd_reg16(info, TCR);
2289 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2290 wr_reg16(info, TCR, val); /* clear reset bit */
2291 }
2292
2293 if (info->tx_active) {
2294 if (info->params.mode != MGSL_MODE_ASYNC) {
2295 if (status & IRQ_TXUNDER)
2296 info->icount.txunder++;
2297 else if (status & IRQ_TXIDLE)
2298 info->icount.txok++;
2299 }
2300
2301 info->tx_active = false;
2302 info->tx_count = 0;
2303
2304 del_timer(&info->tx_timer);
2305
2306 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2307 info->signals &= ~SerialSignal_RTS;
2308 info->drop_rts_on_tx_done = false;
2309 set_signals(info);
2310 }
2311
2312 #if SYNCLINK_GENERIC_HDLC
2313 if (info->netcount)
2314 hdlcdev_tx_done(info);
2315 else
2316 #endif
2317 {
2318 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2319 tx_stop(info);
2320 return;
2321 }
2322 info->pending_bh |= BH_TRANSMIT;
2323 }
2324 }
2325 }
2326
2327 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2328 {
2329 struct cond_wait *w, *prev;
2330
2331 /* wake processes waiting for specific transitions */
2332 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2333 if (w->data & changed) {
2334 w->data = state;
2335 wake_up_interruptible(&w->q);
2336 if (prev != NULL)
2337 prev->next = w->next;
2338 else
2339 info->gpio_wait_q = w->next;
2340 } else
2341 prev = w;
2342 }
2343 }
2344
2345 /* interrupt service routine
2346 *
2347 * irq interrupt number
2348 * dev_id device ID supplied during interrupt registration
2349 */
2350 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2351 {
2352 struct slgt_info *info = dev_id;
2353 unsigned int gsr;
2354 unsigned int i;
2355
2356 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2357
2358 spin_lock(&info->lock);
2359
2360 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2361 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2362 info->irq_occurred = true;
2363 for(i=0; i < info->port_count ; i++) {
2364 if (info->port_array[i] == NULL)
2365 continue;
2366 if (gsr & (BIT8 << i))
2367 isr_serial(info->port_array[i]);
2368 if (gsr & (BIT16 << (i*2)))
2369 isr_rdma(info->port_array[i]);
2370 if (gsr & (BIT17 << (i*2)))
2371 isr_tdma(info->port_array[i]);
2372 }
2373 }
2374
2375 if (info->gpio_present) {
2376 unsigned int state;
2377 unsigned int changed;
2378 while ((changed = rd_reg32(info, IOSR)) != 0) {
2379 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2380 /* read latched state of GPIO signals */
2381 state = rd_reg32(info, IOVR);
2382 /* clear pending GPIO interrupt bits */
2383 wr_reg32(info, IOSR, changed);
2384 for (i=0 ; i < info->port_count ; i++) {
2385 if (info->port_array[i] != NULL)
2386 isr_gpio(info->port_array[i], changed, state);
2387 }
2388 }
2389 }
2390
2391 for(i=0; i < info->port_count ; i++) {
2392 struct slgt_info *port = info->port_array[i];
2393
2394 if (port && (port->count || port->netcount) &&
2395 port->pending_bh && !port->bh_running &&
2396 !port->bh_requested) {
2397 DBGISR(("%s bh queued\n", port->device_name));
2398 schedule_work(&port->task);
2399 port->bh_requested = true;
2400 }
2401 }
2402
2403 spin_unlock(&info->lock);
2404
2405 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2406 return IRQ_HANDLED;
2407 }
2408
2409 static int startup(struct slgt_info *info)
2410 {
2411 DBGINFO(("%s startup\n", info->device_name));
2412
2413 if (info->flags & ASYNC_INITIALIZED)
2414 return 0;
2415
2416 if (!info->tx_buf) {
2417 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2418 if (!info->tx_buf) {
2419 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2420 return -ENOMEM;
2421 }
2422 }
2423
2424 info->pending_bh = 0;
2425
2426 memset(&info->icount, 0, sizeof(info->icount));
2427
2428 /* program hardware for current parameters */
2429 change_params(info);
2430
2431 if (info->tty)
2432 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2433
2434 info->flags |= ASYNC_INITIALIZED;
2435
2436 return 0;
2437 }
2438
2439 /*
2440 * called by close() and hangup() to shutdown hardware
2441 */
2442 static void shutdown(struct slgt_info *info)
2443 {
2444 unsigned long flags;
2445
2446 if (!(info->flags & ASYNC_INITIALIZED))
2447 return;
2448
2449 DBGINFO(("%s shutdown\n", info->device_name));
2450
2451 /* clear status wait queue because status changes */
2452 /* can't happen after shutting down the hardware */
2453 wake_up_interruptible(&info->status_event_wait_q);
2454 wake_up_interruptible(&info->event_wait_q);
2455
2456 del_timer_sync(&info->tx_timer);
2457 del_timer_sync(&info->rx_timer);
2458
2459 kfree(info->tx_buf);
2460 info->tx_buf = NULL;
2461
2462 spin_lock_irqsave(&info->lock,flags);
2463
2464 tx_stop(info);
2465 rx_stop(info);
2466
2467 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2468
2469 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2470 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2471 set_signals(info);
2472 }
2473
2474 flush_cond_wait(&info->gpio_wait_q);
2475
2476 spin_unlock_irqrestore(&info->lock,flags);
2477
2478 if (info->tty)
2479 set_bit(TTY_IO_ERROR, &info->tty->flags);
2480
2481 info->flags &= ~ASYNC_INITIALIZED;
2482 }
2483
2484 static void program_hw(struct slgt_info *info)
2485 {
2486 unsigned long flags;
2487
2488 spin_lock_irqsave(&info->lock,flags);
2489
2490 rx_stop(info);
2491 tx_stop(info);
2492
2493 if (info->params.mode != MGSL_MODE_ASYNC ||
2494 info->netcount)
2495 sync_mode(info);
2496 else
2497 async_mode(info);
2498
2499 set_signals(info);
2500
2501 info->dcd_chkcount = 0;
2502 info->cts_chkcount = 0;
2503 info->ri_chkcount = 0;
2504 info->dsr_chkcount = 0;
2505
2506 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR);
2507 get_signals(info);
2508
2509 if (info->netcount ||
2510 (info->tty && info->tty->termios->c_cflag & CREAD))
2511 rx_start(info);
2512
2513 spin_unlock_irqrestore(&info->lock,flags);
2514 }
2515
2516 /*
2517 * reconfigure adapter based on new parameters
2518 */
2519 static void change_params(struct slgt_info *info)
2520 {
2521 unsigned cflag;
2522 int bits_per_char;
2523
2524 if (!info->tty || !info->tty->termios)
2525 return;
2526 DBGINFO(("%s change_params\n", info->device_name));
2527
2528 cflag = info->tty->termios->c_cflag;
2529
2530 /* if B0 rate (hangup) specified then negate DTR and RTS */
2531 /* otherwise assert DTR and RTS */
2532 if (cflag & CBAUD)
2533 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2534 else
2535 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2536
2537 /* byte size and parity */
2538
2539 switch (cflag & CSIZE) {
2540 case CS5: info->params.data_bits = 5; break;
2541 case CS6: info->params.data_bits = 6; break;
2542 case CS7: info->params.data_bits = 7; break;
2543 case CS8: info->params.data_bits = 8; break;
2544 default: info->params.data_bits = 7; break;
2545 }
2546
2547 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2548
2549 if (cflag & PARENB)
2550 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2551 else
2552 info->params.parity = ASYNC_PARITY_NONE;
2553
2554 /* calculate number of jiffies to transmit a full
2555 * FIFO (32 bytes) at specified data rate
2556 */
2557 bits_per_char = info->params.data_bits +
2558 info->params.stop_bits + 1;
2559
2560 info->params.data_rate = tty_get_baud_rate(info->tty);
2561
2562 if (info->params.data_rate) {
2563 info->timeout = (32*HZ*bits_per_char) /
2564 info->params.data_rate;
2565 }
2566 info->timeout += HZ/50; /* Add .02 seconds of slop */
2567
2568 if (cflag & CRTSCTS)
2569 info->flags |= ASYNC_CTS_FLOW;
2570 else
2571 info->flags &= ~ASYNC_CTS_FLOW;
2572
2573 if (cflag & CLOCAL)
2574 info->flags &= ~ASYNC_CHECK_CD;
2575 else
2576 info->flags |= ASYNC_CHECK_CD;
2577
2578 /* process tty input control flags */
2579
2580 info->read_status_mask = IRQ_RXOVER;
2581 if (I_INPCK(info->tty))
2582 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2583 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2584 info->read_status_mask |= MASK_BREAK;
2585 if (I_IGNPAR(info->tty))
2586 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2587 if (I_IGNBRK(info->tty)) {
2588 info->ignore_status_mask |= MASK_BREAK;
2589 /* If ignoring parity and break indicators, ignore
2590 * overruns too. (For real raw support).
2591 */
2592 if (I_IGNPAR(info->tty))
2593 info->ignore_status_mask |= MASK_OVERRUN;
2594 }
2595
2596 program_hw(info);
2597 }
2598
2599 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2600 {
2601 DBGINFO(("%s get_stats\n", info->device_name));
2602 if (!user_icount) {
2603 memset(&info->icount, 0, sizeof(info->icount));
2604 } else {
2605 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2606 return -EFAULT;
2607 }
2608 return 0;
2609 }
2610
2611 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2612 {
2613 DBGINFO(("%s get_params\n", info->device_name));
2614 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2615 return -EFAULT;
2616 return 0;
2617 }
2618
2619 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2620 {
2621 unsigned long flags;
2622 MGSL_PARAMS tmp_params;
2623
2624 DBGINFO(("%s set_params\n", info->device_name));
2625 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2626 return -EFAULT;
2627
2628 spin_lock_irqsave(&info->lock, flags);
2629 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2630 spin_unlock_irqrestore(&info->lock, flags);
2631
2632 change_params(info);
2633
2634 return 0;
2635 }
2636
2637 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2638 {
2639 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2640 if (put_user(info->idle_mode, idle_mode))
2641 return -EFAULT;
2642 return 0;
2643 }
2644
2645 static int set_txidle(struct slgt_info *info, int idle_mode)
2646 {
2647 unsigned long flags;
2648 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2649 spin_lock_irqsave(&info->lock,flags);
2650 info->idle_mode = idle_mode;
2651 if (info->params.mode != MGSL_MODE_ASYNC)
2652 tx_set_idle(info);
2653 spin_unlock_irqrestore(&info->lock,flags);
2654 return 0;
2655 }
2656
2657 static int tx_enable(struct slgt_info *info, int enable)
2658 {
2659 unsigned long flags;
2660 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2661 spin_lock_irqsave(&info->lock,flags);
2662 if (enable) {
2663 if (!info->tx_enabled)
2664 tx_start(info);
2665 } else {
2666 if (info->tx_enabled)
2667 tx_stop(info);
2668 }
2669 spin_unlock_irqrestore(&info->lock,flags);
2670 return 0;
2671 }
2672
2673 /*
2674 * abort transmit HDLC frame
2675 */
2676 static int tx_abort(struct slgt_info *info)
2677 {
2678 unsigned long flags;
2679 DBGINFO(("%s tx_abort\n", info->device_name));
2680 spin_lock_irqsave(&info->lock,flags);
2681 tdma_reset(info);
2682 spin_unlock_irqrestore(&info->lock,flags);
2683 return 0;
2684 }
2685
2686 static int rx_enable(struct slgt_info *info, int enable)
2687 {
2688 unsigned long flags;
2689 DBGINFO(("%s rx_enable(%d)\n", info->device_name, enable));
2690 spin_lock_irqsave(&info->lock,flags);
2691 if (enable) {
2692 if (!info->rx_enabled)
2693 rx_start(info);
2694 else if (enable == 2) {
2695 /* force hunt mode (write 1 to RCR[3]) */
2696 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2697 }
2698 } else {
2699 if (info->rx_enabled)
2700 rx_stop(info);
2701 }
2702 spin_unlock_irqrestore(&info->lock,flags);
2703 return 0;
2704 }
2705
2706 /*
2707 * wait for specified event to occur
2708 */
2709 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2710 {
2711 unsigned long flags;
2712 int s;
2713 int rc=0;
2714 struct mgsl_icount cprev, cnow;
2715 int events;
2716 int mask;
2717 struct _input_signal_events oldsigs, newsigs;
2718 DECLARE_WAITQUEUE(wait, current);
2719
2720 if (get_user(mask, mask_ptr))
2721 return -EFAULT;
2722
2723 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2724
2725 spin_lock_irqsave(&info->lock,flags);
2726
2727 /* return immediately if state matches requested events */
2728 get_signals(info);
2729 s = info->signals;
2730
2731 events = mask &
2732 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2733 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2734 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2735 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2736 if (events) {
2737 spin_unlock_irqrestore(&info->lock,flags);
2738 goto exit;
2739 }
2740
2741 /* save current irq counts */
2742 cprev = info->icount;
2743 oldsigs = info->input_signal_events;
2744
2745 /* enable hunt and idle irqs if needed */
2746 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2747 unsigned short val = rd_reg16(info, SCR);
2748 if (!(val & IRQ_RXIDLE))
2749 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2750 }
2751
2752 set_current_state(TASK_INTERRUPTIBLE);
2753 add_wait_queue(&info->event_wait_q, &wait);
2754
2755 spin_unlock_irqrestore(&info->lock,flags);
2756
2757 for(;;) {
2758 schedule();
2759 if (signal_pending(current)) {
2760 rc = -ERESTARTSYS;
2761 break;
2762 }
2763
2764 /* get current irq counts */
2765 spin_lock_irqsave(&info->lock,flags);
2766 cnow = info->icount;
2767 newsigs = info->input_signal_events;
2768 set_current_state(TASK_INTERRUPTIBLE);
2769 spin_unlock_irqrestore(&info->lock,flags);
2770
2771 /* if no change, wait aborted for some reason */
2772 if (newsigs.dsr_up == oldsigs.dsr_up &&
2773 newsigs.dsr_down == oldsigs.dsr_down &&
2774 newsigs.dcd_up == oldsigs.dcd_up &&
2775 newsigs.dcd_down == oldsigs.dcd_down &&
2776 newsigs.cts_up == oldsigs.cts_up &&
2777 newsigs.cts_down == oldsigs.cts_down &&
2778 newsigs.ri_up == oldsigs.ri_up &&
2779 newsigs.ri_down == oldsigs.ri_down &&
2780 cnow.exithunt == cprev.exithunt &&
2781 cnow.rxidle == cprev.rxidle) {
2782 rc = -EIO;
2783 break;
2784 }
2785
2786 events = mask &
2787 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2788 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2789 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2790 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2791 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2792 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2793 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2794 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2795 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2796 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2797 if (events)
2798 break;
2799
2800 cprev = cnow;
2801 oldsigs = newsigs;
2802 }
2803
2804 remove_wait_queue(&info->event_wait_q, &wait);
2805 set_current_state(TASK_RUNNING);
2806
2807
2808 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2809 spin_lock_irqsave(&info->lock,flags);
2810 if (!waitqueue_active(&info->event_wait_q)) {
2811 /* disable enable exit hunt mode/idle rcvd IRQs */
2812 wr_reg16(info, SCR,
2813 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2814 }
2815 spin_unlock_irqrestore(&info->lock,flags);
2816 }
2817 exit:
2818 if (rc == 0)
2819 rc = put_user(events, mask_ptr);
2820 return rc;
2821 }
2822
2823 static int get_interface(struct slgt_info *info, int __user *if_mode)
2824 {
2825 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2826 if (put_user(info->if_mode, if_mode))
2827 return -EFAULT;
2828 return 0;
2829 }
2830
2831 static int set_interface(struct slgt_info *info, int if_mode)
2832 {
2833 unsigned long flags;
2834 unsigned short val;
2835
2836 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2837 spin_lock_irqsave(&info->lock,flags);
2838 info->if_mode = if_mode;
2839
2840 msc_set_vcr(info);
2841
2842 /* TCR (tx control) 07 1=RTS driver control */
2843 val = rd_reg16(info, TCR);
2844 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2845 val |= BIT7;
2846 else
2847 val &= ~BIT7;
2848 wr_reg16(info, TCR, val);
2849
2850 spin_unlock_irqrestore(&info->lock,flags);
2851 return 0;
2852 }
2853
2854 /*
2855 * set general purpose IO pin state and direction
2856 *
2857 * user_gpio fields:
2858 * state each bit indicates a pin state
2859 * smask set bit indicates pin state to set
2860 * dir each bit indicates a pin direction (0=input, 1=output)
2861 * dmask set bit indicates pin direction to set
2862 */
2863 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2864 {
2865 unsigned long flags;
2866 struct gpio_desc gpio;
2867 __u32 data;
2868
2869 if (!info->gpio_present)
2870 return -EINVAL;
2871 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2872 return -EFAULT;
2873 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2874 info->device_name, gpio.state, gpio.smask,
2875 gpio.dir, gpio.dmask));
2876
2877 spin_lock_irqsave(&info->lock,flags);
2878 if (gpio.dmask) {
2879 data = rd_reg32(info, IODR);
2880 data |= gpio.dmask & gpio.dir;
2881 data &= ~(gpio.dmask & ~gpio.dir);
2882 wr_reg32(info, IODR, data);
2883 }
2884 if (gpio.smask) {
2885 data = rd_reg32(info, IOVR);
2886 data |= gpio.smask & gpio.state;
2887 data &= ~(gpio.smask & ~gpio.state);
2888 wr_reg32(info, IOVR, data);
2889 }
2890 spin_unlock_irqrestore(&info->lock,flags);
2891
2892 return 0;
2893 }
2894
2895 /*
2896 * get general purpose IO pin state and direction
2897 */
2898 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2899 {
2900 struct gpio_desc gpio;
2901 if (!info->gpio_present)
2902 return -EINVAL;
2903 gpio.state = rd_reg32(info, IOVR);
2904 gpio.smask = 0xffffffff;
2905 gpio.dir = rd_reg32(info, IODR);
2906 gpio.dmask = 0xffffffff;
2907 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2908 return -EFAULT;
2909 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2910 info->device_name, gpio.state, gpio.dir));
2911 return 0;
2912 }
2913
2914 /*
2915 * conditional wait facility
2916 */
2917 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2918 {
2919 init_waitqueue_head(&w->q);
2920 init_waitqueue_entry(&w->wait, current);
2921 w->data = data;
2922 }
2923
2924 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2925 {
2926 set_current_state(TASK_INTERRUPTIBLE);
2927 add_wait_queue(&w->q, &w->wait);
2928 w->next = *head;
2929 *head = w;
2930 }
2931
2932 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2933 {
2934 struct cond_wait *w, *prev;
2935 remove_wait_queue(&cw->q, &cw->wait);
2936 set_current_state(TASK_RUNNING);
2937 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2938 if (w == cw) {
2939 if (prev != NULL)
2940 prev->next = w->next;
2941 else
2942 *head = w->next;
2943 break;
2944 }
2945 }
2946 }
2947
2948 static void flush_cond_wait(struct cond_wait **head)
2949 {
2950 while (*head != NULL) {
2951 wake_up_interruptible(&(*head)->q);
2952 *head = (*head)->next;
2953 }
2954 }
2955
2956 /*
2957 * wait for general purpose I/O pin(s) to enter specified state
2958 *
2959 * user_gpio fields:
2960 * state - bit indicates target pin state
2961 * smask - set bit indicates watched pin
2962 *
2963 * The wait ends when at least one watched pin enters the specified
2964 * state. When 0 (no error) is returned, user_gpio->state is set to the
2965 * state of all GPIO pins when the wait ends.
2966 *
2967 * Note: Each pin may be a dedicated input, dedicated output, or
2968 * configurable input/output. The number and configuration of pins
2969 * varies with the specific adapter model. Only input pins (dedicated
2970 * or configured) can be monitored with this function.
2971 */
2972 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2973 {
2974 unsigned long flags;
2975 int rc = 0;
2976 struct gpio_desc gpio;
2977 struct cond_wait wait;
2978 u32 state;
2979
2980 if (!info->gpio_present)
2981 return -EINVAL;
2982 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2983 return -EFAULT;
2984 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2985 info->device_name, gpio.state, gpio.smask));
2986 /* ignore output pins identified by set IODR bit */
2987 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2988 return -EINVAL;
2989 init_cond_wait(&wait, gpio.smask);
2990
2991 spin_lock_irqsave(&info->lock, flags);
2992 /* enable interrupts for watched pins */
2993 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2994 /* get current pin states */
2995 state = rd_reg32(info, IOVR);
2996
2997 if (gpio.smask & ~(state ^ gpio.state)) {
2998 /* already in target state */
2999 gpio.state = state;
3000 } else {
3001 /* wait for target state */
3002 add_cond_wait(&info->gpio_wait_q, &wait);
3003 spin_unlock_irqrestore(&info->lock, flags);
3004 schedule();
3005 if (signal_pending(current))
3006 rc = -ERESTARTSYS;
3007 else
3008 gpio.state = wait.data;
3009 spin_lock_irqsave(&info->lock, flags);
3010 remove_cond_wait(&info->gpio_wait_q, &wait);
3011 }
3012
3013 /* disable all GPIO interrupts if no waiting processes */
3014 if (info->gpio_wait_q == NULL)
3015 wr_reg32(info, IOER, 0);
3016 spin_unlock_irqrestore(&info->lock,flags);
3017
3018 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3019 rc = -EFAULT;
3020 return rc;
3021 }
3022
3023 static int modem_input_wait(struct slgt_info *info,int arg)
3024 {
3025 unsigned long flags;
3026 int rc;
3027 struct mgsl_icount cprev, cnow;
3028 DECLARE_WAITQUEUE(wait, current);
3029
3030 /* save current irq counts */
3031 spin_lock_irqsave(&info->lock,flags);
3032 cprev = info->icount;
3033 add_wait_queue(&info->status_event_wait_q, &wait);
3034 set_current_state(TASK_INTERRUPTIBLE);
3035 spin_unlock_irqrestore(&info->lock,flags);
3036
3037 for(;;) {
3038 schedule();
3039 if (signal_pending(current)) {
3040 rc = -ERESTARTSYS;
3041 break;
3042 }
3043
3044 /* get new irq counts */
3045 spin_lock_irqsave(&info->lock,flags);
3046 cnow = info->icount;
3047 set_current_state(TASK_INTERRUPTIBLE);
3048 spin_unlock_irqrestore(&info->lock,flags);
3049
3050 /* if no change, wait aborted for some reason */
3051 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3052 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3053 rc = -EIO;
3054 break;
3055 }
3056
3057 /* check for change in caller specified modem input */
3058 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3059 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3060 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3061 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3062 rc = 0;
3063 break;
3064 }
3065
3066 cprev = cnow;
3067 }
3068 remove_wait_queue(&info->status_event_wait_q, &wait);
3069 set_current_state(TASK_RUNNING);
3070 return rc;
3071 }
3072
3073 /*
3074 * return state of serial control and status signals
3075 */
3076 static int tiocmget(struct tty_struct *tty, struct file *file)
3077 {
3078 struct slgt_info *info = tty->driver_data;
3079 unsigned int result;
3080 unsigned long flags;
3081
3082 spin_lock_irqsave(&info->lock,flags);
3083 get_signals(info);
3084 spin_unlock_irqrestore(&info->lock,flags);
3085
3086 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3087 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3088 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3089 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3090 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3091 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3092
3093 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3094 return result;
3095 }
3096
3097 /*
3098 * set modem control signals (DTR/RTS)
3099 *
3100 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3101 * TIOCMSET = set/clear signal values
3102 * value bit mask for command
3103 */
3104 static int tiocmset(struct tty_struct *tty, struct file *file,
3105 unsigned int set, unsigned int clear)
3106 {
3107 struct slgt_info *info = tty->driver_data;
3108 unsigned long flags;
3109
3110 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3111
3112 if (set & TIOCM_RTS)
3113 info->signals |= SerialSignal_RTS;
3114 if (set & TIOCM_DTR)
3115 info->signals |= SerialSignal_DTR;
3116 if (clear & TIOCM_RTS)
3117 info->signals &= ~SerialSignal_RTS;
3118 if (clear & TIOCM_DTR)
3119 info->signals &= ~SerialSignal_DTR;
3120
3121 spin_lock_irqsave(&info->lock,flags);
3122 set_signals(info);
3123 spin_unlock_irqrestore(&info->lock,flags);
3124 return 0;
3125 }
3126
3127 /*
3128 * block current process until the device is ready to open
3129 */
3130 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3131 struct slgt_info *info)
3132 {
3133 DECLARE_WAITQUEUE(wait, current);
3134 int retval;
3135 bool do_clocal = false;
3136 bool extra_count = false;
3137 unsigned long flags;
3138
3139 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3140
3141 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3142 /* nonblock mode is set or port is not enabled */
3143 info->flags |= ASYNC_NORMAL_ACTIVE;
3144 return 0;
3145 }
3146
3147 if (tty->termios->c_cflag & CLOCAL)
3148 do_clocal = true;
3149
3150 /* Wait for carrier detect and the line to become
3151 * free (i.e., not in use by the callout). While we are in
3152 * this loop, info->count is dropped by one, so that
3153 * close() knows when to free things. We restore it upon
3154 * exit, either normal or abnormal.
3155 */
3156
3157 retval = 0;
3158 add_wait_queue(&info->open_wait, &wait);
3159
3160 spin_lock_irqsave(&info->lock, flags);
3161 if (!tty_hung_up_p(filp)) {
3162 extra_count = true;
3163 info->count--;
3164 }
3165 spin_unlock_irqrestore(&info->lock, flags);
3166 info->blocked_open++;
3167
3168 while (1) {
3169 if ((tty->termios->c_cflag & CBAUD)) {
3170 spin_lock_irqsave(&info->lock,flags);
3171 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3172 set_signals(info);
3173 spin_unlock_irqrestore(&info->lock,flags);
3174 }
3175
3176 set_current_state(TASK_INTERRUPTIBLE);
3177
3178 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3179 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3180 -EAGAIN : -ERESTARTSYS;
3181 break;
3182 }
3183
3184 spin_lock_irqsave(&info->lock,flags);
3185 get_signals(info);
3186 spin_unlock_irqrestore(&info->lock,flags);
3187
3188 if (!(info->flags & ASYNC_CLOSING) &&
3189 (do_clocal || (info->signals & SerialSignal_DCD)) ) {
3190 break;
3191 }
3192
3193 if (signal_pending(current)) {
3194 retval = -ERESTARTSYS;
3195 break;
3196 }
3197
3198 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3199 schedule();
3200 }
3201
3202 set_current_state(TASK_RUNNING);
3203 remove_wait_queue(&info->open_wait, &wait);
3204
3205 if (extra_count)
3206 info->count++;
3207 info->blocked_open--;
3208
3209 if (!retval)
3210 info->flags |= ASYNC_NORMAL_ACTIVE;
3211
3212 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3213 return retval;
3214 }
3215
3216 static int alloc_tmp_rbuf(struct slgt_info *info)
3217 {
3218 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3219 if (info->tmp_rbuf == NULL)
3220 return -ENOMEM;
3221 return 0;
3222 }
3223
3224 static void free_tmp_rbuf(struct slgt_info *info)
3225 {
3226 kfree(info->tmp_rbuf);
3227 info->tmp_rbuf = NULL;
3228 }
3229
3230 /*
3231 * allocate DMA descriptor lists.
3232 */
3233 static int alloc_desc(struct slgt_info *info)
3234 {
3235 unsigned int i;
3236 unsigned int pbufs;
3237
3238 /* allocate memory to hold descriptor lists */
3239 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3240 if (info->bufs == NULL)
3241 return -ENOMEM;
3242
3243 memset(info->bufs, 0, DESC_LIST_SIZE);
3244
3245 info->rbufs = (struct slgt_desc*)info->bufs;
3246 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3247
3248 pbufs = (unsigned int)info->bufs_dma_addr;
3249
3250 /*
3251 * Build circular lists of descriptors
3252 */
3253
3254 for (i=0; i < info->rbuf_count; i++) {
3255 /* physical address of this descriptor */
3256 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3257
3258 /* physical address of next descriptor */
3259 if (i == info->rbuf_count - 1)
3260 info->rbufs[i].next = cpu_to_le32(pbufs);
3261 else
3262 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3263 set_desc_count(info->rbufs[i], DMABUFSIZE);
3264 }
3265
3266 for (i=0; i < info->tbuf_count; i++) {
3267 /* physical address of this descriptor */
3268 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3269
3270 /* physical address of next descriptor */
3271 if (i == info->tbuf_count - 1)
3272 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3273 else
3274 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3275 }
3276
3277 return 0;
3278 }
3279
3280 static void free_desc(struct slgt_info *info)
3281 {
3282 if (info->bufs != NULL) {
3283 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3284 info->bufs = NULL;
3285 info->rbufs = NULL;
3286 info->tbufs = NULL;
3287 }
3288 }
3289
3290 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3291 {
3292 int i;
3293 for (i=0; i < count; i++) {
3294 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3295 return -ENOMEM;
3296 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3297 }
3298 return 0;
3299 }
3300
3301 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3302 {
3303 int i;
3304 for (i=0; i < count; i++) {
3305 if (bufs[i].buf == NULL)
3306 continue;
3307 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3308 bufs[i].buf = NULL;
3309 }
3310 }
3311
3312 static int alloc_dma_bufs(struct slgt_info *info)
3313 {
3314 info->rbuf_count = 32;
3315 info->tbuf_count = 32;
3316
3317 if (alloc_desc(info) < 0 ||
3318 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3319 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3320 alloc_tmp_rbuf(info) < 0) {
3321 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3322 return -ENOMEM;
3323 }
3324 reset_rbufs(info);
3325 return 0;
3326 }
3327
3328 static void free_dma_bufs(struct slgt_info *info)
3329 {
3330 if (info->bufs) {
3331 free_bufs(info, info->rbufs, info->rbuf_count);
3332 free_bufs(info, info->tbufs, info->tbuf_count);
3333 free_desc(info);
3334 }
3335 free_tmp_rbuf(info);
3336 }
3337
3338 static int claim_resources(struct slgt_info *info)
3339 {
3340 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3341 DBGERR(("%s reg addr conflict, addr=%08X\n",
3342 info->device_name, info->phys_reg_addr));
3343 info->init_error = DiagStatus_AddressConflict;
3344 goto errout;
3345 }
3346 else
3347 info->reg_addr_requested = true;
3348
3349 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3350 if (!info->reg_addr) {
3351 DBGERR(("%s cant map device registers, addr=%08X\n",
3352 info->device_name, info->phys_reg_addr));
3353 info->init_error = DiagStatus_CantAssignPciResources;
3354 goto errout;
3355 }
3356 return 0;
3357
3358 errout:
3359 release_resources(info);
3360 return -ENODEV;
3361 }
3362
3363 static void release_resources(struct slgt_info *info)
3364 {
3365 if (info->irq_requested) {
3366 free_irq(info->irq_level, info);
3367 info->irq_requested = false;
3368 }
3369
3370 if (info->reg_addr_requested) {
3371 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3372 info->reg_addr_requested = false;
3373 }
3374
3375 if (info->reg_addr) {
3376 iounmap(info->reg_addr);
3377 info->reg_addr = NULL;
3378 }
3379 }
3380
3381 /* Add the specified device instance data structure to the
3382 * global linked list of devices and increment the device count.
3383 */
3384 static void add_device(struct slgt_info *info)
3385 {
3386 char *devstr;
3387
3388 info->next_device = NULL;
3389 info->line = slgt_device_count;
3390 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3391
3392 if (info->line < MAX_DEVICES) {
3393 if (maxframe[info->line])
3394 info->max_frame_size = maxframe[info->line];
3395 info->dosyncppp = dosyncppp[info->line];
3396 }
3397
3398 slgt_device_count++;
3399
3400 if (!slgt_device_list)
3401 slgt_device_list = info;
3402 else {
3403 struct slgt_info *current_dev = slgt_device_list;
3404 while(current_dev->next_device)
3405 current_dev = current_dev->next_device;
3406 current_dev->next_device = info;
3407 }
3408
3409 if (info->max_frame_size < 4096)
3410 info->max_frame_size = 4096;
3411 else if (info->max_frame_size > 65535)
3412 info->max_frame_size = 65535;
3413
3414 switch(info->pdev->device) {
3415 case SYNCLINK_GT_DEVICE_ID:
3416 devstr = "GT";
3417 break;
3418 case SYNCLINK_GT2_DEVICE_ID:
3419 devstr = "GT2";
3420 break;
3421 case SYNCLINK_GT4_DEVICE_ID:
3422 devstr = "GT4";
3423 break;
3424 case SYNCLINK_AC_DEVICE_ID:
3425 devstr = "AC";
3426 info->params.mode = MGSL_MODE_ASYNC;
3427 break;
3428 default:
3429 devstr = "(unknown model)";
3430 }
3431 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3432 devstr, info->device_name, info->phys_reg_addr,
3433 info->irq_level, info->max_frame_size);
3434
3435 #if SYNCLINK_GENERIC_HDLC
3436 hdlcdev_init(info);
3437 #endif
3438 }
3439
3440 /*
3441 * allocate device instance structure, return NULL on failure
3442 */
3443 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3444 {
3445 struct slgt_info *info;
3446
3447 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3448
3449 if (!info) {
3450 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3451 driver_name, adapter_num, port_num));
3452 } else {
3453 info->magic = MGSL_MAGIC;
3454 INIT_WORK(&info->task, bh_handler);
3455 info->max_frame_size = 4096;
3456 info->raw_rx_size = DMABUFSIZE;
3457 info->close_delay = 5*HZ/10;
3458 info->closing_wait = 30*HZ;
3459 init_waitqueue_head(&info->open_wait);
3460 init_waitqueue_head(&info->close_wait);
3461 init_waitqueue_head(&info->status_event_wait_q);
3462 init_waitqueue_head(&info->event_wait_q);
3463 spin_lock_init(&info->netlock);
3464 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3465 info->idle_mode = HDLC_TXIDLE_FLAGS;
3466 info->adapter_num = adapter_num;
3467 info->port_num = port_num;
3468
3469 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3470 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3471
3472 /* Copy configuration info to device instance data */
3473 info->pdev = pdev;
3474 info->irq_level = pdev->irq;
3475 info->phys_reg_addr = pci_resource_start(pdev,0);
3476
3477 info->bus_type = MGSL_BUS_TYPE_PCI;
3478 info->irq_flags = IRQF_SHARED;
3479
3480 info->init_error = -1; /* assume error, set to 0 on successful init */
3481 }
3482
3483 return info;
3484 }
3485
3486 static void device_init(int adapter_num, struct pci_dev *pdev)
3487 {
3488 struct slgt_info *port_array[SLGT_MAX_PORTS];
3489 int i;
3490 int port_count = 1;
3491
3492 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3493 port_count = 2;
3494 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3495 port_count = 4;
3496
3497 /* allocate device instances for all ports */
3498 for (i=0; i < port_count; ++i) {
3499 port_array[i] = alloc_dev(adapter_num, i, pdev);
3500 if (port_array[i] == NULL) {
3501 for (--i; i >= 0; --i)
3502 kfree(port_array[i]);
3503 return;
3504 }
3505 }
3506
3507 /* give copy of port_array to all ports and add to device list */
3508 for (i=0; i < port_count; ++i) {
3509 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3510 add_device(port_array[i]);
3511 port_array[i]->port_count = port_count;
3512 spin_lock_init(&port_array[i]->lock);
3513 }
3514
3515 /* Allocate and claim adapter resources */
3516 if (!claim_resources(port_array[0])) {
3517
3518 alloc_dma_bufs(port_array[0]);
3519
3520 /* copy resource information from first port to others */
3521 for (i = 1; i < port_count; ++i) {
3522 port_array[i]->lock = port_array[0]->lock;
3523 port_array[i]->irq_level = port_array[0]->irq_level;
3524 port_array[i]->reg_addr = port_array[0]->reg_addr;
3525 alloc_dma_bufs(port_array[i]);
3526 }
3527
3528 if (request_irq(port_array[0]->irq_level,
3529 slgt_interrupt,
3530 port_array[0]->irq_flags,
3531 port_array[0]->device_name,
3532 port_array[0]) < 0) {
3533 DBGERR(("%s request_irq failed IRQ=%d\n",
3534 port_array[0]->device_name,
3535 port_array[0]->irq_level));
3536 } else {
3537 port_array[0]->irq_requested = true;
3538 adapter_test(port_array[0]);
3539 for (i=1 ; i < port_count ; i++) {
3540 port_array[i]->init_error = port_array[0]->init_error;
3541 port_array[i]->gpio_present = port_array[0]->gpio_present;
3542 }
3543 }
3544 }
3545
3546 for (i=0; i < port_count; ++i)
3547 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3548 }
3549
3550 static int __devinit init_one(struct pci_dev *dev,
3551 const struct pci_device_id *ent)
3552 {
3553 if (pci_enable_device(dev)) {
3554 printk("error enabling pci device %p\n", dev);
3555 return -EIO;
3556 }
3557 pci_set_master(dev);
3558 device_init(slgt_device_count, dev);
3559 return 0;
3560 }
3561
3562 static void __devexit remove_one(struct pci_dev *dev)
3563 {
3564 }
3565
3566 static const struct tty_operations ops = {
3567 .open = open,
3568 .close = close,
3569 .write = write,
3570 .put_char = put_char,
3571 .flush_chars = flush_chars,
3572 .write_room = write_room,
3573 .chars_in_buffer = chars_in_buffer,
3574 .flush_buffer = flush_buffer,
3575 .ioctl = ioctl,
3576 .compat_ioctl = slgt_compat_ioctl,
3577 .throttle = throttle,
3578 .unthrottle = unthrottle,
3579 .send_xchar = send_xchar,
3580 .break_ctl = set_break,
3581 .wait_until_sent = wait_until_sent,
3582 .read_proc = read_proc,
3583 .set_termios = set_termios,
3584 .stop = tx_hold,
3585 .start = tx_release,
3586 .hangup = hangup,
3587 .tiocmget = tiocmget,
3588 .tiocmset = tiocmset,
3589 };
3590
3591 static void slgt_cleanup(void)
3592 {
3593 int rc;
3594 struct slgt_info *info;
3595 struct slgt_info *tmp;
3596
3597 printk("unload %s %s\n", driver_name, driver_version);
3598
3599 if (serial_driver) {
3600 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3601 tty_unregister_device(serial_driver, info->line);
3602 if ((rc = tty_unregister_driver(serial_driver)))
3603 DBGERR(("tty_unregister_driver error=%d\n", rc));
3604 put_tty_driver(serial_driver);
3605 }
3606
3607 /* reset devices */
3608 info = slgt_device_list;
3609 while(info) {
3610 reset_port(info);
3611 info = info->next_device;
3612 }
3613
3614 /* release devices */
3615 info = slgt_device_list;
3616 while(info) {
3617 #if SYNCLINK_GENERIC_HDLC
3618 hdlcdev_exit(info);
3619 #endif
3620 free_dma_bufs(info);
3621 free_tmp_rbuf(info);
3622 if (info->port_num == 0)
3623 release_resources(info);
3624 tmp = info;
3625 info = info->next_device;
3626 kfree(tmp);
3627 }
3628
3629 if (pci_registered)
3630 pci_unregister_driver(&pci_driver);
3631 }
3632
3633 /*
3634 * Driver initialization entry point.
3635 */
3636 static int __init slgt_init(void)
3637 {
3638 int rc;
3639
3640 printk("%s %s\n", driver_name, driver_version);
3641
3642 serial_driver = alloc_tty_driver(MAX_DEVICES);
3643 if (!serial_driver) {
3644 printk("%s can't allocate tty driver\n", driver_name);
3645 return -ENOMEM;
3646 }
3647
3648 /* Initialize the tty_driver structure */
3649
3650 serial_driver->owner = THIS_MODULE;
3651 serial_driver->driver_name = tty_driver_name;
3652 serial_driver->name = tty_dev_prefix;
3653 serial_driver->major = ttymajor;
3654 serial_driver->minor_start = 64;
3655 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3656 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3657 serial_driver->init_termios = tty_std_termios;
3658 serial_driver->init_termios.c_cflag =
3659 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3660 serial_driver->init_termios.c_ispeed = 9600;
3661 serial_driver->init_termios.c_ospeed = 9600;
3662 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3663 tty_set_operations(serial_driver, &ops);
3664 if ((rc = tty_register_driver(serial_driver)) < 0) {
3665 DBGERR(("%s can't register serial driver\n", driver_name));
3666 put_tty_driver(serial_driver);
3667 serial_driver = NULL;
3668 goto error;
3669 }
3670
3671 printk("%s %s, tty major#%d\n",
3672 driver_name, driver_version,
3673 serial_driver->major);
3674
3675 slgt_device_count = 0;
3676 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3677 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3678 goto error;
3679 }
3680 pci_registered = true;
3681
3682 if (!slgt_device_list)
3683 printk("%s no devices found\n",driver_name);
3684
3685 return 0;
3686
3687 error:
3688 slgt_cleanup();
3689 return rc;
3690 }
3691
3692 static void __exit slgt_exit(void)
3693 {
3694 slgt_cleanup();
3695 }
3696
3697 module_init(slgt_init);
3698 module_exit(slgt_exit);
3699
3700 /*
3701 * register access routines
3702 */
3703
3704 #define CALC_REGADDR() \
3705 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3706 if (addr >= 0x80) \
3707 reg_addr += (info->port_num) * 32;
3708
3709 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3710 {
3711 CALC_REGADDR();
3712 return readb((void __iomem *)reg_addr);
3713 }
3714
3715 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3716 {
3717 CALC_REGADDR();
3718 writeb(value, (void __iomem *)reg_addr);
3719 }
3720
3721 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3722 {
3723 CALC_REGADDR();
3724 return readw((void __iomem *)reg_addr);
3725 }
3726
3727 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3728 {
3729 CALC_REGADDR();
3730 writew(value, (void __iomem *)reg_addr);
3731 }
3732
3733 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3734 {
3735 CALC_REGADDR();
3736 return readl((void __iomem *)reg_addr);
3737 }
3738
3739 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3740 {
3741 CALC_REGADDR();
3742 writel(value, (void __iomem *)reg_addr);
3743 }
3744
3745 static void rdma_reset(struct slgt_info *info)
3746 {
3747 unsigned int i;
3748
3749 /* set reset bit */
3750 wr_reg32(info, RDCSR, BIT1);
3751
3752 /* wait for enable bit cleared */
3753 for(i=0 ; i < 1000 ; i++)
3754 if (!(rd_reg32(info, RDCSR) & BIT0))
3755 break;
3756 }
3757
3758 static void tdma_reset(struct slgt_info *info)
3759 {
3760 unsigned int i;
3761
3762 /* set reset bit */
3763 wr_reg32(info, TDCSR, BIT1);
3764
3765 /* wait for enable bit cleared */
3766 for(i=0 ; i < 1000 ; i++)
3767 if (!(rd_reg32(info, TDCSR) & BIT0))
3768 break;
3769 }
3770
3771 /*
3772 * enable internal loopback
3773 * TxCLK and RxCLK are generated from BRG
3774 * and TxD is looped back to RxD internally.
3775 */
3776 static void enable_loopback(struct slgt_info *info)
3777 {
3778 /* SCR (serial control) BIT2=looopback enable */
3779 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3780
3781 if (info->params.mode != MGSL_MODE_ASYNC) {
3782 /* CCR (clock control)
3783 * 07..05 tx clock source (010 = BRG)
3784 * 04..02 rx clock source (010 = BRG)
3785 * 01 auxclk enable (0 = disable)
3786 * 00 BRG enable (1 = enable)
3787 *
3788 * 0100 1001
3789 */
3790 wr_reg8(info, CCR, 0x49);
3791
3792 /* set speed if available, otherwise use default */
3793 if (info->params.clock_speed)
3794 set_rate(info, info->params.clock_speed);
3795 else
3796 set_rate(info, 3686400);
3797 }
3798 }
3799
3800 /*
3801 * set baud rate generator to specified rate
3802 */
3803 static void set_rate(struct slgt_info *info, u32 rate)
3804 {
3805 unsigned int div;
3806 static unsigned int osc = 14745600;
3807
3808 /* div = osc/rate - 1
3809 *
3810 * Round div up if osc/rate is not integer to
3811 * force to next slowest rate.
3812 */
3813
3814 if (rate) {
3815 div = osc/rate;
3816 if (!(osc % rate) && div)
3817 div--;
3818 wr_reg16(info, BDR, (unsigned short)div);
3819 }
3820 }
3821
3822 static void rx_stop(struct slgt_info *info)
3823 {
3824 unsigned short val;
3825
3826 /* disable and reset receiver */
3827 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3828 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3829 wr_reg16(info, RCR, val); /* clear reset bit */
3830
3831 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3832
3833 /* clear pending rx interrupts */
3834 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3835
3836 rdma_reset(info);
3837
3838 info->rx_enabled = false;
3839 info->rx_restart = false;
3840 }
3841
3842 static void rx_start(struct slgt_info *info)
3843 {
3844 unsigned short val;
3845
3846 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3847
3848 /* clear pending rx overrun IRQ */
3849 wr_reg16(info, SSR, IRQ_RXOVER);
3850
3851 /* reset and disable receiver */
3852 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3853 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3854 wr_reg16(info, RCR, val); /* clear reset bit */
3855
3856 rdma_reset(info);
3857 reset_rbufs(info);
3858
3859 /* set 1st descriptor address */
3860 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3861
3862 if (info->params.mode != MGSL_MODE_ASYNC) {
3863 /* enable rx DMA and DMA interrupt */
3864 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3865 } else {
3866 /* enable saving of rx status, rx DMA and DMA interrupt */
3867 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3868 }
3869
3870 slgt_irq_on(info, IRQ_RXOVER);
3871
3872 /* enable receiver */
3873 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3874
3875 info->rx_restart = false;
3876 info->rx_enabled = true;
3877 }
3878
3879 static void tx_start(struct slgt_info *info)
3880 {
3881 if (!info->tx_enabled) {
3882 wr_reg16(info, TCR,
3883 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3884 info->tx_enabled = true;
3885 }
3886
3887 if (info->tx_count) {
3888 info->drop_rts_on_tx_done = false;
3889
3890 if (info->params.mode != MGSL_MODE_ASYNC) {
3891 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3892 get_signals(info);
3893 if (!(info->signals & SerialSignal_RTS)) {
3894 info->signals |= SerialSignal_RTS;
3895 set_signals(info);
3896 info->drop_rts_on_tx_done = true;
3897 }
3898 }
3899
3900 slgt_irq_off(info, IRQ_TXDATA);
3901 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3902 /* clear tx idle and underrun status bits */
3903 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3904 if (info->params.mode == MGSL_MODE_HDLC)
3905 mod_timer(&info->tx_timer, jiffies +
3906 msecs_to_jiffies(5000));
3907 } else {
3908 slgt_irq_off(info, IRQ_TXDATA);
3909 slgt_irq_on(info, IRQ_TXIDLE);
3910 /* clear tx idle status bit */
3911 wr_reg16(info, SSR, IRQ_TXIDLE);
3912 }
3913 tdma_start(info);
3914 info->tx_active = true;
3915 }
3916 }
3917
3918 /*
3919 * start transmit DMA if inactive and there are unsent buffers
3920 */
3921 static void tdma_start(struct slgt_info *info)
3922 {
3923 unsigned int i;
3924
3925 if (rd_reg32(info, TDCSR) & BIT0)
3926 return;
3927
3928 /* transmit DMA inactive, check for unsent buffers */
3929 i = info->tbuf_start;
3930 while (!desc_count(info->tbufs[i])) {
3931 if (++i == info->tbuf_count)
3932 i = 0;
3933 if (i == info->tbuf_current)
3934 return;
3935 }
3936 info->tbuf_start = i;
3937
3938 /* there are unsent buffers, start transmit DMA */
3939
3940 /* reset needed if previous error condition */
3941 tdma_reset(info);
3942
3943 /* set 1st descriptor address */
3944 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3945 switch(info->params.mode) {
3946 case MGSL_MODE_RAW:
3947 case MGSL_MODE_MONOSYNC:
3948 case MGSL_MODE_BISYNC:
3949 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3950 break;
3951 default:
3952 wr_reg32(info, TDCSR, BIT0); /* DMA enable */
3953 }
3954 }
3955
3956 static void tx_stop(struct slgt_info *info)
3957 {
3958 unsigned short val;
3959
3960 del_timer(&info->tx_timer);
3961
3962 tdma_reset(info);
3963
3964 /* reset and disable transmitter */
3965 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3966 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3967
3968 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3969
3970 /* clear tx idle and underrun status bit */
3971 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3972
3973 reset_tbufs(info);
3974
3975 info->tx_enabled = false;
3976 info->tx_active = false;
3977 }
3978
3979 static void reset_port(struct slgt_info *info)
3980 {
3981 if (!info->reg_addr)
3982 return;
3983
3984 tx_stop(info);
3985 rx_stop(info);
3986
3987 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3988 set_signals(info);
3989
3990 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3991 }
3992
3993 static void reset_adapter(struct slgt_info *info)
3994 {
3995 int i;
3996 for (i=0; i < info->port_count; ++i) {
3997 if (info->port_array[i])
3998 reset_port(info->port_array[i]);
3999 }
4000 }
4001
4002 static void async_mode(struct slgt_info *info)
4003 {
4004 unsigned short val;
4005
4006 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4007 tx_stop(info);
4008 rx_stop(info);
4009
4010 /* TCR (tx control)
4011 *
4012 * 15..13 mode, 010=async
4013 * 12..10 encoding, 000=NRZ
4014 * 09 parity enable
4015 * 08 1=odd parity, 0=even parity
4016 * 07 1=RTS driver control
4017 * 06 1=break enable
4018 * 05..04 character length
4019 * 00=5 bits
4020 * 01=6 bits
4021 * 10=7 bits
4022 * 11=8 bits
4023 * 03 0=1 stop bit, 1=2 stop bits
4024 * 02 reset
4025 * 01 enable
4026 * 00 auto-CTS enable
4027 */
4028 val = 0x4000;
4029
4030 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4031 val |= BIT7;
4032
4033 if (info->params.parity != ASYNC_PARITY_NONE) {
4034 val |= BIT9;
4035 if (info->params.parity == ASYNC_PARITY_ODD)
4036 val |= BIT8;
4037 }
4038
4039 switch (info->params.data_bits)
4040 {
4041 case 6: val |= BIT4; break;
4042 case 7: val |= BIT5; break;
4043 case 8: val |= BIT5 + BIT4; break;
4044 }
4045
4046 if (info->params.stop_bits != 1)
4047 val |= BIT3;
4048
4049 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4050 val |= BIT0;
4051
4052 wr_reg16(info, TCR, val);
4053
4054 /* RCR (rx control)
4055 *
4056 * 15..13 mode, 010=async
4057 * 12..10 encoding, 000=NRZ
4058 * 09 parity enable
4059 * 08 1=odd parity, 0=even parity
4060 * 07..06 reserved, must be 0
4061 * 05..04 character length
4062 * 00=5 bits
4063 * 01=6 bits
4064 * 10=7 bits
4065 * 11=8 bits
4066 * 03 reserved, must be zero
4067 * 02 reset
4068 * 01 enable
4069 * 00 auto-DCD enable
4070 */
4071 val = 0x4000;
4072
4073 if (info->params.parity != ASYNC_PARITY_NONE) {
4074 val |= BIT9;
4075 if (info->params.parity == ASYNC_PARITY_ODD)
4076 val |= BIT8;
4077 }
4078
4079 switch (info->params.data_bits)
4080 {
4081 case 6: val |= BIT4; break;
4082 case 7: val |= BIT5; break;
4083 case 8: val |= BIT5 + BIT4; break;
4084 }
4085
4086 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4087 val |= BIT0;
4088
4089 wr_reg16(info, RCR, val);
4090
4091 /* CCR (clock control)
4092 *
4093 * 07..05 011 = tx clock source is BRG/16
4094 * 04..02 010 = rx clock source is BRG
4095 * 01 0 = auxclk disabled
4096 * 00 1 = BRG enabled
4097 *
4098 * 0110 1001
4099 */
4100 wr_reg8(info, CCR, 0x69);
4101
4102 msc_set_vcr(info);
4103
4104 /* SCR (serial control)
4105 *
4106 * 15 1=tx req on FIFO half empty
4107 * 14 1=rx req on FIFO half full
4108 * 13 tx data IRQ enable
4109 * 12 tx idle IRQ enable
4110 * 11 rx break on IRQ enable
4111 * 10 rx data IRQ enable
4112 * 09 rx break off IRQ enable
4113 * 08 overrun IRQ enable
4114 * 07 DSR IRQ enable
4115 * 06 CTS IRQ enable
4116 * 05 DCD IRQ enable
4117 * 04 RI IRQ enable
4118 * 03 reserved, must be zero
4119 * 02 1=txd->rxd internal loopback enable
4120 * 01 reserved, must be zero
4121 * 00 1=master IRQ enable
4122 */
4123 val = BIT15 + BIT14 + BIT0;
4124 wr_reg16(info, SCR, val);
4125
4126 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4127
4128 set_rate(info, info->params.data_rate * 16);
4129
4130 if (info->params.loopback)
4131 enable_loopback(info);
4132 }
4133
4134 static void sync_mode(struct slgt_info *info)
4135 {
4136 unsigned short val;
4137
4138 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4139 tx_stop(info);
4140 rx_stop(info);
4141
4142 /* TCR (tx control)
4143 *
4144 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4145 * 12..10 encoding
4146 * 09 CRC enable
4147 * 08 CRC32
4148 * 07 1=RTS driver control
4149 * 06 preamble enable
4150 * 05..04 preamble length
4151 * 03 share open/close flag
4152 * 02 reset
4153 * 01 enable
4154 * 00 auto-CTS enable
4155 */
4156 val = 0;
4157
4158 switch(info->params.mode) {
4159 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4160 case MGSL_MODE_BISYNC: val |= BIT15; break;
4161 case MGSL_MODE_RAW: val |= BIT13; break;
4162 }
4163 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4164 val |= BIT7;
4165
4166 switch(info->params.encoding)
4167 {
4168 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4169 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4170 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4171 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4172 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4173 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4174 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4175 }
4176
4177 switch (info->params.crc_type & HDLC_CRC_MASK)
4178 {
4179 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4180 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4181 }
4182
4183 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4184 val |= BIT6;
4185
4186 switch (info->params.preamble_length)
4187 {
4188 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4189 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4190 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4191 }
4192
4193 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4194 val |= BIT0;
4195
4196 wr_reg16(info, TCR, val);
4197
4198 /* TPR (transmit preamble) */
4199
4200 switch (info->params.preamble)
4201 {
4202 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4203 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4204 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4205 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4206 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4207 default: val = 0x7e; break;
4208 }
4209 wr_reg8(info, TPR, (unsigned char)val);
4210
4211 /* RCR (rx control)
4212 *
4213 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4214 * 12..10 encoding
4215 * 09 CRC enable
4216 * 08 CRC32
4217 * 07..03 reserved, must be 0
4218 * 02 reset
4219 * 01 enable
4220 * 00 auto-DCD enable
4221 */
4222 val = 0;
4223
4224 switch(info->params.mode) {
4225 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4226 case MGSL_MODE_BISYNC: val |= BIT15; break;
4227 case MGSL_MODE_RAW: val |= BIT13; break;
4228 }
4229
4230 switch(info->params.encoding)
4231 {
4232 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4233 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4234 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4235 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4236 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4237 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4238 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4239 }
4240
4241 switch (info->params.crc_type & HDLC_CRC_MASK)
4242 {
4243 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4244 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4245 }
4246
4247 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4248 val |= BIT0;
4249
4250 wr_reg16(info, RCR, val);
4251
4252 /* CCR (clock control)
4253 *
4254 * 07..05 tx clock source
4255 * 04..02 rx clock source
4256 * 01 auxclk enable
4257 * 00 BRG enable
4258 */
4259 val = 0;
4260
4261 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4262 {
4263 // when RxC source is DPLL, BRG generates 16X DPLL
4264 // reference clock, so take TxC from BRG/16 to get
4265 // transmit clock at actual data rate
4266 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4267 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4268 else
4269 val |= BIT6; /* 010, txclk = BRG */
4270 }
4271 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4272 val |= BIT7; /* 100, txclk = DPLL Input */
4273 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4274 val |= BIT5; /* 001, txclk = RXC Input */
4275
4276 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4277 val |= BIT3; /* 010, rxclk = BRG */
4278 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4279 val |= BIT4; /* 100, rxclk = DPLL */
4280 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4281 val |= BIT2; /* 001, rxclk = TXC Input */
4282
4283 if (info->params.clock_speed)
4284 val |= BIT1 + BIT0;
4285
4286 wr_reg8(info, CCR, (unsigned char)val);
4287
4288 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4289 {
4290 // program DPLL mode
4291 switch(info->params.encoding)
4292 {
4293 case HDLC_ENCODING_BIPHASE_MARK:
4294 case HDLC_ENCODING_BIPHASE_SPACE:
4295 val = BIT7; break;
4296 case HDLC_ENCODING_BIPHASE_LEVEL:
4297 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4298 val = BIT7 + BIT6; break;
4299 default: val = BIT6; // NRZ encodings
4300 }
4301 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4302
4303 // DPLL requires a 16X reference clock from BRG
4304 set_rate(info, info->params.clock_speed * 16);
4305 }
4306 else
4307 set_rate(info, info->params.clock_speed);
4308
4309 tx_set_idle(info);
4310
4311 msc_set_vcr(info);
4312
4313 /* SCR (serial control)
4314 *
4315 * 15 1=tx req on FIFO half empty
4316 * 14 1=rx req on FIFO half full
4317 * 13 tx data IRQ enable
4318 * 12 tx idle IRQ enable
4319 * 11 underrun IRQ enable
4320 * 10 rx data IRQ enable
4321 * 09 rx idle IRQ enable
4322 * 08 overrun IRQ enable
4323 * 07 DSR IRQ enable
4324 * 06 CTS IRQ enable
4325 * 05 DCD IRQ enable
4326 * 04 RI IRQ enable
4327 * 03 reserved, must be zero
4328 * 02 1=txd->rxd internal loopback enable
4329 * 01 reserved, must be zero
4330 * 00 1=master IRQ enable
4331 */
4332 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4333
4334 if (info->params.loopback)
4335 enable_loopback(info);
4336 }
4337
4338 /*
4339 * set transmit idle mode
4340 */
4341 static void tx_set_idle(struct slgt_info *info)
4342 {
4343 unsigned char val;
4344 unsigned short tcr;
4345
4346 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4347 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4348 */
4349 tcr = rd_reg16(info, TCR);
4350 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4351 /* disable preamble, set idle size to 16 bits */
4352 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4353 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4354 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4355 } else if (!(tcr & BIT6)) {
4356 /* preamble is disabled, set idle size to 8 bits */
4357 tcr &= ~(BIT5 + BIT4);
4358 }
4359 wr_reg16(info, TCR, tcr);
4360
4361 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4362 /* LSB of custom tx idle specified in tx idle register */
4363 val = (unsigned char)(info->idle_mode & 0xff);
4364 } else {
4365 /* standard 8 bit idle patterns */
4366 switch(info->idle_mode)
4367 {
4368 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4369 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4370 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4371 case HDLC_TXIDLE_ZEROS:
4372 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4373 default: val = 0xff;
4374 }
4375 }
4376
4377 wr_reg8(info, TIR, val);
4378 }
4379
4380 /*
4381 * get state of V24 status (input) signals
4382 */
4383 static void get_signals(struct slgt_info *info)
4384 {
4385 unsigned short status = rd_reg16(info, SSR);
4386
4387 /* clear all serial signals except DTR and RTS */
4388 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4389
4390 if (status & BIT3)
4391 info->signals |= SerialSignal_DSR;
4392 if (status & BIT2)
4393 info->signals |= SerialSignal_CTS;
4394 if (status & BIT1)
4395 info->signals |= SerialSignal_DCD;
4396 if (status & BIT0)
4397 info->signals |= SerialSignal_RI;
4398 }
4399
4400 /*
4401 * set V.24 Control Register based on current configuration
4402 */
4403 static void msc_set_vcr(struct slgt_info *info)
4404 {
4405 unsigned char val = 0;
4406
4407 /* VCR (V.24 control)
4408 *
4409 * 07..04 serial IF select
4410 * 03 DTR
4411 * 02 RTS
4412 * 01 LL
4413 * 00 RL
4414 */
4415
4416 switch(info->if_mode & MGSL_INTERFACE_MASK)
4417 {
4418 case MGSL_INTERFACE_RS232:
4419 val |= BIT5; /* 0010 */
4420 break;
4421 case MGSL_INTERFACE_V35:
4422 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4423 break;
4424 case MGSL_INTERFACE_RS422:
4425 val |= BIT6; /* 0100 */
4426 break;
4427 }
4428
4429 if (info->signals & SerialSignal_DTR)
4430 val |= BIT3;
4431 if (info->signals & SerialSignal_RTS)
4432 val |= BIT2;
4433 if (info->if_mode & MGSL_INTERFACE_LL)
4434 val |= BIT1;
4435 if (info->if_mode & MGSL_INTERFACE_RL)
4436 val |= BIT0;
4437 wr_reg8(info, VCR, val);
4438 }
4439
4440 /*
4441 * set state of V24 control (output) signals
4442 */
4443 static void set_signals(struct slgt_info *info)
4444 {
4445 unsigned char val = rd_reg8(info, VCR);
4446 if (info->signals & SerialSignal_DTR)
4447 val |= BIT3;
4448 else
4449 val &= ~BIT3;
4450 if (info->signals & SerialSignal_RTS)
4451 val |= BIT2;
4452 else
4453 val &= ~BIT2;
4454 wr_reg8(info, VCR, val);
4455 }
4456
4457 /*
4458 * free range of receive DMA buffers (i to last)
4459 */
4460 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4461 {
4462 int done = 0;
4463
4464 while(!done) {
4465 /* reset current buffer for reuse */
4466 info->rbufs[i].status = 0;
4467 switch(info->params.mode) {
4468 case MGSL_MODE_RAW:
4469 case MGSL_MODE_MONOSYNC:
4470 case MGSL_MODE_BISYNC:
4471 set_desc_count(info->rbufs[i], info->raw_rx_size);
4472 break;
4473 default:
4474 set_desc_count(info->rbufs[i], DMABUFSIZE);
4475 }
4476
4477 if (i == last)
4478 done = 1;
4479 if (++i == info->rbuf_count)
4480 i = 0;
4481 }
4482 info->rbuf_current = i;
4483 }
4484
4485 /*
4486 * mark all receive DMA buffers as free
4487 */
4488 static void reset_rbufs(struct slgt_info *info)
4489 {
4490 free_rbufs(info, 0, info->rbuf_count - 1);
4491 }
4492
4493 /*
4494 * pass receive HDLC frame to upper layer
4495 *
4496 * return true if frame available, otherwise false
4497 */
4498 static bool rx_get_frame(struct slgt_info *info)
4499 {
4500 unsigned int start, end;
4501 unsigned short status;
4502 unsigned int framesize = 0;
4503 unsigned long flags;
4504 struct tty_struct *tty = info->tty;
4505 unsigned char addr_field = 0xff;
4506 unsigned int crc_size = 0;
4507
4508 switch (info->params.crc_type & HDLC_CRC_MASK) {
4509 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4510 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4511 }
4512
4513 check_again:
4514
4515 framesize = 0;
4516 addr_field = 0xff;
4517 start = end = info->rbuf_current;
4518
4519 for (;;) {
4520 if (!desc_complete(info->rbufs[end]))
4521 goto cleanup;
4522
4523 if (framesize == 0 && info->params.addr_filter != 0xff)
4524 addr_field = info->rbufs[end].buf[0];
4525
4526 framesize += desc_count(info->rbufs[end]);
4527
4528 if (desc_eof(info->rbufs[end]))
4529 break;
4530
4531 if (++end == info->rbuf_count)
4532 end = 0;
4533
4534 if (end == info->rbuf_current) {
4535 if (info->rx_enabled){
4536 spin_lock_irqsave(&info->lock,flags);
4537 rx_start(info);
4538 spin_unlock_irqrestore(&info->lock,flags);
4539 }
4540 goto cleanup;
4541 }
4542 }
4543
4544 /* status
4545 *
4546 * 15 buffer complete
4547 * 14..06 reserved
4548 * 05..04 residue
4549 * 02 eof (end of frame)
4550 * 01 CRC error
4551 * 00 abort
4552 */
4553 status = desc_status(info->rbufs[end]);
4554
4555 /* ignore CRC bit if not using CRC (bit is undefined) */
4556 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4557 status &= ~BIT1;
4558
4559 if (framesize == 0 ||
4560 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4561 free_rbufs(info, start, end);
4562 goto check_again;
4563 }
4564
4565 if (framesize < (2 + crc_size) || status & BIT0) {
4566 info->icount.rxshort++;
4567 framesize = 0;
4568 } else if (status & BIT1) {
4569 info->icount.rxcrc++;
4570 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4571 framesize = 0;
4572 }
4573
4574 #if SYNCLINK_GENERIC_HDLC
4575 if (framesize == 0) {
4576 struct net_device_stats *stats = hdlc_stats(info->netdev);
4577 stats->rx_errors++;
4578 stats->rx_frame_errors++;
4579 }
4580 #endif
4581
4582 DBGBH(("%s rx frame status=%04X size=%d\n",
4583 info->device_name, status, framesize));
4584 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, DMABUFSIZE), "rx");
4585
4586 if (framesize) {
4587 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4588 framesize -= crc_size;
4589 crc_size = 0;
4590 }
4591
4592 if (framesize > info->max_frame_size + crc_size)
4593 info->icount.rxlong++;
4594 else {
4595 /* copy dma buffer(s) to contiguous temp buffer */
4596 int copy_count = framesize;
4597 int i = start;
4598 unsigned char *p = info->tmp_rbuf;
4599 info->tmp_rbuf_count = framesize;
4600
4601 info->icount.rxok++;
4602
4603 while(copy_count) {
4604 int partial_count = min(copy_count, DMABUFSIZE);
4605 memcpy(p, info->rbufs[i].buf, partial_count);
4606 p += partial_count;
4607 copy_count -= partial_count;
4608 if (++i == info->rbuf_count)
4609 i = 0;
4610 }
4611
4612 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4613 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4614 framesize++;
4615 }
4616
4617 #if SYNCLINK_GENERIC_HDLC
4618 if (info->netcount)
4619 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4620 else
4621 #endif
4622 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4623 }
4624 }
4625 free_rbufs(info, start, end);
4626 return true;
4627
4628 cleanup:
4629 return false;
4630 }
4631
4632 /*
4633 * pass receive buffer (RAW synchronous mode) to tty layer
4634 * return true if buffer available, otherwise false
4635 */
4636 static bool rx_get_buf(struct slgt_info *info)
4637 {
4638 unsigned int i = info->rbuf_current;
4639 unsigned int count;
4640
4641 if (!desc_complete(info->rbufs[i]))
4642 return false;
4643 count = desc_count(info->rbufs[i]);
4644 switch(info->params.mode) {
4645 case MGSL_MODE_MONOSYNC:
4646 case MGSL_MODE_BISYNC:
4647 /* ignore residue in byte synchronous modes */
4648 if (desc_residue(info->rbufs[i]))
4649 count--;
4650 break;
4651 }
4652 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4653 DBGINFO(("rx_get_buf size=%d\n", count));
4654 if (count)
4655 ldisc_receive_buf(info->tty, info->rbufs[i].buf,
4656 info->flag_buf, count);
4657 free_rbufs(info, i, i);
4658 return true;
4659 }
4660
4661 static void reset_tbufs(struct slgt_info *info)
4662 {
4663 unsigned int i;
4664 info->tbuf_current = 0;
4665 for (i=0 ; i < info->tbuf_count ; i++) {
4666 info->tbufs[i].status = 0;
4667 info->tbufs[i].count = 0;
4668 }
4669 }
4670
4671 /*
4672 * return number of free transmit DMA buffers
4673 */
4674 static unsigned int free_tbuf_count(struct slgt_info *info)
4675 {
4676 unsigned int count = 0;
4677 unsigned int i = info->tbuf_current;
4678
4679 do
4680 {
4681 if (desc_count(info->tbufs[i]))
4682 break; /* buffer in use */
4683 ++count;
4684 if (++i == info->tbuf_count)
4685 i=0;
4686 } while (i != info->tbuf_current);
4687
4688 /* if tx DMA active, last zero count buffer is in use */
4689 if (count && (rd_reg32(info, TDCSR) & BIT0))
4690 --count;
4691
4692 return count;
4693 }
4694
4695 /*
4696 * load transmit DMA buffer(s) with data
4697 */
4698 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4699 {
4700 unsigned short count;
4701 unsigned int i;
4702 struct slgt_desc *d;
4703
4704 if (size == 0)
4705 return;
4706
4707 DBGDATA(info, buf, size, "tx");
4708
4709 info->tbuf_start = i = info->tbuf_current;
4710
4711 while (size) {
4712 d = &info->tbufs[i];
4713 if (++i == info->tbuf_count)
4714 i = 0;
4715
4716 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4717 memcpy(d->buf, buf, count);
4718
4719 size -= count;
4720 buf += count;
4721
4722 /*
4723 * set EOF bit for last buffer of HDLC frame or
4724 * for every buffer in raw mode
4725 */
4726 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4727 info->params.mode == MGSL_MODE_RAW)
4728 set_desc_eof(*d, 1);
4729 else
4730 set_desc_eof(*d, 0);
4731
4732 set_desc_count(*d, count);
4733 }
4734
4735 info->tbuf_current = i;
4736 }
4737
4738 static int register_test(struct slgt_info *info)
4739 {
4740 static unsigned short patterns[] =
4741 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4742 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4743 unsigned int i;
4744 int rc = 0;
4745
4746 for (i=0 ; i < count ; i++) {
4747 wr_reg16(info, TIR, patterns[i]);
4748 wr_reg16(info, BDR, patterns[(i+1)%count]);
4749 if ((rd_reg16(info, TIR) != patterns[i]) ||
4750 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4751 rc = -ENODEV;
4752 break;
4753 }
4754 }
4755 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4756 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4757 return rc;
4758 }
4759
4760 static int irq_test(struct slgt_info *info)
4761 {
4762 unsigned long timeout;
4763 unsigned long flags;
4764 struct tty_struct *oldtty = info->tty;
4765 u32 speed = info->params.data_rate;
4766
4767 info->params.data_rate = 921600;
4768 info->tty = NULL;
4769
4770 spin_lock_irqsave(&info->lock, flags);
4771 async_mode(info);
4772 slgt_irq_on(info, IRQ_TXIDLE);
4773
4774 /* enable transmitter */
4775 wr_reg16(info, TCR,
4776 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4777
4778 /* write one byte and wait for tx idle */
4779 wr_reg16(info, TDR, 0);
4780
4781 /* assume failure */
4782 info->init_error = DiagStatus_IrqFailure;
4783 info->irq_occurred = false;
4784
4785 spin_unlock_irqrestore(&info->lock, flags);
4786
4787 timeout=100;
4788 while(timeout-- && !info->irq_occurred)
4789 msleep_interruptible(10);
4790
4791 spin_lock_irqsave(&info->lock,flags);
4792 reset_port(info);
4793 spin_unlock_irqrestore(&info->lock,flags);
4794
4795 info->params.data_rate = speed;
4796 info->tty = oldtty;
4797
4798 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4799 return info->irq_occurred ? 0 : -ENODEV;
4800 }
4801
4802 static int loopback_test_rx(struct slgt_info *info)
4803 {
4804 unsigned char *src, *dest;
4805 int count;
4806
4807 if (desc_complete(info->rbufs[0])) {
4808 count = desc_count(info->rbufs[0]);
4809 src = info->rbufs[0].buf;
4810 dest = info->tmp_rbuf;
4811
4812 for( ; count ; count-=2, src+=2) {
4813 /* src=data byte (src+1)=status byte */
4814 if (!(*(src+1) & (BIT9 + BIT8))) {
4815 *dest = *src;
4816 dest++;
4817 info->tmp_rbuf_count++;
4818 }
4819 }
4820 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4821 return 1;
4822 }
4823 return 0;
4824 }
4825
4826 static int loopback_test(struct slgt_info *info)
4827 {
4828 #define TESTFRAMESIZE 20
4829
4830 unsigned long timeout;
4831 u16 count = TESTFRAMESIZE;
4832 unsigned char buf[TESTFRAMESIZE];
4833 int rc = -ENODEV;
4834 unsigned long flags;
4835
4836 struct tty_struct *oldtty = info->tty;
4837 MGSL_PARAMS params;
4838
4839 memcpy(&params, &info->params, sizeof(params));
4840
4841 info->params.mode = MGSL_MODE_ASYNC;
4842 info->params.data_rate = 921600;
4843 info->params.loopback = 1;
4844 info->tty = NULL;
4845
4846 /* build and send transmit frame */
4847 for (count = 0; count < TESTFRAMESIZE; ++count)
4848 buf[count] = (unsigned char)count;
4849
4850 info->tmp_rbuf_count = 0;
4851 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4852
4853 /* program hardware for HDLC and enabled receiver */
4854 spin_lock_irqsave(&info->lock,flags);
4855 async_mode(info);
4856 rx_start(info);
4857 info->tx_count = count;
4858 tx_load(info, buf, count);
4859 tx_start(info);
4860 spin_unlock_irqrestore(&info->lock, flags);
4861
4862 /* wait for receive complete */
4863 for (timeout = 100; timeout; --timeout) {
4864 msleep_interruptible(10);
4865 if (loopback_test_rx(info)) {
4866 rc = 0;
4867 break;
4868 }
4869 }
4870
4871 /* verify received frame length and contents */
4872 if (!rc && (info->tmp_rbuf_count != count ||
4873 memcmp(buf, info->tmp_rbuf, count))) {
4874 rc = -ENODEV;
4875 }
4876
4877 spin_lock_irqsave(&info->lock,flags);
4878 reset_adapter(info);
4879 spin_unlock_irqrestore(&info->lock,flags);
4880
4881 memcpy(&info->params, &params, sizeof(info->params));
4882 info->tty = oldtty;
4883
4884 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4885 return rc;
4886 }
4887
4888 static int adapter_test(struct slgt_info *info)
4889 {
4890 DBGINFO(("testing %s\n", info->device_name));
4891 if (register_test(info) < 0) {
4892 printk("register test failure %s addr=%08X\n",
4893 info->device_name, info->phys_reg_addr);
4894 } else if (irq_test(info) < 0) {
4895 printk("IRQ test failure %s IRQ=%d\n",
4896 info->device_name, info->irq_level);
4897 } else if (loopback_test(info) < 0) {
4898 printk("loopback test failure %s\n", info->device_name);
4899 }
4900 return info->init_error;
4901 }
4902
4903 /*
4904 * transmit timeout handler
4905 */
4906 static void tx_timeout(unsigned long context)
4907 {
4908 struct slgt_info *info = (struct slgt_info*)context;
4909 unsigned long flags;
4910
4911 DBGINFO(("%s tx_timeout\n", info->device_name));
4912 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4913 info->icount.txtimeout++;
4914 }
4915 spin_lock_irqsave(&info->lock,flags);
4916 info->tx_active = false;
4917 info->tx_count = 0;
4918 spin_unlock_irqrestore(&info->lock,flags);
4919
4920 #if SYNCLINK_GENERIC_HDLC
4921 if (info->netcount)
4922 hdlcdev_tx_done(info);
4923 else
4924 #endif
4925 bh_transmit(info);
4926 }
4927
4928 /*
4929 * receive buffer polling timer
4930 */
4931 static void rx_timeout(unsigned long context)
4932 {
4933 struct slgt_info *info = (struct slgt_info*)context;
4934 unsigned long flags;
4935
4936 DBGINFO(("%s rx_timeout\n", info->device_name));
4937 spin_lock_irqsave(&info->lock, flags);
4938 info->pending_bh |= BH_RECEIVE;
4939 spin_unlock_irqrestore(&info->lock, flags);
4940 bh_handler(&info->task);
4941 }
4942
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