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x86: constify function pointer tables
[linux-2.6/linux-2.6-openrd.git] / arch / x86 / kernel / setup_64.c
blob116687ade1807fd271287b707c7f8e4bdbbb6c3e
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/a.out.h>
19 #include <linux/screen_info.h>
20 #include <linux/ioport.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/initrd.h>
24 #include <linux/highmem.h>
25 #include <linux/bootmem.h>
26 #include <linux/module.h>
27 #include <asm/processor.h>
28 #include <linux/console.h>
29 #include <linux/seq_file.h>
30 #include <linux/crash_dump.h>
31 #include <linux/root_dev.h>
32 #include <linux/pci.h>
33 #include <linux/efi.h>
34 #include <linux/acpi.h>
35 #include <linux/kallsyms.h>
36 #include <linux/edd.h>
37 #include <linux/mmzone.h>
38 #include <linux/kexec.h>
39 #include <linux/cpufreq.h>
40 #include <linux/dmi.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/ctype.h>
43 #include <linux/uaccess.h>
44
45 #include <asm/mtrr.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
49 #include <asm/io.h>
50 #include <asm/smp.h>
51 #include <asm/msr.h>
52 #include <asm/desc.h>
53 #include <video/edid.h>
54 #include <asm/e820.h>
55 #include <asm/dma.h>
56 #include <asm/gart.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
61 #include <asm/mach_apic.h>
62 #include <asm/numa.h>
63 #include <asm/sections.h>
64 #include <asm/dmi.h>
65 #include <asm/cacheflush.h>
66 #include <asm/mce.h>
67 #include <asm/ds.h>
68 #include <asm/topology.h>
69
70 #ifdef CONFIG_PARAVIRT
71 #include <asm/paravirt.h>
72 #else
73 #define ARCH_SETUP
74 #endif
75
76 /*
77 * Machine setup..
78 */
79
80 struct cpuinfo_x86 boot_cpu_data __read_mostly;
81 EXPORT_SYMBOL(boot_cpu_data);
82
83 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
84
85 unsigned long mmu_cr4_features;
86
87 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
88 int bootloader_type;
89
90 unsigned long saved_video_mode;
91
92 int force_mwait __cpuinitdata;
93
94 /*
95 * Early DMI memory
96 */
97 int dmi_alloc_index;
98 char dmi_alloc_data[DMI_MAX_DATA];
99
100 /*
101 * Setup options
102 */
103 struct screen_info screen_info;
104 EXPORT_SYMBOL(screen_info);
105 struct sys_desc_table_struct {
106 unsigned short length;
107 unsigned char table[0];
108 };
109
110 struct edid_info edid_info;
111 EXPORT_SYMBOL_GPL(edid_info);
112
113 extern int root_mountflags;
114
115 char __initdata command_line[COMMAND_LINE_SIZE];
116
117 struct resource standard_io_resources[] = {
118 { .name = "dma1", .start = 0x00, .end = 0x1f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic1", .start = 0x20, .end = 0x21,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "timer0", .start = 0x40, .end = 0x43,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "timer1", .start = 0x50, .end = 0x53,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "keyboard", .start = 0x60, .end = 0x6f,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "pic2", .start = 0xa0, .end = 0xa1,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "dma2", .start = 0xc0, .end = 0xdf,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "fpu", .start = 0xf0, .end = 0xff,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
136 };
137
138 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
139
140 static struct resource data_resource = {
141 .name = "Kernel data",
142 .start = 0,
143 .end = 0,
144 .flags = IORESOURCE_RAM,
145 };
146 static struct resource code_resource = {
147 .name = "Kernel code",
148 .start = 0,
149 .end = 0,
150 .flags = IORESOURCE_RAM,
151 };
152 static struct resource bss_resource = {
153 .name = "Kernel bss",
154 .start = 0,
155 .end = 0,
156 .flags = IORESOURCE_RAM,
157 };
158
159 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
160
161 #ifdef CONFIG_PROC_VMCORE
162 /* elfcorehdr= specifies the location of elf core header
163 * stored by the crashed kernel. This option will be passed
164 * by kexec loader to the capture kernel.
165 */
166 static int __init setup_elfcorehdr(char *arg)
167 {
168 char *end;
169 if (!arg)
170 return -EINVAL;
171 elfcorehdr_addr = memparse(arg, &end);
172 return end > arg ? 0 : -EINVAL;
173 }
174 early_param("elfcorehdr", setup_elfcorehdr);
175 #endif
176
177 #ifndef CONFIG_NUMA
178 static void __init
179 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
180 {
181 unsigned long bootmap_size, bootmap;
182
183 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
184 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
185 if (bootmap == -1L)
186 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
187 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
188 e820_register_active_regions(0, start_pfn, end_pfn);
189 free_bootmem_with_active_regions(0, end_pfn);
190 reserve_bootmem(bootmap, bootmap_size);
191 }
192 #endif
193
194 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
195 struct edd edd;
196 #ifdef CONFIG_EDD_MODULE
197 EXPORT_SYMBOL(edd);
198 #endif
199 /**
200 * copy_edd() - Copy the BIOS EDD information
201 * from boot_params into a safe place.
202 *
203 */
204 static inline void copy_edd(void)
205 {
206 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
207 sizeof(edd.mbr_signature));
208 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
209 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
210 edd.edd_info_nr = boot_params.eddbuf_entries;
211 }
212 #else
213 static inline void copy_edd(void)
214 {
215 }
216 #endif
217
218 #ifdef CONFIG_KEXEC
219 static void __init reserve_crashkernel(void)
220 {
221 unsigned long long free_mem;
222 unsigned long long crash_size, crash_base;
223 int ret;
224
225 free_mem =
226 ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
227
228 ret = parse_crashkernel(boot_command_line, free_mem,
229 &crash_size, &crash_base);
230 if (ret == 0 && crash_size) {
231 if (crash_base > 0) {
232 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
233 "for crashkernel (System RAM: %ldMB)\n",
234 (unsigned long)(crash_size >> 20),
235 (unsigned long)(crash_base >> 20),
236 (unsigned long)(free_mem >> 20));
237 crashk_res.start = crash_base;
238 crashk_res.end = crash_base + crash_size - 1;
239 reserve_bootmem(crash_base, crash_size);
240 } else
241 printk(KERN_INFO "crashkernel reservation failed - "
242 "you have to specify a base address\n");
243 }
244 }
245 #else
246 static inline void __init reserve_crashkernel(void)
247 {}
248 #endif
249
250 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
251 void __attribute__((weak)) __init memory_setup(void)
252 {
253 machine_specific_memory_setup();
254 }
255
256 void __init setup_arch(char **cmdline_p)
257 {
258 unsigned i;
259
260 printk(KERN_INFO "Command line: %s\n", boot_command_line);
261
262 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
263 screen_info = boot_params.screen_info;
264 edid_info = boot_params.edid_info;
265 saved_video_mode = boot_params.hdr.vid_mode;
266 bootloader_type = boot_params.hdr.type_of_loader;
267
268 #ifdef CONFIG_BLK_DEV_RAM
269 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
270 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
271 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
272 #endif
273 #ifdef CONFIG_EFI
274 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
275 "EL64", 4))
276 efi_enabled = 1;
277 #endif
278
279 ARCH_SETUP
280
281 memory_setup();
282 copy_edd();
283
284 if (!boot_params.hdr.root_flags)
285 root_mountflags &= ~MS_RDONLY;
286 init_mm.start_code = (unsigned long) &_text;
287 init_mm.end_code = (unsigned long) &_etext;
288 init_mm.end_data = (unsigned long) &_edata;
289 init_mm.brk = (unsigned long) &_end;
290
291 code_resource.start = virt_to_phys(&_text);
292 code_resource.end = virt_to_phys(&_etext)-1;
293 data_resource.start = virt_to_phys(&_etext);
294 data_resource.end = virt_to_phys(&_edata)-1;
295 bss_resource.start = virt_to_phys(&__bss_start);
296 bss_resource.end = virt_to_phys(&__bss_stop)-1;
297
298 early_identify_cpu(&boot_cpu_data);
299
300 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
301 *cmdline_p = command_line;
302
303 parse_early_param();
304
305 finish_e820_parsing();
306
307 early_gart_iommu_check();
308
309 e820_register_active_regions(0, 0, -1UL);
310 /*
311 * partially used pages are not usable - thus
312 * we are rounding upwards:
313 */
314 end_pfn = e820_end_of_ram();
315 /* update e820 for memory not covered by WB MTRRs */
316 mtrr_bp_init();
317 if (mtrr_trim_uncached_memory(end_pfn)) {
318 e820_register_active_regions(0, 0, -1UL);
319 end_pfn = e820_end_of_ram();
320 }
321
322 num_physpages = end_pfn;
323
324 check_efer();
325
326 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
327 if (efi_enabled)
328 efi_init();
329
330 dmi_scan_machine();
331
332 io_delay_init();
333
334 #ifdef CONFIG_SMP
335 /* setup to use the early static init tables during kernel startup */
336 x86_cpu_to_apicid_early_ptr = (void *)&x86_cpu_to_apicid_init;
337 x86_bios_cpu_apicid_early_ptr = (void *)&x86_bios_cpu_apicid_init;
338 #ifdef CONFIG_NUMA
339 x86_cpu_to_node_map_early_ptr = (void *)&x86_cpu_to_node_map_init;
340 #endif
341 x86_bios_cpu_apicid_early_ptr = (void *)&x86_bios_cpu_apicid_init;
342 #endif
343
344 #ifdef CONFIG_ACPI
345 /*
346 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
347 * Call this early for SRAT node setup.
348 */
349 acpi_boot_table_init();
350 #endif
351
352 /* How many end-of-memory variables you have, grandma! */
353 max_low_pfn = end_pfn;
354 max_pfn = end_pfn;
355 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
356
357 /* Remove active ranges so rediscovery with NUMA-awareness happens */
358 remove_all_active_ranges();
359
360 #ifdef CONFIG_ACPI_NUMA
361 /*
362 * Parse SRAT to discover nodes.
363 */
364 acpi_numa_init();
365 #endif
366
367 #ifdef CONFIG_NUMA
368 numa_initmem_init(0, end_pfn);
369 #else
370 contig_initmem_init(0, end_pfn);
371 #endif
372
373 early_res_to_bootmem();
374
375 #ifdef CONFIG_ACPI_SLEEP
376 /*
377 * Reserve low memory region for sleep support.
378 */
379 acpi_reserve_bootmem();
380 #endif
381
382 if (efi_enabled) {
383 efi_map_memmap();
384 efi_reserve_bootmem();
385 }
386
387 /*
388 * Find and reserve possible boot-time SMP configuration:
389 */
390 find_smp_config();
391 #ifdef CONFIG_BLK_DEV_INITRD
392 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
393 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
394 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
395 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
396 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
397
398 if (ramdisk_end <= end_of_mem) {
399 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
400 initrd_start = ramdisk_image + PAGE_OFFSET;
401 initrd_end = initrd_start+ramdisk_size;
402 } else {
403 /* Assumes everything on node 0 */
404 free_bootmem(ramdisk_image, ramdisk_size);
405 printk(KERN_ERR "initrd extends beyond end of memory "
406 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
407 ramdisk_end, end_of_mem);
408 initrd_start = 0;
409 }
410 }
411 #endif
412 reserve_crashkernel();
413 paging_init();
414 map_vsyscall();
415
416 early_quirks();
417
418 /*
419 * set this early, so we dont allocate cpu0
420 * if MADT list doesnt list BSP first
421 * mpparse.c/MP_processor_info() allocates logical cpu numbers.
422 */
423 cpu_set(0, cpu_present_map);
424 #ifdef CONFIG_ACPI
425 /*
426 * Read APIC and some other early information from ACPI tables.
427 */
428 acpi_boot_init();
429 #endif
430
431 init_cpu_to_node();
432
433 /*
434 * get boot-time SMP configuration:
435 */
436 if (smp_found_config)
437 get_smp_config();
438 init_apic_mappings();
439 ioapic_init_mappings();
440
441 /*
442 * We trust e820 completely. No explicit ROM probing in memory.
443 */
444 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
445 e820_mark_nosave_regions();
446
447 /* request I/O space for devices used on all i[345]86 PCs */
448 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
449 request_resource(&ioport_resource, &standard_io_resources[i]);
450
451 e820_setup_gap();
452
453 #ifdef CONFIG_VT
454 #if defined(CONFIG_VGA_CONSOLE)
455 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
456 conswitchp = &vga_con;
457 #elif defined(CONFIG_DUMMY_CONSOLE)
458 conswitchp = &dummy_con;
459 #endif
460 #endif
461 }
462
463 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
464 {
465 unsigned int *v;
466
467 if (c->extended_cpuid_level < 0x80000004)
468 return 0;
469
470 v = (unsigned int *) c->x86_model_id;
471 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
472 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
473 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
474 c->x86_model_id[48] = 0;
475 return 1;
476 }
477
478
479 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
480 {
481 unsigned int n, dummy, eax, ebx, ecx, edx;
482
483 n = c->extended_cpuid_level;
484
485 if (n >= 0x80000005) {
486 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
487 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
488 "D cache %dK (%d bytes/line)\n",
489 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
490 c->x86_cache_size = (ecx>>24) + (edx>>24);
491 /* On K8 L1 TLB is inclusive, so don't count it */
492 c->x86_tlbsize = 0;
493 }
494
495 if (n >= 0x80000006) {
496 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
497 ecx = cpuid_ecx(0x80000006);
498 c->x86_cache_size = ecx >> 16;
499 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
500
501 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
502 c->x86_cache_size, ecx & 0xFF);
503 }
504 if (n >= 0x80000008) {
505 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
506 c->x86_virt_bits = (eax >> 8) & 0xff;
507 c->x86_phys_bits = eax & 0xff;
508 }
509 }
510
511 #ifdef CONFIG_NUMA
512 static int nearby_node(int apicid)
513 {
514 int i, node;
515
516 for (i = apicid - 1; i >= 0; i--) {
517 node = apicid_to_node[i];
518 if (node != NUMA_NO_NODE && node_online(node))
519 return node;
520 }
521 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
522 node = apicid_to_node[i];
523 if (node != NUMA_NO_NODE && node_online(node))
524 return node;
525 }
526 return first_node(node_online_map); /* Shouldn't happen */
527 }
528 #endif
529
530 /*
531 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
532 * Assumes number of cores is a power of two.
533 */
534 static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
535 {
536 #ifdef CONFIG_SMP
537 unsigned bits;
538 #ifdef CONFIG_NUMA
539 int cpu = smp_processor_id();
540 int node = 0;
541 unsigned apicid = hard_smp_processor_id();
542 #endif
543 bits = c->x86_coreid_bits;
544
545 /* Low order bits define the core id (index of core in socket) */
546 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
547 /* Convert the APIC ID into the socket ID */
548 c->phys_proc_id = phys_pkg_id(bits);
549
550 #ifdef CONFIG_NUMA
551 node = c->phys_proc_id;
552 if (apicid_to_node[apicid] != NUMA_NO_NODE)
553 node = apicid_to_node[apicid];
554 if (!node_online(node)) {
555 /* Two possibilities here:
556 - The CPU is missing memory and no node was created.
557 In that case try picking one from a nearby CPU
558 - The APIC IDs differ from the HyperTransport node IDs
559 which the K8 northbridge parsing fills in.
560 Assume they are all increased by a constant offset,
561 but in the same order as the HT nodeids.
562 If that doesn't result in a usable node fall back to the
563 path for the previous case. */
564
565 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
566
567 if (ht_nodeid >= 0 &&
568 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
569 node = apicid_to_node[ht_nodeid];
570 /* Pick a nearby node */
571 if (!node_online(node))
572 node = nearby_node(apicid);
573 }
574 numa_set_node(cpu, node);
575
576 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
577 #endif
578 #endif
579 }
580
581 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
582 {
583 #ifdef CONFIG_SMP
584 unsigned bits, ecx;
585
586 /* Multi core CPU? */
587 if (c->extended_cpuid_level < 0x80000008)
588 return;
589
590 ecx = cpuid_ecx(0x80000008);
591
592 c->x86_max_cores = (ecx & 0xff) + 1;
593
594 /* CPU telling us the core id bits shift? */
595 bits = (ecx >> 12) & 0xF;
596
597 /* Otherwise recompute */
598 if (bits == 0) {
599 while ((1 << bits) < c->x86_max_cores)
600 bits++;
601 }
602
603 c->x86_coreid_bits = bits;
604
605 #endif
606 }
607
608 #define ENABLE_C1E_MASK 0x18000000
609 #define CPUID_PROCESSOR_SIGNATURE 1
610 #define CPUID_XFAM 0x0ff00000
611 #define CPUID_XFAM_K8 0x00000000
612 #define CPUID_XFAM_10H 0x00100000
613 #define CPUID_XFAM_11H 0x00200000
614 #define CPUID_XMOD 0x000f0000
615 #define CPUID_XMOD_REV_F 0x00040000
616
617 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
618 static __cpuinit int amd_apic_timer_broken(void)
619 {
620 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
621
622 switch (eax & CPUID_XFAM) {
623 case CPUID_XFAM_K8:
624 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
625 break;
626 case CPUID_XFAM_10H:
627 case CPUID_XFAM_11H:
628 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
629 if (lo & ENABLE_C1E_MASK)
630 return 1;
631 break;
632 default:
633 /* err on the side of caution */
634 return 1;
635 }
636 return 0;
637 }
638
639 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
640 {
641 early_init_amd_mc(c);
642
643 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
644 if (c->x86_power & (1<<8))
645 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
646 }
647
648 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
649 {
650 unsigned level;
651
652 #ifdef CONFIG_SMP
653 unsigned long value;
654
655 /*
656 * Disable TLB flush filter by setting HWCR.FFDIS on K8
657 * bit 6 of msr C001_0015
658 *
659 * Errata 63 for SH-B3 steppings
660 * Errata 122 for all steppings (F+ have it disabled by default)
661 */
662 if (c->x86 == 15) {
663 rdmsrl(MSR_K8_HWCR, value);
664 value |= 1 << 6;
665 wrmsrl(MSR_K8_HWCR, value);
666 }
667 #endif
668
669 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
670 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
671 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
672
673 /* On C+ stepping K8 rep microcode works well for copy/memset */
674 level = cpuid_eax(1);
675 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
676 level >= 0x0f58))
677 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
678 if (c->x86 == 0x10 || c->x86 == 0x11)
679 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
680
681 /* Enable workaround for FXSAVE leak */
682 if (c->x86 >= 6)
683 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
684
685 level = get_model_name(c);
686 if (!level) {
687 switch (c->x86) {
688 case 15:
689 /* Should distinguish Models here, but this is only
690 a fallback anyways. */
691 strcpy(c->x86_model_id, "Hammer");
692 break;
693 }
694 }
695 display_cacheinfo(c);
696
697 /* Multi core CPU? */
698 if (c->extended_cpuid_level >= 0x80000008)
699 amd_detect_cmp(c);
700
701 if (c->extended_cpuid_level >= 0x80000006 &&
702 (cpuid_edx(0x80000006) & 0xf000))
703 num_cache_leaves = 4;
704 else
705 num_cache_leaves = 3;
706
707 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
708 set_cpu_cap(c, X86_FEATURE_K8);
709
710 /* MFENCE stops RDTSC speculation */
711 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
712
713 if (amd_apic_timer_broken())
714 disable_apic_timer = 1;
715 }
716
717 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
718 {
719 #ifdef CONFIG_SMP
720 u32 eax, ebx, ecx, edx;
721 int index_msb, core_bits;
722
723 cpuid(1, &eax, &ebx, &ecx, &edx);
724
725
726 if (!cpu_has(c, X86_FEATURE_HT))
727 return;
728 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
729 goto out;
730
731 smp_num_siblings = (ebx & 0xff0000) >> 16;
732
733 if (smp_num_siblings == 1) {
734 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
735 } else if (smp_num_siblings > 1) {
736
737 if (smp_num_siblings > NR_CPUS) {
738 printk(KERN_WARNING "CPU: Unsupported number of "
739 "siblings %d", smp_num_siblings);
740 smp_num_siblings = 1;
741 return;
742 }
743
744 index_msb = get_count_order(smp_num_siblings);
745 c->phys_proc_id = phys_pkg_id(index_msb);
746
747 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
748
749 index_msb = get_count_order(smp_num_siblings);
750
751 core_bits = get_count_order(c->x86_max_cores);
752
753 c->cpu_core_id = phys_pkg_id(index_msb) &
754 ((1 << core_bits) - 1);
755 }
756 out:
757 if ((c->x86_max_cores * smp_num_siblings) > 1) {
758 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
759 c->phys_proc_id);
760 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
761 c->cpu_core_id);
762 }
763
764 #endif
765 }
766
767 /*
768 * find out the number of processor cores on the die
769 */
770 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
771 {
772 unsigned int eax, t;
773
774 if (c->cpuid_level < 4)
775 return 1;
776
777 cpuid_count(4, 0, &eax, &t, &t, &t);
778
779 if (eax & 0x1f)
780 return ((eax >> 26) + 1);
781 else
782 return 1;
783 }
784
785 static void srat_detect_node(void)
786 {
787 #ifdef CONFIG_NUMA
788 unsigned node;
789 int cpu = smp_processor_id();
790 int apicid = hard_smp_processor_id();
791
792 /* Don't do the funky fallback heuristics the AMD version employs
793 for now. */
794 node = apicid_to_node[apicid];
795 if (node == NUMA_NO_NODE)
796 node = first_node(node_online_map);
797 numa_set_node(cpu, node);
798
799 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
800 #endif
801 }
802
803 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
804 {
805 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
806 (c->x86 == 0x6 && c->x86_model >= 0x0e))
807 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
808 }
809
810 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
811 {
812 /* Cache sizes */
813 unsigned n;
814
815 init_intel_cacheinfo(c);
816 if (c->cpuid_level > 9) {
817 unsigned eax = cpuid_eax(10);
818 /* Check for version and the number of counters */
819 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
820 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
821 }
822
823 if (cpu_has_ds) {
824 unsigned int l1, l2;
825 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
826 if (!(l1 & (1<<11)))
827 set_cpu_cap(c, X86_FEATURE_BTS);
828 if (!(l1 & (1<<12)))
829 set_cpu_cap(c, X86_FEATURE_PEBS);
830 }
831
832
833 if (cpu_has_bts)
834 ds_init_intel(c);
835
836 n = c->extended_cpuid_level;
837 if (n >= 0x80000008) {
838 unsigned eax = cpuid_eax(0x80000008);
839 c->x86_virt_bits = (eax >> 8) & 0xff;
840 c->x86_phys_bits = eax & 0xff;
841 /* CPUID workaround for Intel 0F34 CPU */
842 if (c->x86_vendor == X86_VENDOR_INTEL &&
843 c->x86 == 0xF && c->x86_model == 0x3 &&
844 c->x86_mask == 0x4)
845 c->x86_phys_bits = 36;
846 }
847
848 if (c->x86 == 15)
849 c->x86_cache_alignment = c->x86_clflush_size * 2;
850 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
851 (c->x86 == 0x6 && c->x86_model >= 0x0e))
852 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
853 if (c->x86 == 6)
854 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
855 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
856 c->x86_max_cores = intel_num_cpu_cores(c);
857
858 srat_detect_node();
859 }
860
861 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
862 {
863 char *v = c->x86_vendor_id;
864
865 if (!strcmp(v, "AuthenticAMD"))
866 c->x86_vendor = X86_VENDOR_AMD;
867 else if (!strcmp(v, "GenuineIntel"))
868 c->x86_vendor = X86_VENDOR_INTEL;
869 else
870 c->x86_vendor = X86_VENDOR_UNKNOWN;
871 }
872
873 struct cpu_model_info {
874 int vendor;
875 int family;
876 char *model_names[16];
877 };
878
879 /* Do some early cpuid on the boot CPU to get some parameter that are
880 needed before check_bugs. Everything advanced is in identify_cpu
881 below. */
882 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
883 {
884 u32 tfms, xlvl;
885
886 c->loops_per_jiffy = loops_per_jiffy;
887 c->x86_cache_size = -1;
888 c->x86_vendor = X86_VENDOR_UNKNOWN;
889 c->x86_model = c->x86_mask = 0; /* So far unknown... */
890 c->x86_vendor_id[0] = '\0'; /* Unset */
891 c->x86_model_id[0] = '\0'; /* Unset */
892 c->x86_clflush_size = 64;
893 c->x86_cache_alignment = c->x86_clflush_size;
894 c->x86_max_cores = 1;
895 c->x86_coreid_bits = 0;
896 c->extended_cpuid_level = 0;
897 memset(&c->x86_capability, 0, sizeof c->x86_capability);
898
899 /* Get vendor name */
900 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
901 (unsigned int *)&c->x86_vendor_id[0],
902 (unsigned int *)&c->x86_vendor_id[8],
903 (unsigned int *)&c->x86_vendor_id[4]);
904
905 get_cpu_vendor(c);
906
907 /* Initialize the standard set of capabilities */
908 /* Note that the vendor-specific code below might override */
909
910 /* Intel-defined flags: level 0x00000001 */
911 if (c->cpuid_level >= 0x00000001) {
912 __u32 misc;
913 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
914 &c->x86_capability[0]);
915 c->x86 = (tfms >> 8) & 0xf;
916 c->x86_model = (tfms >> 4) & 0xf;
917 c->x86_mask = tfms & 0xf;
918 if (c->x86 == 0xf)
919 c->x86 += (tfms >> 20) & 0xff;
920 if (c->x86 >= 0x6)
921 c->x86_model += ((tfms >> 16) & 0xF) << 4;
922 if (c->x86_capability[0] & (1<<19))
923 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
924 } else {
925 /* Have CPUID level 0 only - unheard of */
926 c->x86 = 4;
927 }
928
929 #ifdef CONFIG_SMP
930 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
931 #endif
932 /* AMD-defined flags: level 0x80000001 */
933 xlvl = cpuid_eax(0x80000000);
934 c->extended_cpuid_level = xlvl;
935 if ((xlvl & 0xffff0000) == 0x80000000) {
936 if (xlvl >= 0x80000001) {
937 c->x86_capability[1] = cpuid_edx(0x80000001);
938 c->x86_capability[6] = cpuid_ecx(0x80000001);
939 }
940 if (xlvl >= 0x80000004)
941 get_model_name(c); /* Default name */
942 }
943
944 /* Transmeta-defined flags: level 0x80860001 */
945 xlvl = cpuid_eax(0x80860000);
946 if ((xlvl & 0xffff0000) == 0x80860000) {
947 /* Don't set x86_cpuid_level here for now to not confuse. */
948 if (xlvl >= 0x80860001)
949 c->x86_capability[2] = cpuid_edx(0x80860001);
950 }
951
952 c->extended_cpuid_level = cpuid_eax(0x80000000);
953 if (c->extended_cpuid_level >= 0x80000007)
954 c->x86_power = cpuid_edx(0x80000007);
955
956 switch (c->x86_vendor) {
957 case X86_VENDOR_AMD:
958 early_init_amd(c);
959 break;
960 case X86_VENDOR_INTEL:
961 early_init_intel(c);
962 break;
963 }
964
965 }
966
967 /*
968 * This does the hard work of actually picking apart the CPU stuff...
969 */
970 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
971 {
972 int i;
973
974 early_identify_cpu(c);
975
976 init_scattered_cpuid_features(c);
977
978 c->apicid = phys_pkg_id(0);
979
980 /*
981 * Vendor-specific initialization. In this section we
982 * canonicalize the feature flags, meaning if there are
983 * features a certain CPU supports which CPUID doesn't
984 * tell us, CPUID claiming incorrect flags, or other bugs,
985 * we handle them here.
986 *
987 * At the end of this section, c->x86_capability better
988 * indicate the features this CPU genuinely supports!
989 */
990 switch (c->x86_vendor) {
991 case X86_VENDOR_AMD:
992 init_amd(c);
993 break;
994
995 case X86_VENDOR_INTEL:
996 init_intel(c);
997 break;
998
999 case X86_VENDOR_UNKNOWN:
1000 default:
1001 display_cacheinfo(c);
1002 break;
1003 }
1004
1005 detect_ht(c);
1006
1007 /*
1008 * On SMP, boot_cpu_data holds the common feature set between
1009 * all CPUs; so make sure that we indicate which features are
1010 * common between the CPUs. The first time this routine gets
1011 * executed, c == &boot_cpu_data.
1012 */
1013 if (c != &boot_cpu_data) {
1014 /* AND the already accumulated flags with these */
1015 for (i = 0; i < NCAPINTS; i++)
1016 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1017 }
1018
1019 /* Clear all flags overriden by options */
1020 for (i = 0; i < NCAPINTS; i++)
1021 c->x86_capability[i] ^= cleared_cpu_caps[i];
1022
1023 #ifdef CONFIG_X86_MCE
1024 mcheck_init(c);
1025 #endif
1026 select_idle_routine(c);
1027
1028 if (c != &boot_cpu_data)
1029 mtrr_ap_init();
1030 #ifdef CONFIG_NUMA
1031 numa_add_cpu(smp_processor_id());
1032 #endif
1033
1034 }
1035
1036 static __init int setup_noclflush(char *arg)
1037 {
1038 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1039 return 1;
1040 }
1041 __setup("noclflush", setup_noclflush);
1042
1043 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1044 {
1045 if (c->x86_model_id[0])
1046 printk(KERN_INFO "%s", c->x86_model_id);
1047
1048 if (c->x86_mask || c->cpuid_level >= 0)
1049 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1050 else
1051 printk(KERN_CONT "\n");
1052 }
1053
1054 static __init int setup_disablecpuid(char *arg)
1055 {
1056 int bit;
1057 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1058 setup_clear_cpu_cap(bit);
1059 else
1060 return 0;
1061 return 1;
1062 }
1063 __setup("clearcpuid=", setup_disablecpuid);
1064
1065 /*
1066 * Get CPU information for use by the procfs.
1067 */
1068
1069 static int show_cpuinfo(struct seq_file *m, void *v)
1070 {
1071 struct cpuinfo_x86 *c = v;
1072 int cpu = 0, i;
1073
1074 /*
1075 * These flag bits must match the definitions in <asm/cpufeature.h>.
1076 * NULL means this bit is undefined or reserved; either way it doesn't
1077 * have meaning as far as Linux is concerned. Note that it's important
1078 * to realize there is a difference between this table and CPUID -- if
1079 * applications want to get the raw CPUID data, they should access
1080 * /dev/cpu/<cpu_nr>/cpuid instead.
1081 */
1082 static const char *const x86_cap_flags[] = {
1083 /* Intel-defined */
1084 "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
1085 "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
1086 "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
1087 "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", "pbe",
1088
1089 /* AMD-defined */
1090 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1091 NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
1092 NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
1093 NULL, "fxsr_opt", "pdpe1gb", "rdtscp", NULL, "lm",
1094 "3dnowext", "3dnow",
1095
1096 /* Transmeta-defined */
1097 "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
1098 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1099 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1100 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1101
1102 /* Other (Linux-defined) */
1103 "cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr",
1104 NULL, NULL, NULL, NULL,
1105 "constant_tsc", "up", NULL, "arch_perfmon",
1106 "pebs", "bts", NULL, "sync_rdtsc",
1107 "rep_good", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1108 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1109
1110 /* Intel-defined (#2) */
1111 "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
1112 "tm2", "ssse3", "cid", NULL, NULL, "cx16", "xtpr", NULL,
1113 NULL, NULL, "dca", "sse4_1", "sse4_2", NULL, NULL, "popcnt",
1114 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1115
1116 /* VIA/Cyrix/Centaur-defined */
1117 NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
1118 "ace2", "ace2_en", "phe", "phe_en", "pmm", "pmm_en", NULL, NULL,
1119 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1121
1122 /* AMD-defined (#2) */
1123 "lahf_lm", "cmp_legacy", "svm", "extapic",
1124 "cr8_legacy", "abm", "sse4a", "misalignsse",
1125 "3dnowprefetch", "osvw", "ibs", "sse5",
1126 "skinit", "wdt", NULL, NULL,
1127 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1128 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1129
1130 /* Auxiliary (Linux-defined) */
1131 "ida", NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
1135 };
1136 static const char *const x86_power_flags[] = {
1137 "ts", /* temperature sensor */
1138 "fid", /* frequency id control */
1139 "vid", /* voltage id control */
1140 "ttp", /* thermal trip */
1141 "tm",
1142 "stc",
1143 "100mhzsteps",
1144 "hwpstate",
1145 "", /* tsc invariant mapped to constant_tsc */
1146 /* nothing */
1147 };
1148
1149
1150 #ifdef CONFIG_SMP
1151 cpu = c->cpu_index;
1152 #endif
1153
1154 seq_printf(m, "processor\t: %u\n"
1155 "vendor_id\t: %s\n"
1156 "cpu family\t: %d\n"
1157 "model\t\t: %d\n"
1158 "model name\t: %s\n",
1159 (unsigned)cpu,
1160 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1161 c->x86,
1162 (int)c->x86_model,
1163 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1164
1165 if (c->x86_mask || c->cpuid_level >= 0)
1166 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1167 else
1168 seq_printf(m, "stepping\t: unknown\n");
1169
1170 if (cpu_has(c, X86_FEATURE_TSC)) {
1171 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1172
1173 if (!freq)
1174 freq = cpu_khz;
1175 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1176 freq / 1000, (freq % 1000));
1177 }
1178
1179 /* Cache size */
1180 if (c->x86_cache_size >= 0)
1181 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1182
1183 #ifdef CONFIG_SMP
1184 if (smp_num_siblings * c->x86_max_cores > 1) {
1185 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1186 seq_printf(m, "siblings\t: %d\n",
1187 cpus_weight(per_cpu(cpu_core_map, cpu)));
1188 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1189 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1190 }
1191 #endif
1192
1193 seq_printf(m,
1194 "fpu\t\t: yes\n"
1195 "fpu_exception\t: yes\n"
1196 "cpuid level\t: %d\n"
1197 "wp\t\t: yes\n"
1198 "flags\t\t:",
1199 c->cpuid_level);
1200
1201 for (i = 0; i < 32*NCAPINTS; i++)
1202 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1203 seq_printf(m, " %s", x86_cap_flags[i]);
1204
1205 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1206 c->loops_per_jiffy/(500000/HZ),
1207 (c->loops_per_jiffy/(5000/HZ)) % 100);
1208
1209 if (c->x86_tlbsize > 0)
1210 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1211 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1212 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1213
1214 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1215 c->x86_phys_bits, c->x86_virt_bits);
1216
1217 seq_printf(m, "power management:");
1218 for (i = 0; i < 32; i++) {
1219 if (c->x86_power & (1 << i)) {
1220 if (i < ARRAY_SIZE(x86_power_flags) &&
1221 x86_power_flags[i])
1222 seq_printf(m, "%s%s",
1223 x86_power_flags[i][0]?" ":"",
1224 x86_power_flags[i]);
1225 else
1226 seq_printf(m, " [%d]", i);
1227 }
1228 }
1229
1230 seq_printf(m, "\n\n");
1231
1232 return 0;
1233 }
1234
1235 static void *c_start(struct seq_file *m, loff_t *pos)
1236 {
1237 if (*pos == 0) /* just in case, cpu 0 is not the first */
1238 *pos = first_cpu(cpu_online_map);
1239 if ((*pos) < NR_CPUS && cpu_online(*pos))
1240 return &cpu_data(*pos);
1241 return NULL;
1242 }
1243
1244 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1245 {
1246 *pos = next_cpu(*pos, cpu_online_map);
1247 return c_start(m, pos);
1248 }
1249
1250 static void c_stop(struct seq_file *m, void *v)
1251 {
1252 }
1253
1254 const struct seq_operations cpuinfo_op = {
1255 .start = c_start,
1256 .next = c_next,
1257 .stop = c_stop,
1258 .show = show_cpuinfo,
1259 };
linux 2.6 git repository for openrd