2 * Copyright 2005 Stephane Marchesin.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 #ifndef __NOUVEAU_DRM_H__
26 #define __NOUVEAU_DRM_H__
28 #define NOUVEAU_DRM_HEADER_PATCHLEVEL 15
30 struct drm_nouveau_channel_alloc
{
31 uint32_t fb_ctxdma_handle
;
32 uint32_t tt_ctxdma_handle
;
37 uint32_t notifier_handle
;
39 /* DRM-enforced subchannel assignments */
47 struct drm_nouveau_channel_free
{
51 struct drm_nouveau_grobj_alloc
{
57 struct drm_nouveau_notifierobj_alloc
{
64 struct drm_nouveau_gpuobj_free
{
69 /* FIXME : maybe unify {GET,SET}PARAMs */
70 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
71 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
72 #define NOUVEAU_GETPARAM_BUS_TYPE 5
73 #define NOUVEAU_GETPARAM_FB_PHYSICAL 6
74 #define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
75 #define NOUVEAU_GETPARAM_FB_SIZE 8
76 #define NOUVEAU_GETPARAM_AGP_SIZE 9
77 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
78 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
79 #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
80 #define NOUVEAU_GETPARAM_GRAPH_UNITS 13
81 struct drm_nouveau_getparam
{
86 struct drm_nouveau_setparam
{
91 #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
92 #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
93 #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
94 #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
96 struct drm_nouveau_gem_info
{
106 struct drm_nouveau_gem_new
{
107 struct drm_nouveau_gem_info info
;
108 uint32_t channel_hint
;
112 struct drm_nouveau_gem_pushbuf_bo
{
115 uint32_t read_domains
;
116 uint32_t write_domains
;
117 uint32_t valid_domains
;
118 uint32_t presumed_ok
;
119 uint32_t presumed_domain
;
120 uint64_t presumed_offset
;
123 #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
124 #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
125 #define NOUVEAU_GEM_RELOC_OR (1 << 2)
126 struct drm_nouveau_gem_pushbuf_reloc
{
128 uint32_t reloc_index
;
135 #define NOUVEAU_GEM_MAX_BUFFERS 1024
136 #define NOUVEAU_GEM_MAX_RELOCS 1024
138 struct drm_nouveau_gem_pushbuf
{
148 struct drm_nouveau_gem_pushbuf_call
{
159 /* below only accessed for CALL2 */
160 uint64_t vram_available
;
161 uint64_t gart_available
;
164 struct drm_nouveau_gem_pin
{
170 struct drm_nouveau_gem_unpin
{
174 #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
175 #define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
176 #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
177 struct drm_nouveau_gem_cpu_prep
{
182 struct drm_nouveau_gem_cpu_fini
{
186 struct drm_nouveau_gem_tile
{
194 enum nouveau_bus_type
{
200 struct drm_nouveau_sarea
{
203 #define DRM_NOUVEAU_CARD_INIT 0x00
204 #define DRM_NOUVEAU_GETPARAM 0x01
205 #define DRM_NOUVEAU_SETPARAM 0x02
206 #define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
207 #define DRM_NOUVEAU_CHANNEL_FREE 0x04
208 #define DRM_NOUVEAU_GROBJ_ALLOC 0x05
209 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
210 #define DRM_NOUVEAU_GPUOBJ_FREE 0x07
211 #define DRM_NOUVEAU_GEM_NEW 0x40
212 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
213 #define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42
214 #define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */
215 #define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */
216 #define DRM_NOUVEAU_GEM_CPU_PREP 0x45
217 #define DRM_NOUVEAU_GEM_CPU_FINI 0x46
218 #define DRM_NOUVEAU_GEM_INFO 0x47
219 #define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48
221 #endif /* __NOUVEAU_DRM_H__ */