include/drm/i915_drm.h

   1 /*
   2  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial portions
  15  * of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #ifndef _I915_DRM_H_
  28 #define _I915_DRM_H_
  29
  30 #include "drm.h"
  31
  32 /* Please note that modifications to all structs defined here are
  33  * subject to backwards-compatibility constraints.
  34  */
  35
  36 /* Each region is a minimum of 16k, and there are at most 255 of them.
  37  */
  38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  39                                  * of chars for next/prev indices */
  40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
  41
  42 typedef struct _drm_i915_init {
  43         enum {
  44                 I915_INIT_DMA = 0x01,
  45                 I915_CLEANUP_DMA = 0x02,
  46                 I915_RESUME_DMA = 0x03
  47         } func;
  48         unsigned int mmio_offset;
  49         int sarea_priv_offset;
  50         unsigned int ring_start;
  51         unsigned int ring_end;
  52         unsigned int ring_size;
  53         unsigned int front_offset;
  54         unsigned int back_offset;
  55         unsigned int depth_offset;
  56         unsigned int w;
  57         unsigned int h;
  58         unsigned int pitch;
  59         unsigned int pitch_bits;
  60         unsigned int back_pitch;
  61         unsigned int depth_pitch;
  62         unsigned int cpp;
  63         unsigned int chipset;
  64 } drm_i915_init_t;
  65
  66 typedef struct _drm_i915_sarea {
  67         struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  68         int last_upload;        /* last time texture was uploaded */
  69         int last_enqueue;       /* last time a buffer was enqueued */
  70         int last_dispatch;      /* age of the most recently dispatched buffer */
  71         int ctxOwner;           /* last context to upload state */
  72         int texAge;
  73         int pf_enabled;         /* is pageflipping allowed? */
  74         int pf_active;
  75         int pf_current_page;    /* which buffer is being displayed? */
  76         int perf_boxes;         /* performance boxes to be displayed */
  77         int width, height;      /* screen size in pixels */
  78
  79         drm_handle_t front_handle;
  80         int front_offset;
  81         int front_size;
  82
  83         drm_handle_t back_handle;
  84         int back_offset;
  85         int back_size;
  86
  87         drm_handle_t depth_handle;
  88         int depth_offset;
  89         int depth_size;
  90
  91         drm_handle_t tex_handle;
  92         int tex_offset;
  93         int tex_size;
  94         int log_tex_granularity;
  95         int pitch;
  96         int rotation;           /* 0, 90, 180 or 270 */
  97         int rotated_offset;
  98         int rotated_size;
  99         int rotated_pitch;
 100         int virtualX, virtualY;
 101
 102         unsigned int front_tiled;
 103         unsigned int back_tiled;
 104         unsigned int depth_tiled;
 105         unsigned int rotated_tiled;
 106         unsigned int rotated2_tiled;
 107
 108         int pipeA_x;
 109         int pipeA_y;
 110         int pipeA_w;
 111         int pipeA_h;
 112         int pipeB_x;
 113         int pipeB_y;
 114         int pipeB_w;
 115         int pipeB_h;
 116
 117         /* fill out some space for old userspace triple buffer */
 118         drm_handle_t unused_handle;
 119         __u32 unused1, unused2, unused3;
 120
 121         /* buffer object handles for static buffers. May change
 122          * over the lifetime of the client.
 123          */
 124         __u32 front_bo_handle;
 125         __u32 back_bo_handle;
 126         __u32 unused_bo_handle;
 127         __u32 depth_bo_handle;
 128
 129 } drm_i915_sarea_t;
 130
 131 /* due to userspace building against these headers we need some compat here */
 132 #define planeA_x pipeA_x
 133 #define planeA_y pipeA_y
 134 #define planeA_w pipeA_w
 135 #define planeA_h pipeA_h
 136 #define planeB_x pipeB_x
 137 #define planeB_y pipeB_y
 138 #define planeB_w pipeB_w
 139 #define planeB_h pipeB_h
 140
 141 /* Flags for perf_boxes
 142  */
 143 #define I915_BOX_RING_EMPTY    0x1
 144 #define I915_BOX_FLIP          0x2
 145 #define I915_BOX_WAIT          0x4
 146 #define I915_BOX_TEXTURE_LOAD  0x8
 147 #define I915_BOX_LOST_CONTEXT  0x10
 148
 149 /* I915 specific ioctls
 150  * The device specific ioctl range is 0x40 to 0x79.
 151  */
 152 #define DRM_I915_INIT           0x00
 153 #define DRM_I915_FLUSH          0x01
 154 #define DRM_I915_FLIP           0x02
 155 #define DRM_I915_BATCHBUFFER    0x03
 156 #define DRM_I915_IRQ_EMIT       0x04
 157 #define DRM_I915_IRQ_WAIT       0x05
 158 #define DRM_I915_GETPARAM       0x06
 159 #define DRM_I915_SETPARAM       0x07
 160 #define DRM_I915_ALLOC          0x08
 161 #define DRM_I915_FREE           0x09
 162 #define DRM_I915_INIT_HEAP      0x0a
 163 #define DRM_I915_CMDBUFFER      0x0b
 164 #define DRM_I915_DESTROY_HEAP   0x0c
 165 #define DRM_I915_SET_VBLANK_PIPE        0x0d
 166 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 167 #define DRM_I915_VBLANK_SWAP    0x0f
 168 #define DRM_I915_HWS_ADDR       0x11
 169 #define DRM_I915_GEM_INIT       0x13
 170 #define DRM_I915_GEM_EXECBUFFER 0x14
 171 #define DRM_I915_GEM_PIN        0x15
 172 #define DRM_I915_GEM_UNPIN      0x16
 173 #define DRM_I915_GEM_BUSY       0x17
 174 #define DRM_I915_GEM_THROTTLE   0x18
 175 #define DRM_I915_GEM_ENTERVT    0x19
 176 #define DRM_I915_GEM_LEAVEVT    0x1a
 177 #define DRM_I915_GEM_CREATE     0x1b
 178 #define DRM_I915_GEM_PREAD      0x1c
 179 #define DRM_I915_GEM_PWRITE     0x1d
 180 #define DRM_I915_GEM_MMAP       0x1e
 181 #define DRM_I915_GEM_SET_DOMAIN 0x1f
 182 #define DRM_I915_GEM_SW_FINISH  0x20
 183 #define DRM_I915_GEM_SET_TILING 0x21
 184 #define DRM_I915_GEM_GET_TILING 0x22
 185 #define DRM_I915_GEM_GET_APERTURE 0x23
 186 #define DRM_I915_GEM_MMAP_GTT   0x24
 187 #define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
 188 #define DRM_I915_GEM_MADVISE    0x26
 189 #define DRM_I915_OVERLAY_PUT_IMAGE      0x27
 190 #define DRM_I915_OVERLAY_ATTRS  0x28
 191 #define DRM_I915_GEM_EXECBUFFER2        0x29
 192
 193 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 194 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
 195 #define DRM_IOCTL_I915_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
 196 #define DRM_IOCTL_I915_BATCHBUFFER      DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
 197 #define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
 198 #define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
 199 #define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
 200 #define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
 201 #define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
 202 #define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
 203 #define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
 204 #define DRM_IOCTL_I915_CMDBUFFER        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
 205 #define DRM_IOCTL_I915_DESTROY_HEAP     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
 206 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 207 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 208 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 209 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 210 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
 211 #define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
 212 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 213 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 214 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
 215 #define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
 216 #define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
 217 #define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
 218 #define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
 219 #define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
 220 #define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
 221 #define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
 222 #define DRM_IOCTL_I915_GEM_MMAP_GTT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
 223 #define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
 224 #define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
 225 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 226 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 227 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
 228 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 229 #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
 230 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
 231 #define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 232
 233 /* Allow drivers to submit batchbuffers directly to hardware, relying
 234  * on the security mechanisms provided by hardware.
 235  */
 236 typedef struct drm_i915_batchbuffer {
 237         int start;              /* agp offset */
 238         int used;               /* nr bytes in use */
 239         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 240         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 241         int num_cliprects;      /* mulitpass with multiple cliprects? */
 242         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 243 } drm_i915_batchbuffer_t;
 244
 245 /* As above, but pass a pointer to userspace buffer which can be
 246  * validated by the kernel prior to sending to hardware.
 247  */
 248 typedef struct _drm_i915_cmdbuffer {
 249         char __user *buf;       /* pointer to userspace command buffer */
 250         int sz;                 /* nr bytes in buf */
 251         int DR1;                /* hw flags for GFX_OP_DRAWRECT_INFO */
 252         int DR4;                /* window origin for GFX_OP_DRAWRECT_INFO */
 253         int num_cliprects;      /* mulitpass with multiple cliprects? */
 254         struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
 255 } drm_i915_cmdbuffer_t;
 256
 257 /* Userspace can request & wait on irq's:
 258  */
 259 typedef struct drm_i915_irq_emit {
 260         int __user *irq_seq;
 261 } drm_i915_irq_emit_t;
 262
 263 typedef struct drm_i915_irq_wait {
 264         int irq_seq;
 265 } drm_i915_irq_wait_t;
 266
 267 /* Ioctl to query kernel params:
 268  */
 269 #define I915_PARAM_IRQ_ACTIVE            1
 270 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 271 #define I915_PARAM_LAST_DISPATCH         3
 272 #define I915_PARAM_CHIPSET_ID            4
 273 #define I915_PARAM_HAS_GEM               5
 274 #define I915_PARAM_NUM_FENCES_AVAIL      6
 275 #define I915_PARAM_HAS_OVERLAY           7
 276 #define I915_PARAM_HAS_PAGEFLIPPING      8
 277 #define I915_PARAM_HAS_EXECBUF2          9
 278
 279 typedef struct drm_i915_getparam {
 280         int param;
 281         int __user *value;
 282 } drm_i915_getparam_t;
 283
 284 /* Ioctl to set kernel params:
 285  */
 286 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
 287 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
 288 #define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
 289 #define I915_SETPARAM_NUM_USED_FENCES                     4
 290
 291 typedef struct drm_i915_setparam {
 292         int param;
 293         int value;
 294 } drm_i915_setparam_t;
 295
 296 /* A memory manager for regions of shared memory:
 297  */
 298 #define I915_MEM_REGION_AGP 1
 299
 300 typedef struct drm_i915_mem_alloc {
 301         int region;
 302         int alignment;
 303         int size;
 304         int __user *region_offset;      /* offset from start of fb or agp */
 305 } drm_i915_mem_alloc_t;
 306
 307 typedef struct drm_i915_mem_free {
 308         int region;
 309         int region_offset;
 310 } drm_i915_mem_free_t;
 311
 312 typedef struct drm_i915_mem_init_heap {
 313         int region;
 314         int size;
 315         int start;
 316 } drm_i915_mem_init_heap_t;
 317
 318 /* Allow memory manager to be torn down and re-initialized (eg on
 319  * rotate):
 320  */
 321 typedef struct drm_i915_mem_destroy_heap {
 322         int region;
 323 } drm_i915_mem_destroy_heap_t;
 324
 325 /* Allow X server to configure which pipes to monitor for vblank signals
 326  */
 327 #define DRM_I915_VBLANK_PIPE_A  1
 328 #define DRM_I915_VBLANK_PIPE_B  2
 329
 330 typedef struct drm_i915_vblank_pipe {
 331         int pipe;
 332 } drm_i915_vblank_pipe_t;
 333
 334 /* Schedule buffer swap at given vertical blank:
 335  */
 336 typedef struct drm_i915_vblank_swap {
 337         drm_drawable_t drawable;
 338         enum drm_vblank_seq_type seqtype;
 339         unsigned int sequence;
 340 } drm_i915_vblank_swap_t;
 341
 342 typedef struct drm_i915_hws_addr {
 343         __u64 addr;
 344 } drm_i915_hws_addr_t;
 345
 346 struct drm_i915_gem_init {
 347         /**
 348          * Beginning offset in the GTT to be managed by the DRM memory
 349          * manager.
 350          */
 351         __u64 gtt_start;
 352         /**
 353          * Ending offset in the GTT to be managed by the DRM memory
 354          * manager.
 355          */
 356         __u64 gtt_end;
 357 };
 358
 359 struct drm_i915_gem_create {
 360         /**
 361          * Requested size for the object.
 362          *
 363          * The (page-aligned) allocated size for the object will be returned.
 364          */
 365         __u64 size;
 366         /**
 367          * Returned handle for the object.
 368          *
 369          * Object handles are nonzero.
 370          */
 371         __u32 handle;
 372         __u32 pad;
 373 };
 374
 375 struct drm_i915_gem_pread {
 376         /** Handle for the object being read. */
 377         __u32 handle;
 378         __u32 pad;
 379         /** Offset into the object to read from */
 380         __u64 offset;
 381         /** Length of data to read */
 382         __u64 size;
 383         /**
 384          * Pointer to write the data into.
 385          *
 386          * This is a fixed-size type for 32/64 compatibility.
 387          */
 388         __u64 data_ptr;
 389 };
 390
 391 struct drm_i915_gem_pwrite {
 392         /** Handle for the object being written to. */
 393         __u32 handle;
 394         __u32 pad;
 395         /** Offset into the object to write to */
 396         __u64 offset;
 397         /** Length of data to write */
 398         __u64 size;
 399         /**
 400          * Pointer to read the data from.
 401          *
 402          * This is a fixed-size type for 32/64 compatibility.
 403          */
 404         __u64 data_ptr;
 405 };
 406
 407 struct drm_i915_gem_mmap {
 408         /** Handle for the object being mapped. */
 409         __u32 handle;
 410         __u32 pad;
 411         /** Offset in the object to map. */
 412         __u64 offset;
 413         /**
 414          * Length of data to map.
 415          *
 416          * The value will be page-aligned.
 417          */
 418         __u64 size;
 419         /**
 420          * Returned pointer the data was mapped at.
 421          *
 422          * This is a fixed-size type for 32/64 compatibility.
 423          */
 424         __u64 addr_ptr;
 425 };
 426
 427 struct drm_i915_gem_mmap_gtt {
 428         /** Handle for the object being mapped. */
 429         __u32 handle;
 430         __u32 pad;
 431         /**
 432          * Fake offset to use for subsequent mmap call
 433          *
 434          * This is a fixed-size type for 32/64 compatibility.
 435          */
 436         __u64 offset;
 437 };
 438
 439 struct drm_i915_gem_set_domain {
 440         /** Handle for the object */
 441         __u32 handle;
 442
 443         /** New read domains */
 444         __u32 read_domains;
 445
 446         /** New write domain */
 447         __u32 write_domain;
 448 };
 449
 450 struct drm_i915_gem_sw_finish {
 451         /** Handle for the object */
 452         __u32 handle;
 453 };
 454
 455 struct drm_i915_gem_relocation_entry {
 456         /**
 457          * Handle of the buffer being pointed to by this relocation entry.
 458          *
 459          * It's appealing to make this be an index into the mm_validate_entry
 460          * list to refer to the buffer, but this allows the driver to create
 461          * a relocation list for state buffers and not re-write it per
 462          * exec using the buffer.
 463          */
 464         __u32 target_handle;
 465
 466         /**
 467          * Value to be added to the offset of the target buffer to make up
 468          * the relocation entry.
 469          */
 470         __u32 delta;
 471
 472         /** Offset in the buffer the relocation entry will be written into */
 473         __u64 offset;
 474
 475         /**
 476          * Offset value of the target buffer that the relocation entry was last
 477          * written as.
 478          *
 479          * If the buffer has the same offset as last time, we can skip syncing
 480          * and writing the relocation.  This value is written back out by
 481          * the execbuffer ioctl when the relocation is written.
 482          */
 483         __u64 presumed_offset;
 484
 485         /**
 486          * Target memory domains read by this operation.
 487          */
 488         __u32 read_domains;
 489
 490         /**
 491          * Target memory domains written by this operation.
 492          *
 493          * Note that only one domain may be written by the whole
 494          * execbuffer operation, so that where there are conflicts,
 495          * the application will get -EINVAL back.
 496          */
 497         __u32 write_domain;
 498 };
 499
 500 /** @{
 501  * Intel memory domains
 502  *
 503  * Most of these just align with the various caches in
 504  * the system and are used to flush and invalidate as
 505  * objects end up cached in different domains.
 506  */
 507 /** CPU cache */
 508 #define I915_GEM_DOMAIN_CPU             0x00000001
 509 /** Render cache, used by 2D and 3D drawing */
 510 #define I915_GEM_DOMAIN_RENDER          0x00000002
 511 /** Sampler cache, used by texture engine */
 512 #define I915_GEM_DOMAIN_SAMPLER         0x00000004
 513 /** Command queue, used to load batch buffers */
 514 #define I915_GEM_DOMAIN_COMMAND         0x00000008
 515 /** Instruction cache, used by shader programs */
 516 #define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
 517 /** Vertex address cache */
 518 #define I915_GEM_DOMAIN_VERTEX          0x00000020
 519 /** GTT domain - aperture and scanout */
 520 #define I915_GEM_DOMAIN_GTT             0x00000040
 521 /** @} */
 522
 523 struct drm_i915_gem_exec_object {
 524         /**
 525          * User's handle for a buffer to be bound into the GTT for this
 526          * operation.
 527          */
 528         __u32 handle;
 529
 530         /** Number of relocations to be performed on this buffer */
 531         __u32 relocation_count;
 532         /**
 533          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 534          * the relocations to be performed in this buffer.
 535          */
 536         __u64 relocs_ptr;
 537
 538         /** Required alignment in graphics aperture */
 539         __u64 alignment;
 540
 541         /**
 542          * Returned value of the updated offset of the object, for future
 543          * presumed_offset writes.
 544          */
 545         __u64 offset;
 546 };
 547
 548 struct drm_i915_gem_execbuffer {
 549         /**
 550          * List of buffers to be validated with their relocations to be
 551          * performend on them.
 552          *
 553          * This is a pointer to an array of struct drm_i915_gem_validate_entry.
 554          *
 555          * These buffers must be listed in an order such that all relocations
 556          * a buffer is performing refer to buffers that have already appeared
 557          * in the validate list.
 558          */
 559         __u64 buffers_ptr;
 560         __u32 buffer_count;
 561
 562         /** Offset in the batchbuffer to start execution from. */
 563         __u32 batch_start_offset;
 564         /** Bytes used in batchbuffer from batch_start_offset */
 565         __u32 batch_len;
 566         __u32 DR1;
 567         __u32 DR4;
 568         __u32 num_cliprects;
 569         /** This is a struct drm_clip_rect *cliprects */
 570         __u64 cliprects_ptr;
 571 };
 572
 573 struct drm_i915_gem_exec_object2 {
 574         /**
 575          * User's handle for a buffer to be bound into the GTT for this
 576          * operation.
 577          */
 578         __u32 handle;
 579
 580         /** Number of relocations to be performed on this buffer */
 581         __u32 relocation_count;
 582         /**
 583          * Pointer to array of struct drm_i915_gem_relocation_entry containing
 584          * the relocations to be performed in this buffer.
 585          */
 586         __u64 relocs_ptr;
 587
 588         /** Required alignment in graphics aperture */
 589         __u64 alignment;
 590
 591         /**
 592          * Returned value of the updated offset of the object, for future
 593          * presumed_offset writes.
 594          */
 595         __u64 offset;
 596
 597 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
 598         __u64 flags;
 599         __u64 rsvd1;
 600         __u64 rsvd2;
 601 };
 602
 603 struct drm_i915_gem_execbuffer2 {
 604         /**
 605          * List of gem_exec_object2 structs
 606          */
 607         __u64 buffers_ptr;
 608         __u32 buffer_count;
 609
 610         /** Offset in the batchbuffer to start execution from. */
 611         __u32 batch_start_offset;
 612         /** Bytes used in batchbuffer from batch_start_offset */
 613         __u32 batch_len;
 614         __u32 DR1;
 615         __u32 DR4;
 616         __u32 num_cliprects;
 617         /** This is a struct drm_clip_rect *cliprects */
 618         __u64 cliprects_ptr;
 619         __u64 flags; /* currently unused */
 620         __u64 rsvd1;
 621         __u64 rsvd2;
 622 };
 623
 624 struct drm_i915_gem_pin {
 625         /** Handle of the buffer to be pinned. */
 626         __u32 handle;
 627         __u32 pad;
 628
 629         /** alignment required within the aperture */
 630         __u64 alignment;
 631
 632         /** Returned GTT offset of the buffer. */
 633         __u64 offset;
 634 };
 635
 636 struct drm_i915_gem_unpin {
 637         /** Handle of the buffer to be unpinned. */
 638         __u32 handle;
 639         __u32 pad;
 640 };
 641
 642 struct drm_i915_gem_busy {
 643         /** Handle of the buffer to check for busy */
 644         __u32 handle;
 645
 646         /** Return busy status (1 if busy, 0 if idle) */
 647         __u32 busy;
 648 };
 649
 650 #define I915_TILING_NONE        0
 651 #define I915_TILING_X           1
 652 #define I915_TILING_Y           2
 653
 654 #define I915_BIT_6_SWIZZLE_NONE         0
 655 #define I915_BIT_6_SWIZZLE_9            1
 656 #define I915_BIT_6_SWIZZLE_9_10         2
 657 #define I915_BIT_6_SWIZZLE_9_11         3
 658 #define I915_BIT_6_SWIZZLE_9_10_11      4
 659 /* Not seen by userland */
 660 #define I915_BIT_6_SWIZZLE_UNKNOWN      5
 661 /* Seen by userland. */
 662 #define I915_BIT_6_SWIZZLE_9_17         6
 663 #define I915_BIT_6_SWIZZLE_9_10_17      7
 664
 665 struct drm_i915_gem_set_tiling {
 666         /** Handle of the buffer to have its tiling state updated */
 667         __u32 handle;
 668
 669         /**
 670          * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 671          * I915_TILING_Y).
 672          *
 673          * This value is to be set on request, and will be updated by the
 674          * kernel on successful return with the actual chosen tiling layout.
 675          *
 676          * The tiling mode may be demoted to I915_TILING_NONE when the system
 677          * has bit 6 swizzling that can't be managed correctly by GEM.
 678          *
 679          * Buffer contents become undefined when changing tiling_mode.
 680          */
 681         __u32 tiling_mode;
 682
 683         /**
 684          * Stride in bytes for the object when in I915_TILING_X or
 685          * I915_TILING_Y.
 686          */
 687         __u32 stride;
 688
 689         /**
 690          * Returned address bit 6 swizzling required for CPU access through
 691          * mmap mapping.
 692          */
 693         __u32 swizzle_mode;
 694 };
 695
 696 struct drm_i915_gem_get_tiling {
 697         /** Handle of the buffer to get tiling state for. */
 698         __u32 handle;
 699
 700         /**
 701          * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
 702          * I915_TILING_Y).
 703          */
 704         __u32 tiling_mode;
 705
 706         /**
 707          * Returned address bit 6 swizzling required for CPU access through
 708          * mmap mapping.
 709          */
 710         __u32 swizzle_mode;
 711 };
 712
 713 struct drm_i915_gem_get_aperture {
 714         /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
 715         __u64 aper_size;
 716
 717         /**
 718          * Available space in the aperture used by i915_gem_execbuffer, in
 719          * bytes
 720          */
 721         __u64 aper_available_size;
 722 };
 723
 724 struct drm_i915_get_pipe_from_crtc_id {
 725         /** ID of CRTC being requested **/
 726         __u32 crtc_id;
 727
 728         /** pipe of requested CRTC **/
 729         __u32 pipe;
 730 };
 731
 732 #define I915_MADV_WILLNEED 0
 733 #define I915_MADV_DONTNEED 1
 734 #define __I915_MADV_PURGED 2 /* internal state */
 735
 736 struct drm_i915_gem_madvise {
 737         /** Handle of the buffer to change the backing store advice */
 738         __u32 handle;
 739
 740         /* Advice: either the buffer will be needed again in the near future,
 741          *         or wont be and could be discarded under memory pressure.
 742          */
 743         __u32 madv;
 744
 745         /** Whether the backing store still exists. */
 746         __u32 retained;
 747 };
 748
 749 /* flags */
 750 #define I915_OVERLAY_TYPE_MASK          0xff
 751 #define I915_OVERLAY_YUV_PLANAR         0x01
 752 #define I915_OVERLAY_YUV_PACKED         0x02
 753 #define I915_OVERLAY_RGB                0x03
 754
 755 #define I915_OVERLAY_DEPTH_MASK         0xff00
 756 #define I915_OVERLAY_RGB24              0x1000
 757 #define I915_OVERLAY_RGB16              0x2000
 758 #define I915_OVERLAY_RGB15              0x3000
 759 #define I915_OVERLAY_YUV422             0x0100
 760 #define I915_OVERLAY_YUV411             0x0200
 761 #define I915_OVERLAY_YUV420             0x0300
 762 #define I915_OVERLAY_YUV410             0x0400
 763
 764 #define I915_OVERLAY_SWAP_MASK          0xff0000
 765 #define I915_OVERLAY_NO_SWAP            0x000000
 766 #define I915_OVERLAY_UV_SWAP            0x010000
 767 #define I915_OVERLAY_Y_SWAP             0x020000
 768 #define I915_OVERLAY_Y_AND_UV_SWAP      0x030000
 769
 770 #define I915_OVERLAY_FLAGS_MASK         0xff000000
 771 #define I915_OVERLAY_ENABLE             0x01000000
 772
 773 struct drm_intel_overlay_put_image {
 774         /* various flags and src format description */
 775         __u32 flags;
 776         /* source picture description */
 777         __u32 bo_handle;
 778         /* stride values and offsets are in bytes, buffer relative */
 779         __u16 stride_Y; /* stride for packed formats */
 780         __u16 stride_UV;
 781         __u32 offset_Y; /* offset for packet formats */
 782         __u32 offset_U;
 783         __u32 offset_V;
 784         /* in pixels */
 785         __u16 src_width;
 786         __u16 src_height;
 787         /* to compensate the scaling factors for partially covered surfaces */
 788         __u16 src_scan_width;
 789         __u16 src_scan_height;
 790         /* output crtc description */
 791         __u32 crtc_id;
 792         __u16 dst_x;
 793         __u16 dst_y;
 794         __u16 dst_width;
 795         __u16 dst_height;
 796 };
 797
 798 /* flags */
 799 #define I915_OVERLAY_UPDATE_ATTRS       (1<<0)
 800 #define I915_OVERLAY_UPDATE_GAMMA       (1<<1)
 801 struct drm_intel_overlay_attrs {
 802         __u32 flags;
 803         __u32 color_key;
 804         __s32 brightness;
 805         __u32 contrast;
 806         __u32 saturation;
 807         __u32 gamma0;
 808         __u32 gamma1;
 809         __u32 gamma2;
 810         __u32 gamma3;
 811         __u32 gamma4;
 812         __u32 gamma5;
 813 };
 814
 815 #endif                          /* _I915_DRM_H_ */