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[PATCH] define for_each_online_pgdat
[linux-2.6/linux-2.6-openrd.git] / include / asm-powerpc / cputable.h
blobfe45f6f3a4bee59fa4d4757834190ff4c5e44b96
1 #ifndef __ASM_POWERPC_CPUTABLE_H
2 #define __ASM_POWERPC_CPUTABLE_H
3
4 #include <asm/asm-compat.h>
5
6 #define PPC_FEATURE_32 0x80000000
7 #define PPC_FEATURE_64 0x40000000
8 #define PPC_FEATURE_601_INSTR 0x20000000
9 #define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10 #define PPC_FEATURE_HAS_FPU 0x08000000
11 #define PPC_FEATURE_HAS_MMU 0x04000000
12 #define PPC_FEATURE_HAS_4xxMAC 0x02000000
13 #define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14 #define PPC_FEATURE_HAS_SPE 0x00800000
15 #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16 #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
17 #define PPC_FEATURE_NO_TB 0x00100000
18 #define PPC_FEATURE_POWER4 0x00080000
19 #define PPC_FEATURE_POWER5 0x00040000
20 #define PPC_FEATURE_POWER5_PLUS 0x00020000
21 #define PPC_FEATURE_CELL 0x00010000
22 #define PPC_FEATURE_BOOKE 0x00008000
23 #define PPC_FEATURE_SMT 0x00004000
24 #define PPC_FEATURE_ICACHE_SNOOP 0x00002000
25
26 #ifdef __KERNEL__
27 #ifndef __ASSEMBLY__
28
29 /* This structure can grow, it's real size is used by head.S code
30 * via the mkdefs mechanism.
31 */
32 struct cpu_spec;
33
34 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
35
36 enum powerpc_oprofile_type {
37 PPC_OPROFILE_INVALID = 0,
38 PPC_OPROFILE_RS64 = 1,
39 PPC_OPROFILE_POWER4 = 2,
40 PPC_OPROFILE_G4 = 3,
41 PPC_OPROFILE_BOOKE = 4,
42 };
43
44 struct cpu_spec {
45 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
46 unsigned int pvr_mask;
47 unsigned int pvr_value;
48
49 char *cpu_name;
50 unsigned long cpu_features; /* Kernel features */
51 unsigned int cpu_user_features; /* Userland features */
52
53 /* cache line sizes */
54 unsigned int icache_bsize;
55 unsigned int dcache_bsize;
56
57 /* number of performance monitor counters */
58 unsigned int num_pmcs;
59
60 /* this is called to initialize various CPU bits like L1 cache,
61 * BHT, SPD, etc... from head.S before branching to identify_machine
62 */
63 cpu_setup_t cpu_setup;
64
65 /* Used by oprofile userspace to select the right counters */
66 char *oprofile_cpu_type;
67
68 /* Processor specific oprofile operations */
69 enum powerpc_oprofile_type oprofile_type;
70
71 /* Name of processor class, for the ELF AT_PLATFORM entry */
72 char *platform;
73 };
74
75 extern struct cpu_spec *cur_cpu_spec;
76
77 extern void identify_cpu(unsigned long offset, unsigned long cpu);
78 extern void do_cpu_ftr_fixups(unsigned long offset);
79
80 #endif /* __ASSEMBLY__ */
81
82 /* CPU kernel features */
83
84 /* Retain the 32b definitions all use bottom half of word */
85 #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
86 #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
87 #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
88 #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
89 #define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
90 #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
91 #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
92 #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
93 #define CPU_FTR_601 ASM_CONST(0x0000000000000100)
94 #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
95 #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
96 #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
97 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
98 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
99 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
100 #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
101 #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
102 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
103 #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
104 #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
105 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
106
107 #ifdef __powerpc64__
108 /* Add the 64b processor unique features in the top half of the word */
109 #define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
110 #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
111 #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
112 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
113 #define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
114 #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
115 #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
116 #define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
117 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
118 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
119 #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
120 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
121 #define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
122 #define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
123 #else
124 /* ensure on 32b processors the flags are available for compiling but
125 * don't do anything */
126 #define CPU_FTR_SLB ASM_CONST(0x0)
127 #define CPU_FTR_16M_PAGE ASM_CONST(0x0)
128 #define CPU_FTR_TLBIEL ASM_CONST(0x0)
129 #define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
130 #define CPU_FTR_IABR ASM_CONST(0x0)
131 #define CPU_FTR_MMCRA ASM_CONST(0x0)
132 #define CPU_FTR_CTRL ASM_CONST(0x0)
133 #define CPU_FTR_SMT ASM_CONST(0x0)
134 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
135 #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
136 #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
137 #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
138 #define CPU_FTR_PURR ASM_CONST(0x0)
139 #endif
140
141 #ifndef __ASSEMBLY__
142
143 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
144 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
145 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
146
147 /* iSeries doesn't support large pages */
148 #ifdef CONFIG_PPC_ISERIES
149 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
150 #else
151 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
152 #endif /* CONFIG_PPC_ISERIES */
153
154 /* We only set the altivec features if the kernel was compiled with altivec
155 * support
156 */
157 #ifdef CONFIG_ALTIVEC
158 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
159 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
160 #else
161 #define CPU_FTR_ALTIVEC_COMP 0
162 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
163 #endif
164
165 /* We need to mark all pages as being coherent if we're SMP or we
166 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
167 * it for PCI "streaming/prefetch" to work properly.
168 */
169 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
170 || defined(CONFIG_PPC_83xx)
171 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
172 #else
173 #define CPU_FTR_COMMON 0
174 #endif
175
176 /* The powersave features NAP & DOZE seems to confuse BDI when
177 debugging. So if a BDI is used, disable theses
178 */
179 #ifndef CONFIG_BDI_SWITCH
180 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
181 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
182 #else
183 #define CPU_FTR_MAYBE_CAN_DOZE 0
184 #define CPU_FTR_MAYBE_CAN_NAP 0
185 #endif
186
187 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
188 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
189 !defined(CONFIG_BOOKE))
190
191 enum {
192 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
193 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
194 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
195 CPU_FTR_MAYBE_CAN_NAP,
196 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
197 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
198 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
199 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
200 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
201 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
202 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
203 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
204 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
205 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
206 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
207 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
209 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
210 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
211 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
214 CPU_FTR_NO_DPM,
215 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
217 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
218 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
219 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
220 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
221 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
222 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
223 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
225 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
226 CPU_FTR_MAYBE_CAN_NAP,
227 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
228 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
229 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
230 CPU_FTR_MAYBE_CAN_NAP,
231 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
232 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
233 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
234 CPU_FTR_NEED_COHERENT,
235 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
236 CPU_FTR_USE_TB |
237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
238 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
239 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
240 CPU_FTR_NEED_COHERENT,
241 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
242 CPU_FTR_USE_TB |
243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
245 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
246 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
247 CPU_FTR_USE_TB |
248 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
249 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
250 CPU_FTR_NEED_COHERENT,
251 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
252 CPU_FTR_USE_TB |
253 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
254 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
255 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
256 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
257 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
258 CPU_FTR_USE_TB |
259 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
260 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
261 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
262 CPU_FTR_NEED_COHERENT,
263 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
264 CPU_FTR_USE_TB |
265 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
266 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
267 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
268 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
269 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
270 CPU_FTR_USE_TB |
271 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
272 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
273 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
274 CPU_FTR_NEED_COHERENT,
275 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
276 CPU_FTR_USE_TB |
277 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
278 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
279 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
280 CPU_FTR_NEED_COHERENT,
281 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
282 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
283 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
284 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
285 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
286 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS |
287 CPU_FTR_COMMON,
288 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
289 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
290 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
291 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
292 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
293 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN,
294 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
295 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN,
297 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
298 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
299 CPU_FTR_NODSISRALIGN,
300 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
301 CPU_FTR_NODSISRALIGN,
302 CPU_FTRS_E200 = CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN,
303 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
304 CPU_FTR_NODSISRALIGN,
305 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
306 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN,
307 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN,
308 #ifdef __powerpc64__
309 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
310 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
311 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
312 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
313 CPU_FTR_MMCRA | CPU_FTR_CTRL,
314 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
315 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
316 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
317 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
318 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
319 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
321 CPU_FTR_MMCRA | CPU_FTR_SMT |
322 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
323 CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR,
324 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
325 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
326 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT |
327 CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO,
328 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
329 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
330 #endif
331
332 CPU_FTRS_POSSIBLE =
333 #ifdef __powerpc64__
334 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
335 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
336 CPU_FTR_CI_LARGE_PAGE |
337 #else
338 #if CLASSIC_PPC
339 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
340 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
341 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
342 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
343 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
344 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
345 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
346 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
347 #else
348 CPU_FTRS_GENERIC_32 |
349 #endif
350 #ifdef CONFIG_PPC64BRIDGE
351 CPU_FTRS_POWER3_32 |
352 #endif
353 #ifdef CONFIG_POWER4
354 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
355 #endif
356 #ifdef CONFIG_8xx
357 CPU_FTRS_8XX |
358 #endif
359 #ifdef CONFIG_40x
360 CPU_FTRS_40X |
361 #endif
362 #ifdef CONFIG_44x
363 CPU_FTRS_44X |
364 #endif
365 #ifdef CONFIG_E200
366 CPU_FTRS_E200 |
367 #endif
368 #ifdef CONFIG_E500
369 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
370 #endif
371 #endif /* __powerpc64__ */
372 0,
373
374 CPU_FTRS_ALWAYS =
375 #ifdef __powerpc64__
376 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
377 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
378 #else
379 #if CLASSIC_PPC
380 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
381 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
382 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
383 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
384 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
385 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
386 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
387 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
388 #else
389 CPU_FTRS_GENERIC_32 &
390 #endif
391 #ifdef CONFIG_PPC64BRIDGE
392 CPU_FTRS_POWER3_32 &
393 #endif
394 #ifdef CONFIG_POWER4
395 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
396 #endif
397 #ifdef CONFIG_8xx
398 CPU_FTRS_8XX &
399 #endif
400 #ifdef CONFIG_40x
401 CPU_FTRS_40X &
402 #endif
403 #ifdef CONFIG_44x
404 CPU_FTRS_44X &
405 #endif
406 #ifdef CONFIG_E200
407 CPU_FTRS_E200 &
408 #endif
409 #ifdef CONFIG_E500
410 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
411 #endif
412 #endif /* __powerpc64__ */
413 CPU_FTRS_POSSIBLE,
414 };
415
416 static inline int cpu_has_feature(unsigned long feature)
417 {
418 return (CPU_FTRS_ALWAYS & feature) ||
419 (CPU_FTRS_POSSIBLE
420 & cur_cpu_spec->cpu_features
421 & feature);
422 }
423
424 #endif /* !__ASSEMBLY__ */
425
426 #ifdef __ASSEMBLY__
427
428 #define BEGIN_FTR_SECTION 98:
429
430 #ifndef __powerpc64__
431 #define END_FTR_SECTION(msk, val) \
432 99: \
433 .section __ftr_fixup,"a"; \
434 .align 2; \
435 .long msk; \
436 .long val; \
437 .long 98b; \
438 .long 99b; \
439 .previous
440 #else /* __powerpc64__ */
441 #define END_FTR_SECTION(msk, val) \
442 99: \
443 .section __ftr_fixup,"a"; \
444 .align 3; \
445 .llong msk; \
446 .llong val; \
447 .llong 98b; \
448 .llong 99b; \
449 .previous
450 #endif /* __powerpc64__ */
451
452 #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
453 #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
454 #endif /* __ASSEMBLY__ */
455
456 #endif /* __KERNEL__ */
457 #endif /* __ASM_POWERPC_CPUTABLE_H */
linux 2.6 git repository for openrd