drivers/dma/ioatdma_hw.h

   1 /*
   2  * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc., 59
  16  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called COPYING.
  20  */
  21 #ifndef _IOAT_HW_H_
  22 #define _IOAT_HW_H_
  23
  24 /* PCI Configuration Space Values */
  25 #define IOAT_PCI_VID            0x8086
  26
  27 /* CB device ID's */
  28 #define IOAT_PCI_DID_5000       0x1A38
  29 #define IOAT_PCI_DID_CNB        0x360B
  30 #define IOAT_PCI_DID_SCNB       0x65FF
  31 #define IOAT_PCI_DID_SNB        0x402F
  32
  33 #define IOAT_PCI_RID            0x00
  34 #define IOAT_PCI_SVID           0x8086
  35 #define IOAT_PCI_SID            0x8086
  36 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  37 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  38 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  39
  40 struct ioat_dma_descriptor {
  41         uint32_t        size;
  42         uint32_t        ctl;
  43         uint64_t        src_addr;
  44         uint64_t        dst_addr;
  45         uint64_t        next;
  46         uint64_t        rsv1;
  47         uint64_t        rsv2;
  48         uint64_t        user1;
  49         uint64_t        user2;
  50 };
  51
  52 #define IOAT_DMA_DESCRIPTOR_CTL_INT_GN  0x00000001
  53 #define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN  0x00000002
  54 #define IOAT_DMA_DESCRIPTOR_CTL_DST_SN  0x00000004
  55 #define IOAT_DMA_DESCRIPTOR_CTL_CP_STS  0x00000008
  56 #define IOAT_DMA_DESCRIPTOR_CTL_FRAME   0x00000010
  57 #define IOAT_DMA_DESCRIPTOR_NUL         0x00000020
  58 #define IOAT_DMA_DESCRIPTOR_CTL_SP_BRK  0x00000040
  59 #define IOAT_DMA_DESCRIPTOR_CTL_DP_BRK  0x00000080
  60 #define IOAT_DMA_DESCRIPTOR_CTL_BNDL    0x00000100
  61 #define IOAT_DMA_DESCRIPTOR_CTL_DCA     0x00000200
  62 #define IOAT_DMA_DESCRIPTOR_CTL_BUFHINT 0x00000400
  63
  64 #define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_CONTEXT  0xFF000000
  65 #define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_DMA      0x00000000
  66
  67 #define IOAT_DMA_DESCRIPTOR_CTL_CONTEXT_DCA     0x00000001
  68 #define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_MASK     0xFF000000
  69
  70 #endif