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Blackfin: BF537: push down error masks to avoid namespace pollution
[linux-2.6/linux-2.6-openrd.git] / arch / blackfin / mach-common / ints-priority.c
blob1873b2c1fede8b2d267d639dbe9c111e05091b10
1 /*
2 * Set up the interrupt priorities
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
10 *
11 * Licensed under the GPL-2
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #ifdef CONFIG_IPIPE
19 #include <linux/ipipe.h>
20 #endif
21 #ifdef CONFIG_KGDB
22 #include <linux/kgdb.h>
23 #endif
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
26 #include <asm/gpio.h>
27 #include <asm/irq_handler.h>
28 #include <asm/dpmc.h>
29 #include <asm/bfin5xx_spi.h>
30 #include <asm/bfin_sport.h>
31
32 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
33
34 #ifdef BF537_FAMILY
35 # define BF537_GENERIC_ERROR_INT_DEMUX
36 # define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
37 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
38 # define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
39 # define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
40 # define UART_ERR_MASK (0x6) /* UART_IIR */
41 # define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
42 #else
43 # undef BF537_GENERIC_ERROR_INT_DEMUX
44 #endif
45
46 /*
47 * NOTES:
48 * - we have separated the physical Hardware interrupt from the
49 * levels that the LINUX kernel sees (see the description in irq.h)
50 * -
51 */
52
53 #ifndef CONFIG_SMP
54 /* Initialize this to an actual value to force it into the .data
55 * section so that we know it is properly initialized at entry into
56 * the kernel but before bss is initialized to zero (which is where
57 * it would live otherwise). The 0x1f magic represents the IRQs we
58 * cannot actually mask out in hardware.
59 */
60 unsigned long bfin_irq_flags = 0x1f;
61 EXPORT_SYMBOL(bfin_irq_flags);
62 #endif
63
64 /* The number of spurious interrupts */
65 atomic_t num_spurious;
66
67 #ifdef CONFIG_PM
68 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
69 unsigned vr_wakeup;
70 #endif
71
72 struct ivgx {
73 /* irq number for request_irq, available in mach-bf5xx/irq.h */
74 unsigned int irqno;
75 /* corresponding bit in the SIC_ISR register */
76 unsigned int isrflag;
77 } ivg_table[NR_PERI_INTS];
78
79 struct ivg_slice {
80 /* position of first irq in ivg_table for given ivg */
81 struct ivgx *ifirst;
82 struct ivgx *istop;
83 } ivg7_13[IVG13 - IVG7 + 1];
84
85
86 /*
87 * Search SIC_IAR and fill tables with the irqvalues
88 * and their positions in the SIC_ISR register.
89 */
90 static void __init search_IAR(void)
91 {
92 unsigned ivg, irq_pos = 0;
93 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
94 int irqn;
95
96 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
97
98 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
99 int iar_shift = (irqn & 7) * 4;
100 if (ivg == (0xf &
101 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
102 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
103 bfin_read32((unsigned long *)SIC_IAR0 +
104 ((irqn % 32) >> 3) + ((irqn / 32) *
105 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
106 #else
107 bfin_read32((unsigned long *)SIC_IAR0 +
108 (irqn >> 3)) >> iar_shift)) {
109 #endif
110 ivg_table[irq_pos].irqno = IVG7 + irqn;
111 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
112 ivg7_13[ivg].istop++;
113 irq_pos++;
114 }
115 }
116 }
117 }
118
119 /*
120 * This is for core internal IRQs
121 */
122
123 static void bfin_ack_noop(unsigned int irq)
124 {
125 /* Dummy function. */
126 }
127
128 static void bfin_core_mask_irq(unsigned int irq)
129 {
130 bfin_irq_flags &= ~(1 << irq);
131 if (!irqs_disabled_hw())
132 local_irq_enable_hw();
133 }
134
135 static void bfin_core_unmask_irq(unsigned int irq)
136 {
137 bfin_irq_flags |= 1 << irq;
138 /*
139 * If interrupts are enabled, IMASK must contain the same value
140 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
141 * are currently disabled we need not do anything; one of the
142 * callers will take care of setting IMASK to the proper value
143 * when reenabling interrupts.
144 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
145 * what we need.
146 */
147 if (!irqs_disabled_hw())
148 local_irq_enable_hw();
149 return;
150 }
151
152 static void bfin_internal_mask_irq(unsigned int irq)
153 {
154 unsigned long flags;
155
156 #ifdef CONFIG_BF53x
157 local_irq_save_hw(flags);
158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << SIC_SYSIRQ(irq)));
160 #else
161 unsigned mask_bank, mask_bit;
162 local_irq_save_hw(flags);
163 mask_bank = SIC_SYSIRQ(irq) / 32;
164 mask_bit = SIC_SYSIRQ(irq) % 32;
165 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
166 ~(1 << mask_bit));
167 #ifdef CONFIG_SMP
168 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
169 ~(1 << mask_bit));
170 #endif
171 #endif
172 local_irq_restore_hw(flags);
173 }
174
175 static void bfin_internal_unmask_irq(unsigned int irq)
176 {
177 unsigned long flags;
178
179 #ifdef CONFIG_BF53x
180 local_irq_save_hw(flags);
181 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
182 (1 << SIC_SYSIRQ(irq)));
183 #else
184 unsigned mask_bank, mask_bit;
185 local_irq_save_hw(flags);
186 mask_bank = SIC_SYSIRQ(irq) / 32;
187 mask_bit = SIC_SYSIRQ(irq) % 32;
188 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
189 (1 << mask_bit));
190 #ifdef CONFIG_SMP
191 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
192 (1 << mask_bit));
193 #endif
194 #endif
195 local_irq_restore_hw(flags);
196 }
197
198 #ifdef CONFIG_PM
199 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
200 {
201 u32 bank, bit, wakeup = 0;
202 unsigned long flags;
203 bank = SIC_SYSIRQ(irq) / 32;
204 bit = SIC_SYSIRQ(irq) % 32;
205
206 switch (irq) {
207 #ifdef IRQ_RTC
208 case IRQ_RTC:
209 wakeup |= WAKE;
210 break;
211 #endif
212 #ifdef IRQ_CAN0_RX
213 case IRQ_CAN0_RX:
214 wakeup |= CANWE;
215 break;
216 #endif
217 #ifdef IRQ_CAN1_RX
218 case IRQ_CAN1_RX:
219 wakeup |= CANWE;
220 break;
221 #endif
222 #ifdef IRQ_USB_INT0
223 case IRQ_USB_INT0:
224 wakeup |= USBWE;
225 break;
226 #endif
227 #ifdef IRQ_KEY
228 case IRQ_KEY:
229 wakeup |= KPADWE;
230 break;
231 #endif
232 #ifdef CONFIG_BF54x
233 case IRQ_CNT:
234 wakeup |= ROTWE;
235 break;
236 #endif
237 default:
238 break;
239 }
240
241 local_irq_save_hw(flags);
242
243 if (state) {
244 bfin_sic_iwr[bank] |= (1 << bit);
245 vr_wakeup |= wakeup;
246
247 } else {
248 bfin_sic_iwr[bank] &= ~(1 << bit);
249 vr_wakeup &= ~wakeup;
250 }
251
252 local_irq_restore_hw(flags);
253
254 return 0;
255 }
256 #endif
257
258 static struct irq_chip bfin_core_irqchip = {
259 .name = "CORE",
260 .ack = bfin_ack_noop,
261 .mask = bfin_core_mask_irq,
262 .unmask = bfin_core_unmask_irq,
263 };
264
265 static struct irq_chip bfin_internal_irqchip = {
266 .name = "INTN",
267 .ack = bfin_ack_noop,
268 .mask = bfin_internal_mask_irq,
269 .unmask = bfin_internal_unmask_irq,
270 .mask_ack = bfin_internal_mask_irq,
271 .disable = bfin_internal_mask_irq,
272 .enable = bfin_internal_unmask_irq,
273 #ifdef CONFIG_PM
274 .set_wake = bfin_internal_set_wake,
275 #endif
276 };
277
278 static void bfin_handle_irq(unsigned irq)
279 {
280 #ifdef CONFIG_IPIPE
281 struct pt_regs regs; /* Contents not used. */
282 ipipe_trace_irq_entry(irq);
283 __ipipe_handle_irq(irq, &regs);
284 ipipe_trace_irq_exit(irq);
285 #else /* !CONFIG_IPIPE */
286 struct irq_desc *desc = irq_desc + irq;
287 desc->handle_irq(irq, desc);
288 #endif /* !CONFIG_IPIPE */
289 }
290
291 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
292 static int error_int_mask;
293
294 static void bfin_generic_error_mask_irq(unsigned int irq)
295 {
296 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
297
298 if (!error_int_mask)
299 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
300 }
301
302 static void bfin_generic_error_unmask_irq(unsigned int irq)
303 {
304 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
305 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
306 }
307
308 static struct irq_chip bfin_generic_error_irqchip = {
309 .name = "ERROR",
310 .ack = bfin_ack_noop,
311 .mask_ack = bfin_generic_error_mask_irq,
312 .mask = bfin_generic_error_mask_irq,
313 .unmask = bfin_generic_error_unmask_irq,
314 };
315
316 static void bfin_demux_error_irq(unsigned int int_err_irq,
317 struct irq_desc *inta_desc)
318 {
319 int irq = 0;
320
321 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
322 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
323 irq = IRQ_MAC_ERROR;
324 else
325 #endif
326 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
327 irq = IRQ_SPORT0_ERROR;
328 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
329 irq = IRQ_SPORT1_ERROR;
330 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
331 irq = IRQ_PPI_ERROR;
332 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
333 irq = IRQ_CAN_ERROR;
334 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
335 irq = IRQ_SPI_ERROR;
336 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
337 irq = IRQ_UART0_ERROR;
338 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
339 irq = IRQ_UART1_ERROR;
340
341 if (irq) {
342 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
343 bfin_handle_irq(irq);
344 else {
345
346 switch (irq) {
347 case IRQ_PPI_ERROR:
348 bfin_write_PPI_STATUS(PPI_ERR_MASK);
349 break;
350 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
351 case IRQ_MAC_ERROR:
352 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
353 break;
354 #endif
355 case IRQ_SPORT0_ERROR:
356 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
357 break;
358
359 case IRQ_SPORT1_ERROR:
360 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
361 break;
362
363 case IRQ_CAN_ERROR:
364 bfin_write_CAN_GIS(CAN_ERR_MASK);
365 break;
366
367 case IRQ_SPI_ERROR:
368 bfin_write_SPI_STAT(SPI_ERR_MASK);
369 break;
370
371 default:
372 break;
373 }
374
375 pr_debug("IRQ %d:"
376 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
377 irq);
378 }
379 } else
380 printk(KERN_ERR
381 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
382 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
383 __func__, __FILE__, __LINE__);
384
385 }
386 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
387
388 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
389 {
390 #ifdef CONFIG_IPIPE
391 _set_irq_handler(irq, handle_level_irq);
392 #else
393 struct irq_desc *desc = irq_desc + irq;
394 /* May not call generic set_irq_handler() due to spinlock
395 recursion. */
396 desc->handle_irq = handle;
397 #endif
398 }
399
400 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
401 extern void bfin_gpio_irq_prepare(unsigned gpio);
402
403 #if !defined(CONFIG_BF54x)
404
405 static void bfin_gpio_ack_irq(unsigned int irq)
406 {
407 /* AFAIK ack_irq in case mask_ack is provided
408 * get's only called for edge sense irqs
409 */
410 set_gpio_data(irq_to_gpio(irq), 0);
411 }
412
413 static void bfin_gpio_mask_ack_irq(unsigned int irq)
414 {
415 struct irq_desc *desc = irq_desc + irq;
416 u32 gpionr = irq_to_gpio(irq);
417
418 if (desc->handle_irq == handle_edge_irq)
419 set_gpio_data(gpionr, 0);
420
421 set_gpio_maska(gpionr, 0);
422 }
423
424 static void bfin_gpio_mask_irq(unsigned int irq)
425 {
426 set_gpio_maska(irq_to_gpio(irq), 0);
427 }
428
429 static void bfin_gpio_unmask_irq(unsigned int irq)
430 {
431 set_gpio_maska(irq_to_gpio(irq), 1);
432 }
433
434 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
435 {
436 u32 gpionr = irq_to_gpio(irq);
437
438 if (__test_and_set_bit(gpionr, gpio_enabled))
439 bfin_gpio_irq_prepare(gpionr);
440
441 bfin_gpio_unmask_irq(irq);
442
443 return 0;
444 }
445
446 static void bfin_gpio_irq_shutdown(unsigned int irq)
447 {
448 u32 gpionr = irq_to_gpio(irq);
449
450 bfin_gpio_mask_irq(irq);
451 __clear_bit(gpionr, gpio_enabled);
452 bfin_gpio_irq_free(gpionr);
453 }
454
455 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
456 {
457 int ret;
458 char buf[16];
459 u32 gpionr = irq_to_gpio(irq);
460
461 if (type == IRQ_TYPE_PROBE) {
462 /* only probe unenabled GPIO interrupt lines */
463 if (test_bit(gpionr, gpio_enabled))
464 return 0;
465 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
466 }
467
468 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
469 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
470
471 snprintf(buf, 16, "gpio-irq%d", irq);
472 ret = bfin_gpio_irq_request(gpionr, buf);
473 if (ret)
474 return ret;
475
476 if (__test_and_set_bit(gpionr, gpio_enabled))
477 bfin_gpio_irq_prepare(gpionr);
478
479 } else {
480 __clear_bit(gpionr, gpio_enabled);
481 return 0;
482 }
483
484 set_gpio_inen(gpionr, 0);
485 set_gpio_dir(gpionr, 0);
486
487 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
488 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
489 set_gpio_both(gpionr, 1);
490 else
491 set_gpio_both(gpionr, 0);
492
493 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
494 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
495 else
496 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
497
498 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
499 set_gpio_edge(gpionr, 1);
500 set_gpio_inen(gpionr, 1);
501 set_gpio_data(gpionr, 0);
502
503 } else {
504 set_gpio_edge(gpionr, 0);
505 set_gpio_inen(gpionr, 1);
506 }
507
508 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
509 bfin_set_irq_handler(irq, handle_edge_irq);
510 else
511 bfin_set_irq_handler(irq, handle_level_irq);
512
513 return 0;
514 }
515
516 #ifdef CONFIG_PM
517 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
518 {
519 unsigned gpio = irq_to_gpio(irq);
520
521 if (state)
522 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
523 else
524 gpio_pm_wakeup_free(gpio);
525
526 return 0;
527 }
528 #endif
529
530 static void bfin_demux_gpio_irq(unsigned int inta_irq,
531 struct irq_desc *desc)
532 {
533 unsigned int i, gpio, mask, irq, search = 0;
534
535 switch (inta_irq) {
536 #if defined(CONFIG_BF53x)
537 case IRQ_PROG_INTA:
538 irq = IRQ_PF0;
539 search = 1;
540 break;
541 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
542 case IRQ_MAC_RX:
543 irq = IRQ_PH0;
544 break;
545 # endif
546 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
547 case IRQ_PORTF_INTA:
548 irq = IRQ_PF0;
549 break;
550 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
551 case IRQ_PORTF_INTA:
552 irq = IRQ_PF0;
553 break;
554 case IRQ_PORTG_INTA:
555 irq = IRQ_PG0;
556 break;
557 case IRQ_PORTH_INTA:
558 irq = IRQ_PH0;
559 break;
560 #elif defined(CONFIG_BF561)
561 case IRQ_PROG0_INTA:
562 irq = IRQ_PF0;
563 break;
564 case IRQ_PROG1_INTA:
565 irq = IRQ_PF16;
566 break;
567 case IRQ_PROG2_INTA:
568 irq = IRQ_PF32;
569 break;
570 #endif
571 default:
572 BUG();
573 return;
574 }
575
576 if (search) {
577 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
578 irq += i;
579
580 mask = get_gpiop_data(i) & get_gpiop_maska(i);
581
582 while (mask) {
583 if (mask & 1)
584 bfin_handle_irq(irq);
585 irq++;
586 mask >>= 1;
587 }
588 }
589 } else {
590 gpio = irq_to_gpio(irq);
591 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
592
593 do {
594 if (mask & 1)
595 bfin_handle_irq(irq);
596 irq++;
597 mask >>= 1;
598 } while (mask);
599 }
600
601 }
602
603 #else /* CONFIG_BF54x */
604
605 #define NR_PINT_SYS_IRQS 4
606 #define NR_PINT_BITS 32
607 #define NR_PINTS 160
608 #define IRQ_NOT_AVAIL 0xFF
609
610 #define PINT_2_BANK(x) ((x) >> 5)
611 #define PINT_2_BIT(x) ((x) & 0x1F)
612 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
613
614 static unsigned char irq2pint_lut[NR_PINTS];
615 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
616
617 struct pin_int_t {
618 unsigned int mask_set;
619 unsigned int mask_clear;
620 unsigned int request;
621 unsigned int assign;
622 unsigned int edge_set;
623 unsigned int edge_clear;
624 unsigned int invert_set;
625 unsigned int invert_clear;
626 unsigned int pinstate;
627 unsigned int latch;
628 };
629
630 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
631 (struct pin_int_t *)PINT0_MASK_SET,
632 (struct pin_int_t *)PINT1_MASK_SET,
633 (struct pin_int_t *)PINT2_MASK_SET,
634 (struct pin_int_t *)PINT3_MASK_SET,
635 };
636
637 inline unsigned int get_irq_base(u32 bank, u8 bmap)
638 {
639 unsigned int irq_base;
640
641 if (bank < 2) { /*PA-PB */
642 irq_base = IRQ_PA0 + bmap * 16;
643 } else { /*PC-PJ */
644 irq_base = IRQ_PC0 + bmap * 16;
645 }
646
647 return irq_base;
648 }
649
650 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
651 void init_pint_lut(void)
652 {
653 u16 bank, bit, irq_base, bit_pos;
654 u32 pint_assign;
655 u8 bmap;
656
657 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
658
659 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
660
661 pint_assign = pint[bank]->assign;
662
663 for (bit = 0; bit < NR_PINT_BITS; bit++) {
664
665 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
666
667 irq_base = get_irq_base(bank, bmap);
668
669 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
670 bit_pos = bit + bank * NR_PINT_BITS;
671
672 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
673 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
674 }
675 }
676 }
677
678 static void bfin_gpio_ack_irq(unsigned int irq)
679 {
680 struct irq_desc *desc = irq_desc + irq;
681 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
682 u32 pintbit = PINT_BIT(pint_val);
683 u32 bank = PINT_2_BANK(pint_val);
684
685 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
686 if (pint[bank]->invert_set & pintbit)
687 pint[bank]->invert_clear = pintbit;
688 else
689 pint[bank]->invert_set = pintbit;
690 }
691 pint[bank]->request = pintbit;
692
693 }
694
695 static void bfin_gpio_mask_ack_irq(unsigned int irq)
696 {
697 struct irq_desc *desc = irq_desc + irq;
698 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
699 u32 pintbit = PINT_BIT(pint_val);
700 u32 bank = PINT_2_BANK(pint_val);
701
702 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
703 if (pint[bank]->invert_set & pintbit)
704 pint[bank]->invert_clear = pintbit;
705 else
706 pint[bank]->invert_set = pintbit;
707 }
708
709 pint[bank]->request = pintbit;
710 pint[bank]->mask_clear = pintbit;
711 }
712
713 static void bfin_gpio_mask_irq(unsigned int irq)
714 {
715 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
716
717 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
718 }
719
720 static void bfin_gpio_unmask_irq(unsigned int irq)
721 {
722 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
723 u32 pintbit = PINT_BIT(pint_val);
724 u32 bank = PINT_2_BANK(pint_val);
725
726 pint[bank]->request = pintbit;
727 pint[bank]->mask_set = pintbit;
728 }
729
730 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
731 {
732 u32 gpionr = irq_to_gpio(irq);
733 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
734
735 if (pint_val == IRQ_NOT_AVAIL) {
736 printk(KERN_ERR
737 "GPIO IRQ %d :Not in PINT Assign table "
738 "Reconfigure Interrupt to Port Assignemt\n", irq);
739 return -ENODEV;
740 }
741
742 if (__test_and_set_bit(gpionr, gpio_enabled))
743 bfin_gpio_irq_prepare(gpionr);
744
745 bfin_gpio_unmask_irq(irq);
746
747 return 0;
748 }
749
750 static void bfin_gpio_irq_shutdown(unsigned int irq)
751 {
752 u32 gpionr = irq_to_gpio(irq);
753
754 bfin_gpio_mask_irq(irq);
755 __clear_bit(gpionr, gpio_enabled);
756 bfin_gpio_irq_free(gpionr);
757 }
758
759 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
760 {
761 int ret;
762 char buf[16];
763 u32 gpionr = irq_to_gpio(irq);
764 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
765 u32 pintbit = PINT_BIT(pint_val);
766 u32 bank = PINT_2_BANK(pint_val);
767
768 if (pint_val == IRQ_NOT_AVAIL)
769 return -ENODEV;
770
771 if (type == IRQ_TYPE_PROBE) {
772 /* only probe unenabled GPIO interrupt lines */
773 if (test_bit(gpionr, gpio_enabled))
774 return 0;
775 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
776 }
777
778 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
779 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
780
781 snprintf(buf, 16, "gpio-irq%d", irq);
782 ret = bfin_gpio_irq_request(gpionr, buf);
783 if (ret)
784 return ret;
785
786 if (__test_and_set_bit(gpionr, gpio_enabled))
787 bfin_gpio_irq_prepare(gpionr);
788
789 } else {
790 __clear_bit(gpionr, gpio_enabled);
791 return 0;
792 }
793
794 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
795 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
796 else
797 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
798
799 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
800 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
801 if (gpio_get_value(gpionr))
802 pint[bank]->invert_set = pintbit;
803 else
804 pint[bank]->invert_clear = pintbit;
805 }
806
807 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
808 pint[bank]->edge_set = pintbit;
809 bfin_set_irq_handler(irq, handle_edge_irq);
810 } else {
811 pint[bank]->edge_clear = pintbit;
812 bfin_set_irq_handler(irq, handle_level_irq);
813 }
814
815 return 0;
816 }
817
818 #ifdef CONFIG_PM
819 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
820 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
821
822 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
823 {
824 u32 pint_irq;
825 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
826 u32 bank = PINT_2_BANK(pint_val);
827 u32 pintbit = PINT_BIT(pint_val);
828
829 switch (bank) {
830 case 0:
831 pint_irq = IRQ_PINT0;
832 break;
833 case 2:
834 pint_irq = IRQ_PINT2;
835 break;
836 case 3:
837 pint_irq = IRQ_PINT3;
838 break;
839 case 1:
840 pint_irq = IRQ_PINT1;
841 break;
842 default:
843 return -EINVAL;
844 }
845
846 bfin_internal_set_wake(pint_irq, state);
847
848 if (state)
849 pint_wakeup_masks[bank] |= pintbit;
850 else
851 pint_wakeup_masks[bank] &= ~pintbit;
852
853 return 0;
854 }
855
856 u32 bfin_pm_setup(void)
857 {
858 u32 val, i;
859
860 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
861 val = pint[i]->mask_clear;
862 pint_saved_masks[i] = val;
863 if (val ^ pint_wakeup_masks[i]) {
864 pint[i]->mask_clear = val;
865 pint[i]->mask_set = pint_wakeup_masks[i];
866 }
867 }
868
869 return 0;
870 }
871
872 void bfin_pm_restore(void)
873 {
874 u32 i, val;
875
876 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
877 val = pint_saved_masks[i];
878 if (val ^ pint_wakeup_masks[i]) {
879 pint[i]->mask_clear = pint[i]->mask_clear;
880 pint[i]->mask_set = val;
881 }
882 }
883 }
884 #endif
885
886 static void bfin_demux_gpio_irq(unsigned int inta_irq,
887 struct irq_desc *desc)
888 {
889 u32 bank, pint_val;
890 u32 request, irq;
891
892 switch (inta_irq) {
893 case IRQ_PINT0:
894 bank = 0;
895 break;
896 case IRQ_PINT2:
897 bank = 2;
898 break;
899 case IRQ_PINT3:
900 bank = 3;
901 break;
902 case IRQ_PINT1:
903 bank = 1;
904 break;
905 default:
906 return;
907 }
908
909 pint_val = bank * NR_PINT_BITS;
910
911 request = pint[bank]->request;
912
913 while (request) {
914 if (request & 1) {
915 irq = pint2irq_lut[pint_val] + SYS_IRQS;
916 bfin_handle_irq(irq);
917 }
918 pint_val++;
919 request >>= 1;
920 }
921
922 }
923 #endif
924
925 static struct irq_chip bfin_gpio_irqchip = {
926 .name = "GPIO",
927 .ack = bfin_gpio_ack_irq,
928 .mask = bfin_gpio_mask_irq,
929 .mask_ack = bfin_gpio_mask_ack_irq,
930 .unmask = bfin_gpio_unmask_irq,
931 .disable = bfin_gpio_mask_irq,
932 .enable = bfin_gpio_unmask_irq,
933 .set_type = bfin_gpio_irq_type,
934 .startup = bfin_gpio_irq_startup,
935 .shutdown = bfin_gpio_irq_shutdown,
936 #ifdef CONFIG_PM
937 .set_wake = bfin_gpio_set_wake,
938 #endif
939 };
940
941 void __cpuinit init_exception_vectors(void)
942 {
943 /* cannot program in software:
944 * evt0 - emulation (jtag)
945 * evt1 - reset
946 */
947 bfin_write_EVT2(evt_nmi);
948 bfin_write_EVT3(trap);
949 bfin_write_EVT5(evt_ivhw);
950 bfin_write_EVT6(evt_timer);
951 bfin_write_EVT7(evt_evt7);
952 bfin_write_EVT8(evt_evt8);
953 bfin_write_EVT9(evt_evt9);
954 bfin_write_EVT10(evt_evt10);
955 bfin_write_EVT11(evt_evt11);
956 bfin_write_EVT12(evt_evt12);
957 bfin_write_EVT13(evt_evt13);
958 bfin_write_EVT14(evt_evt14);
959 bfin_write_EVT15(evt_system_call);
960 CSYNC();
961 }
962
963 /*
964 * This function should be called during kernel startup to initialize
965 * the BFin IRQ handling routines.
966 */
967
968 int __init init_arch_irq(void)
969 {
970 int irq;
971 unsigned long ilat = 0;
972 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
973 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
974 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
975 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
976 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
977 # ifdef CONFIG_BF54x
978 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
979 # endif
980 # ifdef CONFIG_SMP
981 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
982 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
983 # endif
984 #else
985 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
986 #endif
987
988 local_irq_disable();
989
990 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
991 /* Clear EMAC Interrupt Status bits so we can demux it later */
992 bfin_write_EMAC_SYSTAT(-1);
993 #endif
994
995 #ifdef CONFIG_BF54x
996 # ifdef CONFIG_PINTx_REASSIGN
997 pint[0]->assign = CONFIG_PINT0_ASSIGN;
998 pint[1]->assign = CONFIG_PINT1_ASSIGN;
999 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1000 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1001 # endif
1002 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1003 init_pint_lut();
1004 #endif
1005
1006 for (irq = 0; irq <= SYS_IRQS; irq++) {
1007 if (irq <= IRQ_CORETMR)
1008 set_irq_chip(irq, &bfin_core_irqchip);
1009 else
1010 set_irq_chip(irq, &bfin_internal_irqchip);
1011
1012 switch (irq) {
1013 #if defined(CONFIG_BF53x)
1014 case IRQ_PROG_INTA:
1015 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1016 case IRQ_MAC_RX:
1017 # endif
1018 #elif defined(CONFIG_BF54x)
1019 case IRQ_PINT0:
1020 case IRQ_PINT1:
1021 case IRQ_PINT2:
1022 case IRQ_PINT3:
1023 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1024 case IRQ_PORTF_INTA:
1025 case IRQ_PORTG_INTA:
1026 case IRQ_PORTH_INTA:
1027 #elif defined(CONFIG_BF561)
1028 case IRQ_PROG0_INTA:
1029 case IRQ_PROG1_INTA:
1030 case IRQ_PROG2_INTA:
1031 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1032 case IRQ_PORTF_INTA:
1033 #endif
1034
1035 set_irq_chained_handler(irq,
1036 bfin_demux_gpio_irq);
1037 break;
1038 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1039 case IRQ_GENERIC_ERROR:
1040 set_irq_chained_handler(irq, bfin_demux_error_irq);
1041 break;
1042 #endif
1043
1044 #ifdef CONFIG_SMP
1045 #ifdef CONFIG_TICKSOURCE_GPTMR0
1046 case IRQ_TIMER0:
1047 #endif
1048 #ifdef CONFIG_TICKSOURCE_CORETMR
1049 case IRQ_CORETMR:
1050 #endif
1051 case IRQ_SUPPLE_0:
1052 case IRQ_SUPPLE_1:
1053 set_irq_handler(irq, handle_percpu_irq);
1054 break;
1055 #endif
1056
1057 #ifdef CONFIG_IPIPE
1058 #ifndef CONFIG_TICKSOURCE_CORETMR
1059 case IRQ_TIMER0:
1060 set_irq_handler(irq, handle_simple_irq);
1061 break;
1062 #endif
1063 case IRQ_CORETMR:
1064 set_irq_handler(irq, handle_simple_irq);
1065 break;
1066 default:
1067 set_irq_handler(irq, handle_level_irq);
1068 break;
1069 #else /* !CONFIG_IPIPE */
1070 default:
1071 set_irq_handler(irq, handle_simple_irq);
1072 break;
1073 #endif /* !CONFIG_IPIPE */
1074 }
1075 }
1076
1077 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1078 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1079 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1080 handle_level_irq);
1081 #endif
1082
1083 /* if configured as edge, then will be changed to do_edge_IRQ */
1084 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1085 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1086 handle_level_irq);
1087
1088
1089 bfin_write_IMASK(0);
1090 CSYNC();
1091 ilat = bfin_read_ILAT();
1092 CSYNC();
1093 bfin_write_ILAT(ilat);
1094 CSYNC();
1095
1096 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1097 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1098 * local_irq_enable()
1099 */
1100 program_IAR();
1101 /* Therefore it's better to setup IARs before interrupts enabled */
1102 search_IAR();
1103
1104 /* Enable interrupts IVG7-15 */
1105 bfin_irq_flags |= IMASK_IVG15 |
1106 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1107 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1108
1109 /* This implicitly covers ANOMALY_05000171
1110 * Boot-ROM code modifies SICA_IWRx wakeup registers
1111 */
1112 #ifdef SIC_IWR0
1113 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1114 # ifdef SIC_IWR1
1115 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1116 * will screw up the bootrom as it relies on MDMA0/1 waking it
1117 * up from IDLE instructions. See this report for more info:
1118 * http://blackfin.uclinux.org/gf/tracker/4323
1119 */
1120 if (ANOMALY_05000435)
1121 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1122 else
1123 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1124 # endif
1125 # ifdef SIC_IWR2
1126 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1127 # endif
1128 #else
1129 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1130 #endif
1131
1132 return 0;
1133 }
1134
1135 #ifdef CONFIG_DO_IRQ_L1
1136 __attribute__((l1_text))
1137 #endif
1138 void do_irq(int vec, struct pt_regs *fp)
1139 {
1140 if (vec == EVT_IVTMR_P) {
1141 vec = IRQ_CORETMR;
1142 } else {
1143 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1144 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1145 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1146 unsigned long sic_status[3];
1147
1148 if (smp_processor_id()) {
1149 # ifdef SICB_ISR0
1150 /* This will be optimized out in UP mode. */
1151 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1152 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1153 # endif
1154 } else {
1155 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1156 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1157 }
1158 # ifdef SIC_ISR2
1159 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1160 # endif
1161 for (;; ivg++) {
1162 if (ivg >= ivg_stop) {
1163 atomic_inc(&num_spurious);
1164 return;
1165 }
1166 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1167 break;
1168 }
1169 #else
1170 unsigned long sic_status;
1171
1172 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1173
1174 for (;; ivg++) {
1175 if (ivg >= ivg_stop) {
1176 atomic_inc(&num_spurious);
1177 return;
1178 } else if (sic_status & ivg->isrflag)
1179 break;
1180 }
1181 #endif
1182 vec = ivg->irqno;
1183 }
1184 asm_do_IRQ(vec, fp);
1185 }
1186
1187 #ifdef CONFIG_IPIPE
1188
1189 int __ipipe_get_irq_priority(unsigned irq)
1190 {
1191 int ient, prio;
1192
1193 if (irq <= IRQ_CORETMR)
1194 return irq;
1195
1196 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1197 struct ivgx *ivg = ivg_table + ient;
1198 if (ivg->irqno == irq) {
1199 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1200 if (ivg7_13[prio].ifirst <= ivg &&
1201 ivg7_13[prio].istop > ivg)
1202 return IVG7 + prio;
1203 }
1204 }
1205 }
1206
1207 return IVG15;
1208 }
1209
1210 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1211 #ifdef CONFIG_DO_IRQ_L1
1212 __attribute__((l1_text))
1213 #endif
1214 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1215 {
1216 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1217 struct ipipe_domain *this_domain = __ipipe_current_domain;
1218 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1219 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1220 int irq, s;
1221
1222 if (likely(vec == EVT_IVTMR_P))
1223 irq = IRQ_CORETMR;
1224 else {
1225 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1226 unsigned long sic_status[3];
1227
1228 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1229 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1230 # ifdef SIC_ISR2
1231 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1232 # endif
1233 for (;; ivg++) {
1234 if (ivg >= ivg_stop) {
1235 atomic_inc(&num_spurious);
1236 return 0;
1237 }
1238 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1239 break;
1240 }
1241 #else
1242 unsigned long sic_status;
1243
1244 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1245
1246 for (;; ivg++) {
1247 if (ivg >= ivg_stop) {
1248 atomic_inc(&num_spurious);
1249 return 0;
1250 } else if (sic_status & ivg->isrflag)
1251 break;
1252 }
1253 #endif
1254 irq = ivg->irqno;
1255 }
1256
1257 if (irq == IRQ_SYSTMR) {
1258 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1259 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1260 #endif
1261 /* This is basically what we need from the register frame. */
1262 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1263 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1264 if (this_domain != ipipe_root_domain)
1265 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1266 else
1267 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1268 }
1269
1270 if (this_domain == ipipe_root_domain) {
1271 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1272 barrier();
1273 }
1274
1275 ipipe_trace_irq_entry(irq);
1276 __ipipe_handle_irq(irq, regs);
1277 ipipe_trace_irq_exit(irq);
1278
1279 if (this_domain == ipipe_root_domain) {
1280 set_thread_flag(TIF_IRQ_SYNC);
1281 if (!s) {
1282 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1283 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1284 }
1285 }
1286
1287 return 0;
1288 }
1289
1290 #endif /* CONFIG_IPIPE */
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