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sysfs: sysfs_sd_setattr set iattrs unconditionally
[linux-2.6/linux-2.6-openrd.git] / drivers / dma / ipu / ipu_idmac.c
blobe80bae1673fa910f2a774fb455b28f4f61b05075
1 /*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/err.h>
15 #include <linux/spinlock.h>
16 #include <linux/delay.h>
17 #include <linux/list.h>
18 #include <linux/clk.h>
19 #include <linux/vmalloc.h>
20 #include <linux/string.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23
24 #include <mach/ipu.h>
25
26 #include "ipu_intern.h"
27
28 #define FS_VF_IN_VALID 0x00000002
29 #define FS_ENC_IN_VALID 0x00000001
30
31 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
32 bool wait_for_stop);
33
34 /*
35 * There can be only one, we could allocate it dynamically, but then we'd have
36 * to add an extra parameter to some functions, and use something as ugly as
37 * struct ipu *ipu = to_ipu(to_idmac(ichan->dma_chan.device));
38 * in the ISR
39 */
40 static struct ipu ipu_data;
41
42 #define to_ipu(id) container_of(id, struct ipu, idmac)
43
44 static u32 __idmac_read_icreg(struct ipu *ipu, unsigned long reg)
45 {
46 return __raw_readl(ipu->reg_ic + reg);
47 }
48
49 #define idmac_read_icreg(ipu, reg) __idmac_read_icreg(ipu, reg - IC_CONF)
50
51 static void __idmac_write_icreg(struct ipu *ipu, u32 value, unsigned long reg)
52 {
53 __raw_writel(value, ipu->reg_ic + reg);
54 }
55
56 #define idmac_write_icreg(ipu, v, reg) __idmac_write_icreg(ipu, v, reg - IC_CONF)
57
58 static u32 idmac_read_ipureg(struct ipu *ipu, unsigned long reg)
59 {
60 return __raw_readl(ipu->reg_ipu + reg);
61 }
62
63 static void idmac_write_ipureg(struct ipu *ipu, u32 value, unsigned long reg)
64 {
65 __raw_writel(value, ipu->reg_ipu + reg);
66 }
67
68 /*****************************************************************************
69 * IPU / IC common functions
70 */
71 static void dump_idmac_reg(struct ipu *ipu)
72 {
73 dev_dbg(ipu->dev, "IDMAC_CONF 0x%x, IC_CONF 0x%x, IDMAC_CHA_EN 0x%x, "
74 "IDMAC_CHA_PRI 0x%x, IDMAC_CHA_BUSY 0x%x\n",
75 idmac_read_icreg(ipu, IDMAC_CONF),
76 idmac_read_icreg(ipu, IC_CONF),
77 idmac_read_icreg(ipu, IDMAC_CHA_EN),
78 idmac_read_icreg(ipu, IDMAC_CHA_PRI),
79 idmac_read_icreg(ipu, IDMAC_CHA_BUSY));
80 dev_dbg(ipu->dev, "BUF0_RDY 0x%x, BUF1_RDY 0x%x, CUR_BUF 0x%x, "
81 "DB_MODE 0x%x, TASKS_STAT 0x%x\n",
82 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
83 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
84 idmac_read_ipureg(ipu, IPU_CHA_CUR_BUF),
85 idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL),
86 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
87 }
88
89 static uint32_t bytes_per_pixel(enum pixel_fmt fmt)
90 {
91 switch (fmt) {
92 case IPU_PIX_FMT_GENERIC: /* generic data */
93 case IPU_PIX_FMT_RGB332:
94 case IPU_PIX_FMT_YUV420P:
95 case IPU_PIX_FMT_YUV422P:
96 default:
97 return 1;
98 case IPU_PIX_FMT_RGB565:
99 case IPU_PIX_FMT_YUYV:
100 case IPU_PIX_FMT_UYVY:
101 return 2;
102 case IPU_PIX_FMT_BGR24:
103 case IPU_PIX_FMT_RGB24:
104 return 3;
105 case IPU_PIX_FMT_GENERIC_32: /* generic data */
106 case IPU_PIX_FMT_BGR32:
107 case IPU_PIX_FMT_RGB32:
108 case IPU_PIX_FMT_ABGR32:
109 return 4;
110 }
111 }
112
113 /* Enable direct write to memory by the Camera Sensor Interface */
114 static void ipu_ic_enable_task(struct ipu *ipu, enum ipu_channel channel)
115 {
116 uint32_t ic_conf, mask;
117
118 switch (channel) {
119 case IDMAC_IC_0:
120 mask = IC_CONF_PRPENC_EN;
121 break;
122 case IDMAC_IC_7:
123 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
124 break;
125 default:
126 return;
127 }
128 ic_conf = idmac_read_icreg(ipu, IC_CONF) | mask;
129 idmac_write_icreg(ipu, ic_conf, IC_CONF);
130 }
131
132 /* Called under spin_lock_irqsave(&ipu_data.lock) */
133 static void ipu_ic_disable_task(struct ipu *ipu, enum ipu_channel channel)
134 {
135 uint32_t ic_conf, mask;
136
137 switch (channel) {
138 case IDMAC_IC_0:
139 mask = IC_CONF_PRPENC_EN;
140 break;
141 case IDMAC_IC_7:
142 mask = IC_CONF_RWS_EN | IC_CONF_PRPENC_EN;
143 break;
144 default:
145 return;
146 }
147 ic_conf = idmac_read_icreg(ipu, IC_CONF) & ~mask;
148 idmac_write_icreg(ipu, ic_conf, IC_CONF);
149 }
150
151 static uint32_t ipu_channel_status(struct ipu *ipu, enum ipu_channel channel)
152 {
153 uint32_t stat = TASK_STAT_IDLE;
154 uint32_t task_stat_reg = idmac_read_ipureg(ipu, IPU_TASKS_STAT);
155
156 switch (channel) {
157 case IDMAC_IC_7:
158 stat = (task_stat_reg & TSTAT_CSI2MEM_MASK) >>
159 TSTAT_CSI2MEM_OFFSET;
160 break;
161 case IDMAC_IC_0:
162 case IDMAC_SDC_0:
163 case IDMAC_SDC_1:
164 default:
165 break;
166 }
167 return stat;
168 }
169
170 struct chan_param_mem_planar {
171 /* Word 0 */
172 u32 xv:10;
173 u32 yv:10;
174 u32 xb:12;
175
176 u32 yb:12;
177 u32 res1:2;
178 u32 nsb:1;
179 u32 lnpb:6;
180 u32 ubo_l:11;
181
182 u32 ubo_h:15;
183 u32 vbo_l:17;
184
185 u32 vbo_h:9;
186 u32 res2:3;
187 u32 fw:12;
188 u32 fh_l:8;
189
190 u32 fh_h:4;
191 u32 res3:28;
192
193 /* Word 1 */
194 u32 eba0;
195
196 u32 eba1;
197
198 u32 bpp:3;
199 u32 sl:14;
200 u32 pfs:3;
201 u32 bam:3;
202 u32 res4:2;
203 u32 npb:6;
204 u32 res5:1;
205
206 u32 sat:2;
207 u32 res6:30;
208 } __attribute__ ((packed));
209
210 struct chan_param_mem_interleaved {
211 /* Word 0 */
212 u32 xv:10;
213 u32 yv:10;
214 u32 xb:12;
215
216 u32 yb:12;
217 u32 sce:1;
218 u32 res1:1;
219 u32 nsb:1;
220 u32 lnpb:6;
221 u32 sx:10;
222 u32 sy_l:1;
223
224 u32 sy_h:9;
225 u32 ns:10;
226 u32 sm:10;
227 u32 sdx_l:3;
228
229 u32 sdx_h:2;
230 u32 sdy:5;
231 u32 sdrx:1;
232 u32 sdry:1;
233 u32 sdr1:1;
234 u32 res2:2;
235 u32 fw:12;
236 u32 fh_l:8;
237
238 u32 fh_h:4;
239 u32 res3:28;
240
241 /* Word 1 */
242 u32 eba0;
243
244 u32 eba1;
245
246 u32 bpp:3;
247 u32 sl:14;
248 u32 pfs:3;
249 u32 bam:3;
250 u32 res4:2;
251 u32 npb:6;
252 u32 res5:1;
253
254 u32 sat:2;
255 u32 scc:1;
256 u32 ofs0:5;
257 u32 ofs1:5;
258 u32 ofs2:5;
259 u32 ofs3:5;
260 u32 wid0:3;
261 u32 wid1:3;
262 u32 wid2:3;
263
264 u32 wid3:3;
265 u32 dec_sel:1;
266 u32 res6:28;
267 } __attribute__ ((packed));
268
269 union chan_param_mem {
270 struct chan_param_mem_planar pp;
271 struct chan_param_mem_interleaved ip;
272 };
273
274 static void ipu_ch_param_set_plane_offset(union chan_param_mem *params,
275 u32 u_offset, u32 v_offset)
276 {
277 params->pp.ubo_l = u_offset & 0x7ff;
278 params->pp.ubo_h = u_offset >> 11;
279 params->pp.vbo_l = v_offset & 0x1ffff;
280 params->pp.vbo_h = v_offset >> 17;
281 }
282
283 static void ipu_ch_param_set_size(union chan_param_mem *params,
284 uint32_t pixel_fmt, uint16_t width,
285 uint16_t height, uint16_t stride)
286 {
287 u32 u_offset;
288 u32 v_offset;
289
290 params->pp.fw = width - 1;
291 params->pp.fh_l = height - 1;
292 params->pp.fh_h = (height - 1) >> 8;
293 params->pp.sl = stride - 1;
294
295 switch (pixel_fmt) {
296 case IPU_PIX_FMT_GENERIC:
297 /*Represents 8-bit Generic data */
298 params->pp.bpp = 3;
299 params->pp.pfs = 7;
300 params->pp.npb = 31;
301 params->pp.sat = 2; /* SAT = use 32-bit access */
302 break;
303 case IPU_PIX_FMT_GENERIC_32:
304 /*Represents 32-bit Generic data */
305 params->pp.bpp = 0;
306 params->pp.pfs = 7;
307 params->pp.npb = 7;
308 params->pp.sat = 2; /* SAT = use 32-bit access */
309 break;
310 case IPU_PIX_FMT_RGB565:
311 params->ip.bpp = 2;
312 params->ip.pfs = 4;
313 params->ip.npb = 7;
314 params->ip.sat = 2; /* SAT = 32-bit access */
315 params->ip.ofs0 = 0; /* Red bit offset */
316 params->ip.ofs1 = 5; /* Green bit offset */
317 params->ip.ofs2 = 11; /* Blue bit offset */
318 params->ip.ofs3 = 16; /* Alpha bit offset */
319 params->ip.wid0 = 4; /* Red bit width - 1 */
320 params->ip.wid1 = 5; /* Green bit width - 1 */
321 params->ip.wid2 = 4; /* Blue bit width - 1 */
322 break;
323 case IPU_PIX_FMT_BGR24:
324 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
325 params->ip.pfs = 4;
326 params->ip.npb = 7;
327 params->ip.sat = 2; /* SAT = 32-bit access */
328 params->ip.ofs0 = 0; /* Red bit offset */
329 params->ip.ofs1 = 8; /* Green bit offset */
330 params->ip.ofs2 = 16; /* Blue bit offset */
331 params->ip.ofs3 = 24; /* Alpha bit offset */
332 params->ip.wid0 = 7; /* Red bit width - 1 */
333 params->ip.wid1 = 7; /* Green bit width - 1 */
334 params->ip.wid2 = 7; /* Blue bit width - 1 */
335 break;
336 case IPU_PIX_FMT_RGB24:
337 params->ip.bpp = 1; /* 24 BPP & RGB PFS */
338 params->ip.pfs = 4;
339 params->ip.npb = 7;
340 params->ip.sat = 2; /* SAT = 32-bit access */
341 params->ip.ofs0 = 16; /* Red bit offset */
342 params->ip.ofs1 = 8; /* Green bit offset */
343 params->ip.ofs2 = 0; /* Blue bit offset */
344 params->ip.ofs3 = 24; /* Alpha bit offset */
345 params->ip.wid0 = 7; /* Red bit width - 1 */
346 params->ip.wid1 = 7; /* Green bit width - 1 */
347 params->ip.wid2 = 7; /* Blue bit width - 1 */
348 break;
349 case IPU_PIX_FMT_BGRA32:
350 case IPU_PIX_FMT_BGR32:
351 params->ip.bpp = 0;
352 params->ip.pfs = 4;
353 params->ip.npb = 7;
354 params->ip.sat = 2; /* SAT = 32-bit access */
355 params->ip.ofs0 = 8; /* Red bit offset */
356 params->ip.ofs1 = 16; /* Green bit offset */
357 params->ip.ofs2 = 24; /* Blue bit offset */
358 params->ip.ofs3 = 0; /* Alpha bit offset */
359 params->ip.wid0 = 7; /* Red bit width - 1 */
360 params->ip.wid1 = 7; /* Green bit width - 1 */
361 params->ip.wid2 = 7; /* Blue bit width - 1 */
362 params->ip.wid3 = 7; /* Alpha bit width - 1 */
363 break;
364 case IPU_PIX_FMT_RGBA32:
365 case IPU_PIX_FMT_RGB32:
366 params->ip.bpp = 0;
367 params->ip.pfs = 4;
368 params->ip.npb = 7;
369 params->ip.sat = 2; /* SAT = 32-bit access */
370 params->ip.ofs0 = 24; /* Red bit offset */
371 params->ip.ofs1 = 16; /* Green bit offset */
372 params->ip.ofs2 = 8; /* Blue bit offset */
373 params->ip.ofs3 = 0; /* Alpha bit offset */
374 params->ip.wid0 = 7; /* Red bit width - 1 */
375 params->ip.wid1 = 7; /* Green bit width - 1 */
376 params->ip.wid2 = 7; /* Blue bit width - 1 */
377 params->ip.wid3 = 7; /* Alpha bit width - 1 */
378 break;
379 case IPU_PIX_FMT_ABGR32:
380 params->ip.bpp = 0;
381 params->ip.pfs = 4;
382 params->ip.npb = 7;
383 params->ip.sat = 2; /* SAT = 32-bit access */
384 params->ip.ofs0 = 8; /* Red bit offset */
385 params->ip.ofs1 = 16; /* Green bit offset */
386 params->ip.ofs2 = 24; /* Blue bit offset */
387 params->ip.ofs3 = 0; /* Alpha bit offset */
388 params->ip.wid0 = 7; /* Red bit width - 1 */
389 params->ip.wid1 = 7; /* Green bit width - 1 */
390 params->ip.wid2 = 7; /* Blue bit width - 1 */
391 params->ip.wid3 = 7; /* Alpha bit width - 1 */
392 break;
393 case IPU_PIX_FMT_UYVY:
394 params->ip.bpp = 2;
395 params->ip.pfs = 6;
396 params->ip.npb = 7;
397 params->ip.sat = 2; /* SAT = 32-bit access */
398 break;
399 case IPU_PIX_FMT_YUV420P2:
400 case IPU_PIX_FMT_YUV420P:
401 params->ip.bpp = 3;
402 params->ip.pfs = 3;
403 params->ip.npb = 7;
404 params->ip.sat = 2; /* SAT = 32-bit access */
405 u_offset = stride * height;
406 v_offset = u_offset + u_offset / 4;
407 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
408 break;
409 case IPU_PIX_FMT_YVU422P:
410 params->ip.bpp = 3;
411 params->ip.pfs = 2;
412 params->ip.npb = 7;
413 params->ip.sat = 2; /* SAT = 32-bit access */
414 v_offset = stride * height;
415 u_offset = v_offset + v_offset / 2;
416 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
417 break;
418 case IPU_PIX_FMT_YUV422P:
419 params->ip.bpp = 3;
420 params->ip.pfs = 2;
421 params->ip.npb = 7;
422 params->ip.sat = 2; /* SAT = 32-bit access */
423 u_offset = stride * height;
424 v_offset = u_offset + u_offset / 2;
425 ipu_ch_param_set_plane_offset(params, u_offset, v_offset);
426 break;
427 default:
428 dev_err(ipu_data.dev,
429 "mx3 ipu: unimplemented pixel format %d\n", pixel_fmt);
430 break;
431 }
432
433 params->pp.nsb = 1;
434 }
435
436 static void ipu_ch_param_set_burst_size(union chan_param_mem *params,
437 uint16_t burst_pixels)
438 {
439 params->pp.npb = burst_pixels - 1;
440 }
441
442 static void ipu_ch_param_set_buffer(union chan_param_mem *params,
443 dma_addr_t buf0, dma_addr_t buf1)
444 {
445 params->pp.eba0 = buf0;
446 params->pp.eba1 = buf1;
447 }
448
449 static void ipu_ch_param_set_rotation(union chan_param_mem *params,
450 enum ipu_rotate_mode rotate)
451 {
452 params->pp.bam = rotate;
453 }
454
455 static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
456 uint32_t num_words)
457 {
458 for (; num_words > 0; num_words--) {
459 dev_dbg(ipu_data.dev,
460 "write param mem - addr = 0x%08X, data = 0x%08X\n",
461 addr, *data);
462 idmac_write_ipureg(&ipu_data, addr, IPU_IMA_ADDR);
463 idmac_write_ipureg(&ipu_data, *data++, IPU_IMA_DATA);
464 addr++;
465 if ((addr & 0x7) == 5) {
466 addr &= ~0x7; /* set to word 0 */
467 addr += 8; /* increment to next row */
468 }
469 }
470 }
471
472 static int calc_resize_coeffs(uint32_t in_size, uint32_t out_size,
473 uint32_t *resize_coeff,
474 uint32_t *downsize_coeff)
475 {
476 uint32_t temp_size;
477 uint32_t temp_downsize;
478
479 *resize_coeff = 1 << 13;
480 *downsize_coeff = 1 << 13;
481
482 /* Cannot downsize more than 8:1 */
483 if (out_size << 3 < in_size)
484 return -EINVAL;
485
486 /* compute downsizing coefficient */
487 temp_downsize = 0;
488 temp_size = in_size;
489 while (temp_size >= out_size * 2 && temp_downsize < 2) {
490 temp_size >>= 1;
491 temp_downsize++;
492 }
493 *downsize_coeff = temp_downsize;
494
495 /*
496 * compute resizing coefficient using the following formula:
497 * resize_coeff = M*(SI -1)/(SO - 1)
498 * where M = 2^13, SI - input size, SO - output size
499 */
500 *resize_coeff = (8192L * (temp_size - 1)) / (out_size - 1);
501 if (*resize_coeff >= 16384L) {
502 dev_err(ipu_data.dev, "Warning! Overflow on resize coeff.\n");
503 *resize_coeff = 0x3FFF;
504 }
505
506 dev_dbg(ipu_data.dev, "resizing from %u -> %u pixels, "
507 "downsize=%u, resize=%u.%lu (reg=%u)\n", in_size, out_size,
508 *downsize_coeff, *resize_coeff >= 8192L ? 1 : 0,
509 ((*resize_coeff & 0x1FFF) * 10000L) / 8192L, *resize_coeff);
510
511 return 0;
512 }
513
514 static enum ipu_color_space format_to_colorspace(enum pixel_fmt fmt)
515 {
516 switch (fmt) {
517 case IPU_PIX_FMT_RGB565:
518 case IPU_PIX_FMT_BGR24:
519 case IPU_PIX_FMT_RGB24:
520 case IPU_PIX_FMT_BGR32:
521 case IPU_PIX_FMT_RGB32:
522 return IPU_COLORSPACE_RGB;
523 default:
524 return IPU_COLORSPACE_YCBCR;
525 }
526 }
527
528 static int ipu_ic_init_prpenc(struct ipu *ipu,
529 union ipu_channel_param *params, bool src_is_csi)
530 {
531 uint32_t reg, ic_conf;
532 uint32_t downsize_coeff, resize_coeff;
533 enum ipu_color_space in_fmt, out_fmt;
534
535 /* Setup vertical resizing */
536 calc_resize_coeffs(params->video.in_height,
537 params->video.out_height,
538 &resize_coeff, &downsize_coeff);
539 reg = (downsize_coeff << 30) | (resize_coeff << 16);
540
541 /* Setup horizontal resizing */
542 calc_resize_coeffs(params->video.in_width,
543 params->video.out_width,
544 &resize_coeff, &downsize_coeff);
545 reg |= (downsize_coeff << 14) | resize_coeff;
546
547 /* Setup color space conversion */
548 in_fmt = format_to_colorspace(params->video.in_pixel_fmt);
549 out_fmt = format_to_colorspace(params->video.out_pixel_fmt);
550
551 /*
552 * Colourspace conversion unsupported yet - see _init_csc() in
553 * Freescale sources
554 */
555 if (in_fmt != out_fmt) {
556 dev_err(ipu->dev, "Colourspace conversion unsupported!\n");
557 return -EOPNOTSUPP;
558 }
559
560 idmac_write_icreg(ipu, reg, IC_PRP_ENC_RSC);
561
562 ic_conf = idmac_read_icreg(ipu, IC_CONF);
563
564 if (src_is_csi)
565 ic_conf &= ~IC_CONF_RWS_EN;
566 else
567 ic_conf |= IC_CONF_RWS_EN;
568
569 idmac_write_icreg(ipu, ic_conf, IC_CONF);
570
571 return 0;
572 }
573
574 static uint32_t dma_param_addr(uint32_t dma_ch)
575 {
576 /* Channel Parameter Memory */
577 return 0x10000 | (dma_ch << 4);
578 }
579
580 static void ipu_channel_set_priority(struct ipu *ipu, enum ipu_channel channel,
581 bool prio)
582 {
583 u32 reg = idmac_read_icreg(ipu, IDMAC_CHA_PRI);
584
585 if (prio)
586 reg |= 1UL << channel;
587 else
588 reg &= ~(1UL << channel);
589
590 idmac_write_icreg(ipu, reg, IDMAC_CHA_PRI);
591
592 dump_idmac_reg(ipu);
593 }
594
595 static uint32_t ipu_channel_conf_mask(enum ipu_channel channel)
596 {
597 uint32_t mask;
598
599 switch (channel) {
600 case IDMAC_IC_0:
601 case IDMAC_IC_7:
602 mask = IPU_CONF_CSI_EN | IPU_CONF_IC_EN;
603 break;
604 case IDMAC_SDC_0:
605 case IDMAC_SDC_1:
606 mask = IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
607 break;
608 default:
609 mask = 0;
610 break;
611 }
612
613 return mask;
614 }
615
616 /**
617 * ipu_enable_channel() - enable an IPU channel.
618 * @idmac: IPU DMAC context.
619 * @ichan: IDMAC channel.
620 * @return: 0 on success or negative error code on failure.
621 */
622 static int ipu_enable_channel(struct idmac *idmac, struct idmac_channel *ichan)
623 {
624 struct ipu *ipu = to_ipu(idmac);
625 enum ipu_channel channel = ichan->dma_chan.chan_id;
626 uint32_t reg;
627 unsigned long flags;
628
629 spin_lock_irqsave(&ipu->lock, flags);
630
631 /* Reset to buffer 0 */
632 idmac_write_ipureg(ipu, 1UL << channel, IPU_CHA_CUR_BUF);
633 ichan->active_buffer = 0;
634 ichan->status = IPU_CHANNEL_ENABLED;
635
636 switch (channel) {
637 case IDMAC_SDC_0:
638 case IDMAC_SDC_1:
639 case IDMAC_IC_7:
640 ipu_channel_set_priority(ipu, channel, true);
641 default:
642 break;
643 }
644
645 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
646
647 idmac_write_icreg(ipu, reg | (1UL << channel), IDMAC_CHA_EN);
648
649 ipu_ic_enable_task(ipu, channel);
650
651 spin_unlock_irqrestore(&ipu->lock, flags);
652 return 0;
653 }
654
655 /**
656 * ipu_init_channel_buffer() - initialize a buffer for logical IPU channel.
657 * @ichan: IDMAC channel.
658 * @pixel_fmt: pixel format of buffer. Pixel format is a FOURCC ASCII code.
659 * @width: width of buffer in pixels.
660 * @height: height of buffer in pixels.
661 * @stride: stride length of buffer in pixels.
662 * @rot_mode: rotation mode of buffer. A rotation setting other than
663 * IPU_ROTATE_VERT_FLIP should only be used for input buffers of
664 * rotation channels.
665 * @phyaddr_0: buffer 0 physical address.
666 * @phyaddr_1: buffer 1 physical address. Setting this to a value other than
667 * NULL enables double buffering mode.
668 * @return: 0 on success or negative error code on failure.
669 */
670 static int ipu_init_channel_buffer(struct idmac_channel *ichan,
671 enum pixel_fmt pixel_fmt,
672 uint16_t width, uint16_t height,
673 uint32_t stride,
674 enum ipu_rotate_mode rot_mode,
675 dma_addr_t phyaddr_0, dma_addr_t phyaddr_1)
676 {
677 enum ipu_channel channel = ichan->dma_chan.chan_id;
678 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
679 struct ipu *ipu = to_ipu(idmac);
680 union chan_param_mem params = {};
681 unsigned long flags;
682 uint32_t reg;
683 uint32_t stride_bytes;
684
685 stride_bytes = stride * bytes_per_pixel(pixel_fmt);
686
687 if (stride_bytes % 4) {
688 dev_err(ipu->dev,
689 "Stride length must be 32-bit aligned, stride = %d, bytes = %d\n",
690 stride, stride_bytes);
691 return -EINVAL;
692 }
693
694 /* IC channel's stride must be a multiple of 8 pixels */
695 if ((channel <= IDMAC_IC_13) && (stride % 8)) {
696 dev_err(ipu->dev, "Stride must be 8 pixel multiple\n");
697 return -EINVAL;
698 }
699
700 /* Build parameter memory data for DMA channel */
701 ipu_ch_param_set_size(&params, pixel_fmt, width, height, stride_bytes);
702 ipu_ch_param_set_buffer(&params, phyaddr_0, phyaddr_1);
703 ipu_ch_param_set_rotation(&params, rot_mode);
704 /* Some channels (rotation) have restriction on burst length */
705 switch (channel) {
706 case IDMAC_IC_7: /* Hangs with burst 8, 16, other values
707 invalid - Table 44-30 */
708 /*
709 ipu_ch_param_set_burst_size(&params, 8);
710 */
711 break;
712 case IDMAC_SDC_0:
713 case IDMAC_SDC_1:
714 /* In original code only IPU_PIX_FMT_RGB565 was setting burst */
715 ipu_ch_param_set_burst_size(&params, 16);
716 break;
717 case IDMAC_IC_0:
718 default:
719 break;
720 }
721
722 spin_lock_irqsave(&ipu->lock, flags);
723
724 ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
725
726 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
727
728 if (phyaddr_1)
729 reg |= 1UL << channel;
730 else
731 reg &= ~(1UL << channel);
732
733 idmac_write_ipureg(ipu, reg, IPU_CHA_DB_MODE_SEL);
734
735 ichan->status = IPU_CHANNEL_READY;
736
737 spin_unlock_irqrestore(&ipu->lock, flags);
738
739 return 0;
740 }
741
742 /**
743 * ipu_select_buffer() - mark a channel's buffer as ready.
744 * @channel: channel ID.
745 * @buffer_n: buffer number to mark ready.
746 */
747 static void ipu_select_buffer(enum ipu_channel channel, int buffer_n)
748 {
749 /* No locking - this is a write-one-to-set register, cleared by IPU */
750 if (buffer_n == 0)
751 /* Mark buffer 0 as ready. */
752 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF0_RDY);
753 else
754 /* Mark buffer 1 as ready. */
755 idmac_write_ipureg(&ipu_data, 1UL << channel, IPU_CHA_BUF1_RDY);
756 }
757
758 /**
759 * ipu_update_channel_buffer() - update physical address of a channel buffer.
760 * @ichan: IDMAC channel.
761 * @buffer_n: buffer number to update.
762 * 0 or 1 are the only valid values.
763 * @phyaddr: buffer physical address.
764 */
765 /* Called under spin_lock(_irqsave)(&ichan->lock) */
766 static void ipu_update_channel_buffer(struct idmac_channel *ichan,
767 int buffer_n, dma_addr_t phyaddr)
768 {
769 enum ipu_channel channel = ichan->dma_chan.chan_id;
770 uint32_t reg;
771 unsigned long flags;
772
773 spin_lock_irqsave(&ipu_data.lock, flags);
774
775 if (buffer_n == 0) {
776 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
777 if (reg & (1UL << channel)) {
778 ipu_ic_disable_task(&ipu_data, channel);
779 ichan->status = IPU_CHANNEL_READY;
780 }
781
782 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
783 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
784 0x0008UL, IPU_IMA_ADDR);
785 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
786 } else {
787 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
788 if (reg & (1UL << channel)) {
789 ipu_ic_disable_task(&ipu_data, channel);
790 ichan->status = IPU_CHANNEL_READY;
791 }
792
793 /* Check if double-buffering is already enabled */
794 reg = idmac_read_ipureg(&ipu_data, IPU_CHA_DB_MODE_SEL);
795
796 if (!(reg & (1UL << channel)))
797 idmac_write_ipureg(&ipu_data, reg | (1UL << channel),
798 IPU_CHA_DB_MODE_SEL);
799
800 /* 44.3.3.1.9 - Row Number 1 (WORD1, offset 1) */
801 idmac_write_ipureg(&ipu_data, dma_param_addr(channel) +
802 0x0009UL, IPU_IMA_ADDR);
803 idmac_write_ipureg(&ipu_data, phyaddr, IPU_IMA_DATA);
804 }
805
806 spin_unlock_irqrestore(&ipu_data.lock, flags);
807 }
808
809 /* Called under spin_lock_irqsave(&ichan->lock) */
810 static int ipu_submit_buffer(struct idmac_channel *ichan,
811 struct idmac_tx_desc *desc, struct scatterlist *sg, int buf_idx)
812 {
813 unsigned int chan_id = ichan->dma_chan.chan_id;
814 struct device *dev = &ichan->dma_chan.dev->device;
815
816 if (async_tx_test_ack(&desc->txd))
817 return -EINTR;
818
819 /*
820 * On first invocation this shouldn't be necessary, the call to
821 * ipu_init_channel_buffer() above will set addresses for us, so we
822 * could make it conditional on status >= IPU_CHANNEL_ENABLED, but
823 * doing it again shouldn't hurt either.
824 */
825 ipu_update_channel_buffer(ichan, buf_idx, sg_dma_address(sg));
826
827 ipu_select_buffer(chan_id, buf_idx);
828 dev_dbg(dev, "Updated sg %p on channel 0x%x buffer %d\n",
829 sg, chan_id, buf_idx);
830
831 return 0;
832 }
833
834 /* Called under spin_lock_irqsave(&ichan->lock) */
835 static int ipu_submit_channel_buffers(struct idmac_channel *ichan,
836 struct idmac_tx_desc *desc)
837 {
838 struct scatterlist *sg;
839 int i, ret = 0;
840
841 for (i = 0, sg = desc->sg; i < 2 && sg; i++) {
842 if (!ichan->sg[i]) {
843 ichan->sg[i] = sg;
844
845 ret = ipu_submit_buffer(ichan, desc, sg, i);
846 if (ret < 0)
847 return ret;
848
849 sg = sg_next(sg);
850 }
851 }
852
853 return ret;
854 }
855
856 static dma_cookie_t idmac_tx_submit(struct dma_async_tx_descriptor *tx)
857 {
858 struct idmac_tx_desc *desc = to_tx_desc(tx);
859 struct idmac_channel *ichan = to_idmac_chan(tx->chan);
860 struct idmac *idmac = to_idmac(tx->chan->device);
861 struct ipu *ipu = to_ipu(idmac);
862 struct device *dev = &ichan->dma_chan.dev->device;
863 dma_cookie_t cookie;
864 unsigned long flags;
865 int ret;
866
867 /* Sanity check */
868 if (!list_empty(&desc->list)) {
869 /* The descriptor doesn't belong to client */
870 dev_err(dev, "Descriptor %p not prepared!\n", tx);
871 return -EBUSY;
872 }
873
874 mutex_lock(&ichan->chan_mutex);
875
876 async_tx_clear_ack(tx);
877
878 if (ichan->status < IPU_CHANNEL_READY) {
879 struct idmac_video_param *video = &ichan->params.video;
880 /*
881 * Initial buffer assignment - the first two sg-entries from
882 * the descriptor will end up in the IDMAC buffers
883 */
884 dma_addr_t dma_1 = sg_is_last(desc->sg) ? 0 :
885 sg_dma_address(&desc->sg[1]);
886
887 WARN_ON(ichan->sg[0] || ichan->sg[1]);
888
889 cookie = ipu_init_channel_buffer(ichan,
890 video->out_pixel_fmt,
891 video->out_width,
892 video->out_height,
893 video->out_stride,
894 IPU_ROTATE_NONE,
895 sg_dma_address(&desc->sg[0]),
896 dma_1);
897 if (cookie < 0)
898 goto out;
899 }
900
901 dev_dbg(dev, "Submitting sg %p\n", &desc->sg[0]);
902
903 cookie = ichan->dma_chan.cookie;
904
905 if (++cookie < 0)
906 cookie = 1;
907
908 /* from dmaengine.h: "last cookie value returned to client" */
909 ichan->dma_chan.cookie = cookie;
910 tx->cookie = cookie;
911
912 /* ipu->lock can be taken under ichan->lock, but not v.v. */
913 spin_lock_irqsave(&ichan->lock, flags);
914
915 list_add_tail(&desc->list, &ichan->queue);
916 /* submit_buffers() atomically verifies and fills empty sg slots */
917 ret = ipu_submit_channel_buffers(ichan, desc);
918
919 spin_unlock_irqrestore(&ichan->lock, flags);
920
921 if (ret < 0) {
922 cookie = ret;
923 goto dequeue;
924 }
925
926 if (ichan->status < IPU_CHANNEL_ENABLED) {
927 ret = ipu_enable_channel(idmac, ichan);
928 if (ret < 0) {
929 cookie = ret;
930 goto dequeue;
931 }
932 }
933
934 dump_idmac_reg(ipu);
935
936 dequeue:
937 if (cookie < 0) {
938 spin_lock_irqsave(&ichan->lock, flags);
939 list_del_init(&desc->list);
940 spin_unlock_irqrestore(&ichan->lock, flags);
941 tx->cookie = cookie;
942 ichan->dma_chan.cookie = cookie;
943 }
944
945 out:
946 mutex_unlock(&ichan->chan_mutex);
947
948 return cookie;
949 }
950
951 /* Called with ichan->chan_mutex held */
952 static int idmac_desc_alloc(struct idmac_channel *ichan, int n)
953 {
954 struct idmac_tx_desc *desc = vmalloc(n * sizeof(struct idmac_tx_desc));
955 struct idmac *idmac = to_idmac(ichan->dma_chan.device);
956
957 if (!desc)
958 return -ENOMEM;
959
960 /* No interrupts, just disable the tasklet for a moment */
961 tasklet_disable(&to_ipu(idmac)->tasklet);
962
963 ichan->n_tx_desc = n;
964 ichan->desc = desc;
965 INIT_LIST_HEAD(&ichan->queue);
966 INIT_LIST_HEAD(&ichan->free_list);
967
968 while (n--) {
969 struct dma_async_tx_descriptor *txd = &desc->txd;
970
971 memset(txd, 0, sizeof(*txd));
972 dma_async_tx_descriptor_init(txd, &ichan->dma_chan);
973 txd->tx_submit = idmac_tx_submit;
974
975 list_add(&desc->list, &ichan->free_list);
976
977 desc++;
978 }
979
980 tasklet_enable(&to_ipu(idmac)->tasklet);
981
982 return 0;
983 }
984
985 /**
986 * ipu_init_channel() - initialize an IPU channel.
987 * @idmac: IPU DMAC context.
988 * @ichan: pointer to the channel object.
989 * @return 0 on success or negative error code on failure.
990 */
991 static int ipu_init_channel(struct idmac *idmac, struct idmac_channel *ichan)
992 {
993 union ipu_channel_param *params = &ichan->params;
994 uint32_t ipu_conf;
995 enum ipu_channel channel = ichan->dma_chan.chan_id;
996 unsigned long flags;
997 uint32_t reg;
998 struct ipu *ipu = to_ipu(idmac);
999 int ret = 0, n_desc = 0;
1000
1001 dev_dbg(ipu->dev, "init channel = %d\n", channel);
1002
1003 if (channel != IDMAC_SDC_0 && channel != IDMAC_SDC_1 &&
1004 channel != IDMAC_IC_7)
1005 return -EINVAL;
1006
1007 spin_lock_irqsave(&ipu->lock, flags);
1008
1009 switch (channel) {
1010 case IDMAC_IC_7:
1011 n_desc = 16;
1012 reg = idmac_read_icreg(ipu, IC_CONF);
1013 idmac_write_icreg(ipu, reg & ~IC_CONF_CSI_MEM_WR_EN, IC_CONF);
1014 break;
1015 case IDMAC_IC_0:
1016 n_desc = 16;
1017 reg = idmac_read_ipureg(ipu, IPU_FS_PROC_FLOW);
1018 idmac_write_ipureg(ipu, reg & ~FS_ENC_IN_VALID, IPU_FS_PROC_FLOW);
1019 ret = ipu_ic_init_prpenc(ipu, params, true);
1020 break;
1021 case IDMAC_SDC_0:
1022 case IDMAC_SDC_1:
1023 n_desc = 4;
1024 default:
1025 break;
1026 }
1027
1028 ipu->channel_init_mask |= 1L << channel;
1029
1030 /* Enable IPU sub module */
1031 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) |
1032 ipu_channel_conf_mask(channel);
1033 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1034
1035 spin_unlock_irqrestore(&ipu->lock, flags);
1036
1037 if (n_desc && !ichan->desc)
1038 ret = idmac_desc_alloc(ichan, n_desc);
1039
1040 dump_idmac_reg(ipu);
1041
1042 return ret;
1043 }
1044
1045 /**
1046 * ipu_uninit_channel() - uninitialize an IPU channel.
1047 * @idmac: IPU DMAC context.
1048 * @ichan: pointer to the channel object.
1049 */
1050 static void ipu_uninit_channel(struct idmac *idmac, struct idmac_channel *ichan)
1051 {
1052 enum ipu_channel channel = ichan->dma_chan.chan_id;
1053 unsigned long flags;
1054 uint32_t reg;
1055 unsigned long chan_mask = 1UL << channel;
1056 uint32_t ipu_conf;
1057 struct ipu *ipu = to_ipu(idmac);
1058
1059 spin_lock_irqsave(&ipu->lock, flags);
1060
1061 if (!(ipu->channel_init_mask & chan_mask)) {
1062 dev_err(ipu->dev, "Channel already uninitialized %d\n",
1063 channel);
1064 spin_unlock_irqrestore(&ipu->lock, flags);
1065 return;
1066 }
1067
1068 /* Reset the double buffer */
1069 reg = idmac_read_ipureg(ipu, IPU_CHA_DB_MODE_SEL);
1070 idmac_write_ipureg(ipu, reg & ~chan_mask, IPU_CHA_DB_MODE_SEL);
1071
1072 ichan->sec_chan_en = false;
1073
1074 switch (channel) {
1075 case IDMAC_IC_7:
1076 reg = idmac_read_icreg(ipu, IC_CONF);
1077 idmac_write_icreg(ipu, reg & ~(IC_CONF_RWS_EN | IC_CONF_PRPENC_EN),
1078 IC_CONF);
1079 break;
1080 case IDMAC_IC_0:
1081 reg = idmac_read_icreg(ipu, IC_CONF);
1082 idmac_write_icreg(ipu, reg & ~(IC_CONF_PRPENC_EN | IC_CONF_PRPENC_CSC1),
1083 IC_CONF);
1084 break;
1085 case IDMAC_SDC_0:
1086 case IDMAC_SDC_1:
1087 default:
1088 break;
1089 }
1090
1091 ipu->channel_init_mask &= ~(1L << channel);
1092
1093 ipu_conf = idmac_read_ipureg(ipu, IPU_CONF) &
1094 ~ipu_channel_conf_mask(channel);
1095 idmac_write_ipureg(ipu, ipu_conf, IPU_CONF);
1096
1097 spin_unlock_irqrestore(&ipu->lock, flags);
1098
1099 ichan->n_tx_desc = 0;
1100 vfree(ichan->desc);
1101 ichan->desc = NULL;
1102 }
1103
1104 /**
1105 * ipu_disable_channel() - disable an IPU channel.
1106 * @idmac: IPU DMAC context.
1107 * @ichan: channel object pointer.
1108 * @wait_for_stop: flag to set whether to wait for channel end of frame or
1109 * return immediately.
1110 * @return: 0 on success or negative error code on failure.
1111 */
1112 static int ipu_disable_channel(struct idmac *idmac, struct idmac_channel *ichan,
1113 bool wait_for_stop)
1114 {
1115 enum ipu_channel channel = ichan->dma_chan.chan_id;
1116 struct ipu *ipu = to_ipu(idmac);
1117 uint32_t reg;
1118 unsigned long flags;
1119 unsigned long chan_mask = 1UL << channel;
1120 unsigned int timeout;
1121
1122 if (wait_for_stop && channel != IDMAC_SDC_1 && channel != IDMAC_SDC_0) {
1123 timeout = 40;
1124 /* This waiting always fails. Related to spurious irq problem */
1125 while ((idmac_read_icreg(ipu, IDMAC_CHA_BUSY) & chan_mask) ||
1126 (ipu_channel_status(ipu, channel) == TASK_STAT_ACTIVE)) {
1127 timeout--;
1128 msleep(10);
1129
1130 if (!timeout) {
1131 dev_dbg(ipu->dev,
1132 "Warning: timeout waiting for channel %u to "
1133 "stop: buf0_rdy = 0x%08X, buf1_rdy = 0x%08X, "
1134 "busy = 0x%08X, tstat = 0x%08X\n", channel,
1135 idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY),
1136 idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY),
1137 idmac_read_icreg(ipu, IDMAC_CHA_BUSY),
1138 idmac_read_ipureg(ipu, IPU_TASKS_STAT));
1139 break;
1140 }
1141 }
1142 dev_dbg(ipu->dev, "timeout = %d * 10ms\n", 40 - timeout);
1143 }
1144 /* SDC BG and FG must be disabled before DMA is disabled */
1145 if (wait_for_stop && (channel == IDMAC_SDC_0 ||
1146 channel == IDMAC_SDC_1)) {
1147 for (timeout = 5;
1148 timeout && !ipu_irq_status(ichan->eof_irq); timeout--)
1149 msleep(5);
1150 }
1151
1152 spin_lock_irqsave(&ipu->lock, flags);
1153
1154 /* Disable IC task */
1155 ipu_ic_disable_task(ipu, channel);
1156
1157 /* Disable DMA channel(s) */
1158 reg = idmac_read_icreg(ipu, IDMAC_CHA_EN);
1159 idmac_write_icreg(ipu, reg & ~chan_mask, IDMAC_CHA_EN);
1160
1161 /*
1162 * Problem (observed with channel DMAIC_7): after enabling the channel
1163 * and initialising buffers, there comes an interrupt with current still
1164 * pointing at buffer 0, whereas it should use buffer 0 first and only
1165 * generate an interrupt when it is done, then current should already
1166 * point to buffer 1. This spurious interrupt also comes on channel
1167 * DMASDC_0. With DMAIC_7 normally, is we just leave the ISR after the
1168 * first interrupt, there comes the second with current correctly
1169 * pointing to buffer 1 this time. But sometimes this second interrupt
1170 * doesn't come and the channel hangs. Clearing BUFx_RDY when disabling
1171 * the channel seems to prevent the channel from hanging, but it doesn't
1172 * prevent the spurious interrupt. This might also be unsafe. Think
1173 * about the IDMAC controller trying to switch to a buffer, when we
1174 * clear the ready bit, and re-enable it a moment later.
1175 */
1176 reg = idmac_read_ipureg(ipu, IPU_CHA_BUF0_RDY);
1177 idmac_write_ipureg(ipu, 0, IPU_CHA_BUF0_RDY);
1178 idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF0_RDY);
1179
1180 reg = idmac_read_ipureg(ipu, IPU_CHA_BUF1_RDY);
1181 idmac_write_ipureg(ipu, 0, IPU_CHA_BUF1_RDY);
1182 idmac_write_ipureg(ipu, reg & ~(1UL << channel), IPU_CHA_BUF1_RDY);
1183
1184 spin_unlock_irqrestore(&ipu->lock, flags);
1185
1186 return 0;
1187 }
1188
1189 static struct scatterlist *idmac_sg_next(struct idmac_channel *ichan,
1190 struct idmac_tx_desc **desc, struct scatterlist *sg)
1191 {
1192 struct scatterlist *sgnew = sg ? sg_next(sg) : NULL;
1193
1194 if (sgnew)
1195 /* next sg-element in this list */
1196 return sgnew;
1197
1198 if ((*desc)->list.next == &ichan->queue)
1199 /* No more descriptors on the queue */
1200 return NULL;
1201
1202 /* Fetch next descriptor */
1203 *desc = list_entry((*desc)->list.next, struct idmac_tx_desc, list);
1204 return (*desc)->sg;
1205 }
1206
1207 /*
1208 * We have several possibilities here:
1209 * current BUF next BUF
1210 *
1211 * not last sg next not last sg
1212 * not last sg next last sg
1213 * last sg first sg from next descriptor
1214 * last sg NULL
1215 *
1216 * Besides, the descriptor queue might be empty or not. We process all these
1217 * cases carefully.
1218 */
1219 static irqreturn_t idmac_interrupt(int irq, void *dev_id)
1220 {
1221 struct idmac_channel *ichan = dev_id;
1222 struct device *dev = &ichan->dma_chan.dev->device;
1223 unsigned int chan_id = ichan->dma_chan.chan_id;
1224 struct scatterlist **sg, *sgnext, *sgnew = NULL;
1225 /* Next transfer descriptor */
1226 struct idmac_tx_desc *desc, *descnew;
1227 dma_async_tx_callback callback;
1228 void *callback_param;
1229 bool done = false;
1230 u32 ready0, ready1, curbuf, err;
1231 unsigned long flags;
1232
1233 /* IDMAC has cleared the respective BUFx_RDY bit, we manage the buffer */
1234
1235 dev_dbg(dev, "IDMAC irq %d, buf %d\n", irq, ichan->active_buffer);
1236
1237 spin_lock_irqsave(&ipu_data.lock, flags);
1238
1239 ready0 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF0_RDY);
1240 ready1 = idmac_read_ipureg(&ipu_data, IPU_CHA_BUF1_RDY);
1241 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1242 err = idmac_read_ipureg(&ipu_data, IPU_INT_STAT_4);
1243
1244 if (err & (1 << chan_id)) {
1245 idmac_write_ipureg(&ipu_data, 1 << chan_id, IPU_INT_STAT_4);
1246 spin_unlock_irqrestore(&ipu_data.lock, flags);
1247 /*
1248 * Doing this
1249 * ichan->sg[0] = ichan->sg[1] = NULL;
1250 * you can force channel re-enable on the next tx_submit(), but
1251 * this is dirty - think about descriptors with multiple
1252 * sg elements.
1253 */
1254 dev_warn(dev, "NFB4EOF on channel %d, ready %x, %x, cur %x\n",
1255 chan_id, ready0, ready1, curbuf);
1256 return IRQ_HANDLED;
1257 }
1258 spin_unlock_irqrestore(&ipu_data.lock, flags);
1259
1260 /* Other interrupts do not interfere with this channel */
1261 spin_lock(&ichan->lock);
1262 if (unlikely(chan_id != IDMAC_SDC_0 && chan_id != IDMAC_SDC_1 &&
1263 ((curbuf >> chan_id) & 1) == ichan->active_buffer &&
1264 !list_is_last(ichan->queue.next, &ichan->queue))) {
1265 int i = 100;
1266
1267 /* This doesn't help. See comment in ipu_disable_channel() */
1268 while (--i) {
1269 curbuf = idmac_read_ipureg(&ipu_data, IPU_CHA_CUR_BUF);
1270 if (((curbuf >> chan_id) & 1) != ichan->active_buffer)
1271 break;
1272 cpu_relax();
1273 }
1274
1275 if (!i) {
1276 spin_unlock(&ichan->lock);
1277 dev_dbg(dev,
1278 "IRQ on active buffer on channel %x, active "
1279 "%d, ready %x, %x, current %x!\n", chan_id,
1280 ichan->active_buffer, ready0, ready1, curbuf);
1281 return IRQ_NONE;
1282 } else
1283 dev_dbg(dev,
1284 "Buffer deactivated on channel %x, active "
1285 "%d, ready %x, %x, current %x, rest %d!\n", chan_id,
1286 ichan->active_buffer, ready0, ready1, curbuf, i);
1287 }
1288
1289 if (unlikely((ichan->active_buffer && (ready1 >> chan_id) & 1) ||
1290 (!ichan->active_buffer && (ready0 >> chan_id) & 1)
1291 )) {
1292 spin_unlock(&ichan->lock);
1293 dev_dbg(dev,
1294 "IRQ with active buffer still ready on channel %x, "
1295 "active %d, ready %x, %x!\n", chan_id,
1296 ichan->active_buffer, ready0, ready1);
1297 return IRQ_NONE;
1298 }
1299
1300 if (unlikely(list_empty(&ichan->queue))) {
1301 ichan->sg[ichan->active_buffer] = NULL;
1302 spin_unlock(&ichan->lock);
1303 dev_err(dev,
1304 "IRQ without queued buffers on channel %x, active %d, "
1305 "ready %x, %x!\n", chan_id,
1306 ichan->active_buffer, ready0, ready1);
1307 return IRQ_NONE;
1308 }
1309
1310 /*
1311 * active_buffer is a software flag, it shows which buffer we are
1312 * currently expecting back from the hardware, IDMAC should be
1313 * processing the other buffer already
1314 */
1315 sg = &ichan->sg[ichan->active_buffer];
1316 sgnext = ichan->sg[!ichan->active_buffer];
1317
1318 if (!*sg) {
1319 spin_unlock(&ichan->lock);
1320 return IRQ_HANDLED;
1321 }
1322
1323 desc = list_entry(ichan->queue.next, struct idmac_tx_desc, list);
1324 descnew = desc;
1325
1326 dev_dbg(dev, "IDMAC irq %d, dma 0x%08x, next dma 0x%08x, current %d, curbuf 0x%08x\n",
1327 irq, sg_dma_address(*sg), sgnext ? sg_dma_address(sgnext) : 0, ichan->active_buffer, curbuf);
1328
1329 /* Find the descriptor of sgnext */
1330 sgnew = idmac_sg_next(ichan, &descnew, *sg);
1331 if (sgnext != sgnew)
1332 dev_err(dev, "Submitted buffer %p, next buffer %p\n", sgnext, sgnew);
1333
1334 /*
1335 * if sgnext == NULL sg must be the last element in a scatterlist and
1336 * queue must be empty
1337 */
1338 if (unlikely(!sgnext)) {
1339 if (!WARN_ON(sg_next(*sg)))
1340 dev_dbg(dev, "Underrun on channel %x\n", chan_id);
1341 ichan->sg[!ichan->active_buffer] = sgnew;
1342
1343 if (unlikely(sgnew)) {
1344 ipu_submit_buffer(ichan, descnew, sgnew, !ichan->active_buffer);
1345 } else {
1346 spin_lock_irqsave(&ipu_data.lock, flags);
1347 ipu_ic_disable_task(&ipu_data, chan_id);
1348 spin_unlock_irqrestore(&ipu_data.lock, flags);
1349 ichan->status = IPU_CHANNEL_READY;
1350 /* Continue to check for complete descriptor */
1351 }
1352 }
1353
1354 /* Calculate and submit the next sg element */
1355 sgnew = idmac_sg_next(ichan, &descnew, sgnew);
1356
1357 if (unlikely(!sg_next(*sg)) || !sgnext) {
1358 /*
1359 * Last element in scatterlist done, remove from the queue,
1360 * _init for debugging
1361 */
1362 list_del_init(&desc->list);
1363 done = true;
1364 }
1365
1366 *sg = sgnew;
1367
1368 if (likely(sgnew) &&
1369 ipu_submit_buffer(ichan, descnew, sgnew, ichan->active_buffer) < 0) {
1370 callback = descnew->txd.callback;
1371 callback_param = descnew->txd.callback_param;
1372 spin_unlock(&ichan->lock);
1373 if (callback)
1374 callback(callback_param);
1375 spin_lock(&ichan->lock);
1376 }
1377
1378 /* Flip the active buffer - even if update above failed */
1379 ichan->active_buffer = !ichan->active_buffer;
1380 if (done)
1381 ichan->completed = desc->txd.cookie;
1382
1383 callback = desc->txd.callback;
1384 callback_param = desc->txd.callback_param;
1385
1386 spin_unlock(&ichan->lock);
1387
1388 if (done && (desc->txd.flags & DMA_PREP_INTERRUPT) && callback)
1389 callback(callback_param);
1390
1391 return IRQ_HANDLED;
1392 }
1393
1394 static void ipu_gc_tasklet(unsigned long arg)
1395 {
1396 struct ipu *ipu = (struct ipu *)arg;
1397 int i;
1398
1399 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1400 struct idmac_channel *ichan = ipu->channel + i;
1401 struct idmac_tx_desc *desc;
1402 unsigned long flags;
1403 struct scatterlist *sg;
1404 int j, k;
1405
1406 for (j = 0; j < ichan->n_tx_desc; j++) {
1407 desc = ichan->desc + j;
1408 spin_lock_irqsave(&ichan->lock, flags);
1409 if (async_tx_test_ack(&desc->txd)) {
1410 list_move(&desc->list, &ichan->free_list);
1411 for_each_sg(desc->sg, sg, desc->sg_len, k) {
1412 if (ichan->sg[0] == sg)
1413 ichan->sg[0] = NULL;
1414 else if (ichan->sg[1] == sg)
1415 ichan->sg[1] = NULL;
1416 }
1417 async_tx_clear_ack(&desc->txd);
1418 }
1419 spin_unlock_irqrestore(&ichan->lock, flags);
1420 }
1421 }
1422 }
1423
1424 /* Allocate and initialise a transfer descriptor. */
1425 static struct dma_async_tx_descriptor *idmac_prep_slave_sg(struct dma_chan *chan,
1426 struct scatterlist *sgl, unsigned int sg_len,
1427 enum dma_data_direction direction, unsigned long tx_flags)
1428 {
1429 struct idmac_channel *ichan = to_idmac_chan(chan);
1430 struct idmac_tx_desc *desc = NULL;
1431 struct dma_async_tx_descriptor *txd = NULL;
1432 unsigned long flags;
1433
1434 /* We only can handle these three channels so far */
1435 if (chan->chan_id != IDMAC_SDC_0 && chan->chan_id != IDMAC_SDC_1 &&
1436 chan->chan_id != IDMAC_IC_7)
1437 return NULL;
1438
1439 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE) {
1440 dev_err(chan->device->dev, "Invalid DMA direction %d!\n", direction);
1441 return NULL;
1442 }
1443
1444 mutex_lock(&ichan->chan_mutex);
1445
1446 spin_lock_irqsave(&ichan->lock, flags);
1447 if (!list_empty(&ichan->free_list)) {
1448 desc = list_entry(ichan->free_list.next,
1449 struct idmac_tx_desc, list);
1450
1451 list_del_init(&desc->list);
1452
1453 desc->sg_len = sg_len;
1454 desc->sg = sgl;
1455 txd = &desc->txd;
1456 txd->flags = tx_flags;
1457 }
1458 spin_unlock_irqrestore(&ichan->lock, flags);
1459
1460 mutex_unlock(&ichan->chan_mutex);
1461
1462 tasklet_schedule(&to_ipu(to_idmac(chan->device))->tasklet);
1463
1464 return txd;
1465 }
1466
1467 /* Re-select the current buffer and re-activate the channel */
1468 static void idmac_issue_pending(struct dma_chan *chan)
1469 {
1470 struct idmac_channel *ichan = to_idmac_chan(chan);
1471 struct idmac *idmac = to_idmac(chan->device);
1472 struct ipu *ipu = to_ipu(idmac);
1473 unsigned long flags;
1474
1475 /* This is not always needed, but doesn't hurt either */
1476 spin_lock_irqsave(&ipu->lock, flags);
1477 ipu_select_buffer(chan->chan_id, ichan->active_buffer);
1478 spin_unlock_irqrestore(&ipu->lock, flags);
1479
1480 /*
1481 * Might need to perform some parts of initialisation from
1482 * ipu_enable_channel(), but not all, we do not want to reset to buffer
1483 * 0, don't need to set priority again either, but re-enabling the task
1484 * and the channel might be a good idea.
1485 */
1486 }
1487
1488 static void __idmac_terminate_all(struct dma_chan *chan)
1489 {
1490 struct idmac_channel *ichan = to_idmac_chan(chan);
1491 struct idmac *idmac = to_idmac(chan->device);
1492 unsigned long flags;
1493 int i;
1494
1495 ipu_disable_channel(idmac, ichan,
1496 ichan->status >= IPU_CHANNEL_ENABLED);
1497
1498 tasklet_disable(&to_ipu(idmac)->tasklet);
1499
1500 /* ichan->queue is modified in ISR, have to spinlock */
1501 spin_lock_irqsave(&ichan->lock, flags);
1502 list_splice_init(&ichan->queue, &ichan->free_list);
1503
1504 if (ichan->desc)
1505 for (i = 0; i < ichan->n_tx_desc; i++) {
1506 struct idmac_tx_desc *desc = ichan->desc + i;
1507 if (list_empty(&desc->list))
1508 /* Descriptor was prepared, but not submitted */
1509 list_add(&desc->list, &ichan->free_list);
1510
1511 async_tx_clear_ack(&desc->txd);
1512 }
1513
1514 ichan->sg[0] = NULL;
1515 ichan->sg[1] = NULL;
1516 spin_unlock_irqrestore(&ichan->lock, flags);
1517
1518 tasklet_enable(&to_ipu(idmac)->tasklet);
1519
1520 ichan->status = IPU_CHANNEL_INITIALIZED;
1521 }
1522
1523 static void idmac_terminate_all(struct dma_chan *chan)
1524 {
1525 struct idmac_channel *ichan = to_idmac_chan(chan);
1526
1527 mutex_lock(&ichan->chan_mutex);
1528
1529 __idmac_terminate_all(chan);
1530
1531 mutex_unlock(&ichan->chan_mutex);
1532 }
1533
1534 #ifdef DEBUG
1535 static irqreturn_t ic_sof_irq(int irq, void *dev_id)
1536 {
1537 struct idmac_channel *ichan = dev_id;
1538 printk(KERN_DEBUG "Got SOF IRQ %d on Channel %d\n",
1539 irq, ichan->dma_chan.chan_id);
1540 disable_irq_nosync(irq);
1541 return IRQ_HANDLED;
1542 }
1543
1544 static irqreturn_t ic_eof_irq(int irq, void *dev_id)
1545 {
1546 struct idmac_channel *ichan = dev_id;
1547 printk(KERN_DEBUG "Got EOF IRQ %d on Channel %d\n",
1548 irq, ichan->dma_chan.chan_id);
1549 disable_irq_nosync(irq);
1550 return IRQ_HANDLED;
1551 }
1552
1553 static int ic_sof = -EINVAL, ic_eof = -EINVAL;
1554 #endif
1555
1556 static int idmac_alloc_chan_resources(struct dma_chan *chan)
1557 {
1558 struct idmac_channel *ichan = to_idmac_chan(chan);
1559 struct idmac *idmac = to_idmac(chan->device);
1560 int ret;
1561
1562 /* dmaengine.c now guarantees to only offer free channels */
1563 BUG_ON(chan->client_count > 1);
1564 WARN_ON(ichan->status != IPU_CHANNEL_FREE);
1565
1566 chan->cookie = 1;
1567 ichan->completed = -ENXIO;
1568
1569 ret = ipu_irq_map(chan->chan_id);
1570 if (ret < 0)
1571 goto eimap;
1572
1573 ichan->eof_irq = ret;
1574
1575 /*
1576 * Important to first disable the channel, because maybe someone
1577 * used it before us, e.g., the bootloader
1578 */
1579 ipu_disable_channel(idmac, ichan, true);
1580
1581 ret = ipu_init_channel(idmac, ichan);
1582 if (ret < 0)
1583 goto eichan;
1584
1585 ret = request_irq(ichan->eof_irq, idmac_interrupt, 0,
1586 ichan->eof_name, ichan);
1587 if (ret < 0)
1588 goto erirq;
1589
1590 #ifdef DEBUG
1591 if (chan->chan_id == IDMAC_IC_7) {
1592 ic_sof = ipu_irq_map(69);
1593 if (ic_sof > 0)
1594 request_irq(ic_sof, ic_sof_irq, 0, "IC SOF", ichan);
1595 ic_eof = ipu_irq_map(70);
1596 if (ic_eof > 0)
1597 request_irq(ic_eof, ic_eof_irq, 0, "IC EOF", ichan);
1598 }
1599 #endif
1600
1601 ichan->status = IPU_CHANNEL_INITIALIZED;
1602
1603 dev_dbg(&chan->dev->device, "Found channel 0x%x, irq %d\n",
1604 chan->chan_id, ichan->eof_irq);
1605
1606 return ret;
1607
1608 erirq:
1609 ipu_uninit_channel(idmac, ichan);
1610 eichan:
1611 ipu_irq_unmap(chan->chan_id);
1612 eimap:
1613 return ret;
1614 }
1615
1616 static void idmac_free_chan_resources(struct dma_chan *chan)
1617 {
1618 struct idmac_channel *ichan = to_idmac_chan(chan);
1619 struct idmac *idmac = to_idmac(chan->device);
1620
1621 mutex_lock(&ichan->chan_mutex);
1622
1623 __idmac_terminate_all(chan);
1624
1625 if (ichan->status > IPU_CHANNEL_FREE) {
1626 #ifdef DEBUG
1627 if (chan->chan_id == IDMAC_IC_7) {
1628 if (ic_sof > 0) {
1629 free_irq(ic_sof, ichan);
1630 ipu_irq_unmap(69);
1631 ic_sof = -EINVAL;
1632 }
1633 if (ic_eof > 0) {
1634 free_irq(ic_eof, ichan);
1635 ipu_irq_unmap(70);
1636 ic_eof = -EINVAL;
1637 }
1638 }
1639 #endif
1640 free_irq(ichan->eof_irq, ichan);
1641 ipu_irq_unmap(chan->chan_id);
1642 }
1643
1644 ichan->status = IPU_CHANNEL_FREE;
1645
1646 ipu_uninit_channel(idmac, ichan);
1647
1648 mutex_unlock(&ichan->chan_mutex);
1649
1650 tasklet_schedule(&to_ipu(idmac)->tasklet);
1651 }
1652
1653 static enum dma_status idmac_is_tx_complete(struct dma_chan *chan,
1654 dma_cookie_t cookie, dma_cookie_t *done, dma_cookie_t *used)
1655 {
1656 struct idmac_channel *ichan = to_idmac_chan(chan);
1657
1658 if (done)
1659 *done = ichan->completed;
1660 if (used)
1661 *used = chan->cookie;
1662 if (cookie != chan->cookie)
1663 return DMA_ERROR;
1664 return DMA_SUCCESS;
1665 }
1666
1667 static int __init ipu_idmac_init(struct ipu *ipu)
1668 {
1669 struct idmac *idmac = &ipu->idmac;
1670 struct dma_device *dma = &idmac->dma;
1671 int i;
1672
1673 dma_cap_set(DMA_SLAVE, dma->cap_mask);
1674 dma_cap_set(DMA_PRIVATE, dma->cap_mask);
1675
1676 /* Compulsory common fields */
1677 dma->dev = ipu->dev;
1678 dma->device_alloc_chan_resources = idmac_alloc_chan_resources;
1679 dma->device_free_chan_resources = idmac_free_chan_resources;
1680 dma->device_is_tx_complete = idmac_is_tx_complete;
1681 dma->device_issue_pending = idmac_issue_pending;
1682
1683 /* Compulsory for DMA_SLAVE fields */
1684 dma->device_prep_slave_sg = idmac_prep_slave_sg;
1685 dma->device_terminate_all = idmac_terminate_all;
1686
1687 INIT_LIST_HEAD(&dma->channels);
1688 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1689 struct idmac_channel *ichan = ipu->channel + i;
1690 struct dma_chan *dma_chan = &ichan->dma_chan;
1691
1692 spin_lock_init(&ichan->lock);
1693 mutex_init(&ichan->chan_mutex);
1694
1695 ichan->status = IPU_CHANNEL_FREE;
1696 ichan->sec_chan_en = false;
1697 ichan->completed = -ENXIO;
1698 snprintf(ichan->eof_name, sizeof(ichan->eof_name), "IDMAC EOF %d", i);
1699
1700 dma_chan->device = &idmac->dma;
1701 dma_chan->cookie = 1;
1702 dma_chan->chan_id = i;
1703 list_add_tail(&dma_chan->device_node, &dma->channels);
1704 }
1705
1706 idmac_write_icreg(ipu, 0x00000070, IDMAC_CONF);
1707
1708 return dma_async_device_register(&idmac->dma);
1709 }
1710
1711 static void __exit ipu_idmac_exit(struct ipu *ipu)
1712 {
1713 int i;
1714 struct idmac *idmac = &ipu->idmac;
1715
1716 for (i = 0; i < IPU_CHANNELS_NUM; i++) {
1717 struct idmac_channel *ichan = ipu->channel + i;
1718
1719 idmac_terminate_all(&ichan->dma_chan);
1720 idmac_prep_slave_sg(&ichan->dma_chan, NULL, 0, DMA_NONE, 0);
1721 }
1722
1723 dma_async_device_unregister(&idmac->dma);
1724 }
1725
1726 /*****************************************************************************
1727 * IPU common probe / remove
1728 */
1729
1730 static int __init ipu_probe(struct platform_device *pdev)
1731 {
1732 struct ipu_platform_data *pdata = pdev->dev.platform_data;
1733 struct resource *mem_ipu, *mem_ic;
1734 int ret;
1735
1736 spin_lock_init(&ipu_data.lock);
1737
1738 mem_ipu = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1739 mem_ic = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1740 if (!pdata || !mem_ipu || !mem_ic)
1741 return -EINVAL;
1742
1743 ipu_data.dev = &pdev->dev;
1744
1745 platform_set_drvdata(pdev, &ipu_data);
1746
1747 ret = platform_get_irq(pdev, 0);
1748 if (ret < 0)
1749 goto err_noirq;
1750
1751 ipu_data.irq_fn = ret;
1752 ret = platform_get_irq(pdev, 1);
1753 if (ret < 0)
1754 goto err_noirq;
1755
1756 ipu_data.irq_err = ret;
1757 ipu_data.irq_base = pdata->irq_base;
1758
1759 dev_dbg(&pdev->dev, "fn irq %u, err irq %u, irq-base %u\n",
1760 ipu_data.irq_fn, ipu_data.irq_err, ipu_data.irq_base);
1761
1762 /* Remap IPU common registers */
1763 ipu_data.reg_ipu = ioremap(mem_ipu->start,
1764 mem_ipu->end - mem_ipu->start + 1);
1765 if (!ipu_data.reg_ipu) {
1766 ret = -ENOMEM;
1767 goto err_ioremap_ipu;
1768 }
1769
1770 /* Remap Image Converter and Image DMA Controller registers */
1771 ipu_data.reg_ic = ioremap(mem_ic->start,
1772 mem_ic->end - mem_ic->start + 1);
1773 if (!ipu_data.reg_ic) {
1774 ret = -ENOMEM;
1775 goto err_ioremap_ic;
1776 }
1777
1778 /* Get IPU clock */
1779 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1780 if (IS_ERR(ipu_data.ipu_clk)) {
1781 ret = PTR_ERR(ipu_data.ipu_clk);
1782 goto err_clk_get;
1783 }
1784
1785 /* Make sure IPU HSP clock is running */
1786 clk_enable(ipu_data.ipu_clk);
1787
1788 /* Disable all interrupts */
1789 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_1);
1790 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_2);
1791 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_3);
1792 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_4);
1793 idmac_write_ipureg(&ipu_data, 0, IPU_INT_CTRL_5);
1794
1795 dev_dbg(&pdev->dev, "%s @ 0x%08lx, fn irq %u, err irq %u\n", pdev->name,
1796 (unsigned long)mem_ipu->start, ipu_data.irq_fn, ipu_data.irq_err);
1797
1798 ret = ipu_irq_attach_irq(&ipu_data, pdev);
1799 if (ret < 0)
1800 goto err_attach_irq;
1801
1802 /* Initialize DMA engine */
1803 ret = ipu_idmac_init(&ipu_data);
1804 if (ret < 0)
1805 goto err_idmac_init;
1806
1807 tasklet_init(&ipu_data.tasklet, ipu_gc_tasklet, (unsigned long)&ipu_data);
1808
1809 ipu_data.dev = &pdev->dev;
1810
1811 dev_dbg(ipu_data.dev, "IPU initialized\n");
1812
1813 return 0;
1814
1815 err_idmac_init:
1816 err_attach_irq:
1817 ipu_irq_detach_irq(&ipu_data, pdev);
1818 clk_disable(ipu_data.ipu_clk);
1819 clk_put(ipu_data.ipu_clk);
1820 err_clk_get:
1821 iounmap(ipu_data.reg_ic);
1822 err_ioremap_ic:
1823 iounmap(ipu_data.reg_ipu);
1824 err_ioremap_ipu:
1825 err_noirq:
1826 dev_err(&pdev->dev, "Failed to probe IPU: %d\n", ret);
1827 return ret;
1828 }
1829
1830 static int __exit ipu_remove(struct platform_device *pdev)
1831 {
1832 struct ipu *ipu = platform_get_drvdata(pdev);
1833
1834 ipu_idmac_exit(ipu);
1835 ipu_irq_detach_irq(ipu, pdev);
1836 clk_disable(ipu->ipu_clk);
1837 clk_put(ipu->ipu_clk);
1838 iounmap(ipu->reg_ic);
1839 iounmap(ipu->reg_ipu);
1840 tasklet_kill(&ipu->tasklet);
1841 platform_set_drvdata(pdev, NULL);
1842
1843 return 0;
1844 }
1845
1846 /*
1847 * We need two MEM resources - with IPU-common and Image Converter registers,
1848 * including PF_CONF and IDMAC_* registers, and two IRQs - function and error
1849 */
1850 static struct platform_driver ipu_platform_driver = {
1851 .driver = {
1852 .name = "ipu-core",
1853 .owner = THIS_MODULE,
1854 },
1855 .remove = __exit_p(ipu_remove),
1856 };
1857
1858 static int __init ipu_init(void)
1859 {
1860 return platform_driver_probe(&ipu_platform_driver, ipu_probe);
1861 }
1862 subsys_initcall(ipu_init);
1863
1864 MODULE_DESCRIPTION("IPU core driver");
1865 MODULE_LICENSE("GPL v2");
1866 MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
1867 MODULE_ALIAS("platform:ipu-core");
linux 2.6 git repository for openrd