2 * linux/arch/arm/plat-omap/dmtimer.c
4 * OMAP Dual-Mode Timers
6 * Copyright (C) 2005 Nokia Corporation
7 * OMAP2 support by Juha Yrjola
8 * API improvements and OMAP2 clock framework support by Timo Teras
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 #include <linux/init.h>
30 #include <linux/spinlock.h>
31 #include <linux/errno.h>
32 #include <linux/list.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
36 #include <mach/hardware.h>
37 #include <mach/dmtimer.h>
38 #include <mach/irqs.h>
40 /* register offsets */
41 #define _OMAP_TIMER_ID_OFFSET 0x00
42 #define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
43 #define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
44 #define _OMAP_TIMER_STAT_OFFSET 0x18
45 #define _OMAP_TIMER_INT_EN_OFFSET 0x1c
46 #define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
47 #define _OMAP_TIMER_CTRL_OFFSET 0x24
48 #define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
49 #define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
50 #define OMAP_TIMER_CTRL_PT (1 << 12)
51 #define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
52 #define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
53 #define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
54 #define OMAP_TIMER_CTRL_SCPWM (1 << 7)
55 #define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
56 #define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
57 #define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
58 #define OMAP_TIMER_CTRL_POSTED (1 << 2)
59 #define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
60 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
61 #define _OMAP_TIMER_COUNTER_OFFSET 0x28
62 #define _OMAP_TIMER_LOAD_OFFSET 0x2c
63 #define _OMAP_TIMER_TRIGGER_OFFSET 0x30
64 #define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
65 #define WP_NONE 0 /* no write pending bit */
66 #define WP_TCLR (1 << 0)
67 #define WP_TCRR (1 << 1)
68 #define WP_TLDR (1 << 2)
69 #define WP_TTGR (1 << 3)
70 #define WP_TMAR (1 << 4)
71 #define WP_TPIR (1 << 5)
72 #define WP_TNIR (1 << 6)
73 #define WP_TCVR (1 << 7)
74 #define WP_TOCR (1 << 8)
75 #define WP_TOWR (1 << 9)
76 #define _OMAP_TIMER_MATCH_OFFSET 0x38
77 #define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
78 #define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
79 #define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
80 #define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
81 #define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
82 #define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
83 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
84 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
86 /* register offsets with the write pending bit encoded */
89 #define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
90 | (WP_NONE << WPSHIFT))
92 #define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
93 | (WP_NONE << WPSHIFT))
95 #define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
96 | (WP_NONE << WPSHIFT))
98 #define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
99 | (WP_NONE << WPSHIFT))
101 #define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
102 | (WP_NONE << WPSHIFT))
104 #define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
105 | (WP_NONE << WPSHIFT))
107 #define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
108 | (WP_TCLR << WPSHIFT))
110 #define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
111 | (WP_TCRR << WPSHIFT))
113 #define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
114 | (WP_TLDR << WPSHIFT))
116 #define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
117 | (WP_TTGR << WPSHIFT))
119 #define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
120 | (WP_NONE << WPSHIFT))
122 #define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
123 | (WP_TMAR << WPSHIFT))
125 #define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
126 | (WP_NONE << WPSHIFT))
128 #define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
129 | (WP_NONE << WPSHIFT))
131 #define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
132 | (WP_NONE << WPSHIFT))
134 #define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
135 | (WP_TPIR << WPSHIFT))
137 #define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
138 | (WP_TNIR << WPSHIFT))
140 #define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
141 | (WP_TCVR << WPSHIFT))
143 #define OMAP_TIMER_TICK_INT_MASK_SET_REG \
144 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
146 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
147 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
149 struct omap_dm_timer
{
150 unsigned long phys_base
;
152 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
153 struct clk
*iclk
, *fclk
;
155 void __iomem
*io_base
;
161 #ifdef CONFIG_ARCH_OMAP1
163 #define omap_dm_clk_enable(x)
164 #define omap_dm_clk_disable(x)
165 #define omap2_dm_timers NULL
166 #define omap2_dm_source_names NULL
167 #define omap2_dm_source_clocks NULL
168 #define omap3_dm_timers NULL
169 #define omap3_dm_source_names NULL
170 #define omap3_dm_source_clocks NULL
172 static struct omap_dm_timer omap1_dm_timers
[] = {
173 { .phys_base
= 0xfffb1400, .irq
= INT_1610_GPTIMER1
},
174 { .phys_base
= 0xfffb1c00, .irq
= INT_1610_GPTIMER2
},
175 { .phys_base
= 0xfffb2400, .irq
= INT_1610_GPTIMER3
},
176 { .phys_base
= 0xfffb2c00, .irq
= INT_1610_GPTIMER4
},
177 { .phys_base
= 0xfffb3400, .irq
= INT_1610_GPTIMER5
},
178 { .phys_base
= 0xfffb3c00, .irq
= INT_1610_GPTIMER6
},
179 { .phys_base
= 0xfffb7400, .irq
= INT_1610_GPTIMER7
},
180 { .phys_base
= 0xfffbd400, .irq
= INT_1610_GPTIMER8
},
183 static const int dm_timer_count
= ARRAY_SIZE(omap1_dm_timers
);
185 #elif defined(CONFIG_ARCH_OMAP2)
187 #define omap_dm_clk_enable(x) clk_enable(x)
188 #define omap_dm_clk_disable(x) clk_disable(x)
189 #define omap1_dm_timers NULL
190 #define omap3_dm_timers NULL
191 #define omap3_dm_source_names NULL
192 #define omap3_dm_source_clocks NULL
194 static struct omap_dm_timer omap2_dm_timers
[] = {
195 { .phys_base
= 0x48028000, .irq
= INT_24XX_GPTIMER1
},
196 { .phys_base
= 0x4802a000, .irq
= INT_24XX_GPTIMER2
},
197 { .phys_base
= 0x48078000, .irq
= INT_24XX_GPTIMER3
},
198 { .phys_base
= 0x4807a000, .irq
= INT_24XX_GPTIMER4
},
199 { .phys_base
= 0x4807c000, .irq
= INT_24XX_GPTIMER5
},
200 { .phys_base
= 0x4807e000, .irq
= INT_24XX_GPTIMER6
},
201 { .phys_base
= 0x48080000, .irq
= INT_24XX_GPTIMER7
},
202 { .phys_base
= 0x48082000, .irq
= INT_24XX_GPTIMER8
},
203 { .phys_base
= 0x48084000, .irq
= INT_24XX_GPTIMER9
},
204 { .phys_base
= 0x48086000, .irq
= INT_24XX_GPTIMER10
},
205 { .phys_base
= 0x48088000, .irq
= INT_24XX_GPTIMER11
},
206 { .phys_base
= 0x4808a000, .irq
= INT_24XX_GPTIMER12
},
209 static const char *omap2_dm_source_names
[] __initdata
= {
216 static struct clk
**omap2_dm_source_clocks
[3];
217 static const int dm_timer_count
= ARRAY_SIZE(omap2_dm_timers
);
219 #elif defined(CONFIG_ARCH_OMAP3)
221 #define omap_dm_clk_enable(x) clk_enable(x)
222 #define omap_dm_clk_disable(x) clk_disable(x)
223 #define omap1_dm_timers NULL
224 #define omap2_dm_timers NULL
225 #define omap2_dm_source_names NULL
226 #define omap2_dm_source_clocks NULL
228 static struct omap_dm_timer omap3_dm_timers
[] = {
229 { .phys_base
= 0x48318000, .irq
= INT_24XX_GPTIMER1
},
230 { .phys_base
= 0x49032000, .irq
= INT_24XX_GPTIMER2
},
231 { .phys_base
= 0x49034000, .irq
= INT_24XX_GPTIMER3
},
232 { .phys_base
= 0x49036000, .irq
= INT_24XX_GPTIMER4
},
233 { .phys_base
= 0x49038000, .irq
= INT_24XX_GPTIMER5
},
234 { .phys_base
= 0x4903A000, .irq
= INT_24XX_GPTIMER6
},
235 { .phys_base
= 0x4903C000, .irq
= INT_24XX_GPTIMER7
},
236 { .phys_base
= 0x4903E000, .irq
= INT_24XX_GPTIMER8
},
237 { .phys_base
= 0x49040000, .irq
= INT_24XX_GPTIMER9
},
238 { .phys_base
= 0x48086000, .irq
= INT_24XX_GPTIMER10
},
239 { .phys_base
= 0x48088000, .irq
= INT_24XX_GPTIMER11
},
240 { .phys_base
= 0x48304000, .irq
= INT_24XX_GPTIMER12
},
243 static const char *omap3_dm_source_names
[] __initdata
= {
249 static struct clk
**omap3_dm_source_clocks
[2];
250 static const int dm_timer_count
= ARRAY_SIZE(omap3_dm_timers
);
254 #error OMAP architecture not supported!
258 static struct omap_dm_timer
*dm_timers
;
259 static char **dm_source_names
;
260 static struct clk
**dm_source_clocks
;
262 static spinlock_t dm_timer_lock
;
265 * Reads timer registers in posted and non-posted mode. The posted mode bit
266 * is encoded in reg. Note that in posted mode write pending bit must be
267 * checked. Otherwise a read of a non completed write will produce an error.
269 static inline u32
omap_dm_timer_read_reg(struct omap_dm_timer
*timer
, u32 reg
)
272 while (readl(timer
->io_base
+ (OMAP_TIMER_WRITE_PEND_REG
& 0xff))
275 return readl(timer
->io_base
+ (reg
& 0xff));
279 * Writes timer registers in posted and non-posted mode. The posted mode bit
280 * is encoded in reg. Note that in posted mode the write pending bit must be
281 * checked. Otherwise a write on a register which has a pending write will be
284 static void omap_dm_timer_write_reg(struct omap_dm_timer
*timer
, u32 reg
,
288 while (readl(timer
->io_base
+ (OMAP_TIMER_WRITE_PEND_REG
& 0xff))
291 writel(value
, timer
->io_base
+ (reg
& 0xff));
294 static void omap_dm_timer_wait_for_reset(struct omap_dm_timer
*timer
)
299 while (!(omap_dm_timer_read_reg(timer
, OMAP_TIMER_SYS_STAT_REG
) & 1)) {
302 printk(KERN_ERR
"Timer failed to reset\n");
308 static void omap_dm_timer_reset(struct omap_dm_timer
*timer
)
312 if (!cpu_class_is_omap2() || timer
!= &dm_timers
[0]) {
313 omap_dm_timer_write_reg(timer
, OMAP_TIMER_IF_CTRL_REG
, 0x06);
314 omap_dm_timer_wait_for_reset(timer
);
316 omap_dm_timer_set_source(timer
, OMAP_TIMER_SRC_32_KHZ
);
318 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_OCP_CFG_REG
);
319 l
|= 0x02 << 3; /* Set to smart-idle mode */
320 l
|= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
323 * Enable wake-up only for GPT1 on OMAP2 CPUs.
324 * FIXME: All timers should have wake-up enabled and clear
327 if (cpu_class_is_omap2() && (timer
== &dm_timers
[0]))
329 omap_dm_timer_write_reg(timer
, OMAP_TIMER_OCP_CFG_REG
, l
);
331 /* Match hardware reset default of posted mode */
332 omap_dm_timer_write_reg(timer
, OMAP_TIMER_IF_CTRL_REG
,
333 OMAP_TIMER_CTRL_POSTED
);
337 static void omap_dm_timer_prepare(struct omap_dm_timer
*timer
)
339 omap_dm_timer_enable(timer
);
340 omap_dm_timer_reset(timer
);
343 struct omap_dm_timer
*omap_dm_timer_request(void)
345 struct omap_dm_timer
*timer
= NULL
;
349 spin_lock_irqsave(&dm_timer_lock
, flags
);
350 for (i
= 0; i
< dm_timer_count
; i
++) {
351 if (dm_timers
[i
].reserved
)
354 timer
= &dm_timers
[i
];
358 spin_unlock_irqrestore(&dm_timer_lock
, flags
);
361 omap_dm_timer_prepare(timer
);
366 struct omap_dm_timer
*omap_dm_timer_request_specific(int id
)
368 struct omap_dm_timer
*timer
;
371 spin_lock_irqsave(&dm_timer_lock
, flags
);
372 if (id
<= 0 || id
> dm_timer_count
|| dm_timers
[id
-1].reserved
) {
373 spin_unlock_irqrestore(&dm_timer_lock
, flags
);
374 printk("BUG: warning at %s:%d/%s(): unable to get timer %d\n",
375 __FILE__
, __LINE__
, __func__
, id
);
380 timer
= &dm_timers
[id
-1];
382 spin_unlock_irqrestore(&dm_timer_lock
, flags
);
384 omap_dm_timer_prepare(timer
);
389 void omap_dm_timer_free(struct omap_dm_timer
*timer
)
391 omap_dm_timer_enable(timer
);
392 omap_dm_timer_reset(timer
);
393 omap_dm_timer_disable(timer
);
395 WARN_ON(!timer
->reserved
);
399 void omap_dm_timer_enable(struct omap_dm_timer
*timer
)
404 omap_dm_clk_enable(timer
->fclk
);
405 omap_dm_clk_enable(timer
->iclk
);
410 void omap_dm_timer_disable(struct omap_dm_timer
*timer
)
415 omap_dm_clk_disable(timer
->iclk
);
416 omap_dm_clk_disable(timer
->fclk
);
421 int omap_dm_timer_get_irq(struct omap_dm_timer
*timer
)
426 #if defined(CONFIG_ARCH_OMAP1)
429 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
430 * @inputmask: current value of idlect mask
432 __u32
omap_dm_timer_modify_idlect_mask(__u32 inputmask
)
436 /* If ARMXOR cannot be idled this function call is unnecessary */
437 if (!(inputmask
& (1 << 1)))
440 /* If any active timer is using ARMXOR return modified mask */
441 for (i
= 0; i
< dm_timer_count
; i
++) {
444 l
= omap_dm_timer_read_reg(&dm_timers
[i
], OMAP_TIMER_CTRL_REG
);
445 if (l
& OMAP_TIMER_CTRL_ST
) {
446 if (((omap_readl(MOD_CONF_CTRL_1
) >> (i
* 2)) & 0x03) == 0)
447 inputmask
&= ~(1 << 1);
449 inputmask
&= ~(1 << 2);
456 #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3)
458 struct clk
*omap_dm_timer_get_fclk(struct omap_dm_timer
*timer
)
463 __u32
omap_dm_timer_modify_idlect_mask(__u32 inputmask
)
472 void omap_dm_timer_trigger(struct omap_dm_timer
*timer
)
474 omap_dm_timer_write_reg(timer
, OMAP_TIMER_TRIGGER_REG
, 0);
477 void omap_dm_timer_start(struct omap_dm_timer
*timer
)
481 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
482 if (!(l
& OMAP_TIMER_CTRL_ST
)) {
483 l
|= OMAP_TIMER_CTRL_ST
;
484 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
488 void omap_dm_timer_stop(struct omap_dm_timer
*timer
)
492 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
493 if (l
& OMAP_TIMER_CTRL_ST
) {
495 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
499 #ifdef CONFIG_ARCH_OMAP1
501 void omap_dm_timer_set_source(struct omap_dm_timer
*timer
, int source
)
503 int n
= (timer
- dm_timers
) << 1;
506 l
= omap_readl(MOD_CONF_CTRL_1
) & ~(0x03 << n
);
508 omap_writel(l
, MOD_CONF_CTRL_1
);
513 void omap_dm_timer_set_source(struct omap_dm_timer
*timer
, int source
)
515 if (source
< 0 || source
>= 3)
518 clk_disable(timer
->fclk
);
519 clk_set_parent(timer
->fclk
, dm_source_clocks
[source
]);
520 clk_enable(timer
->fclk
);
522 /* When the functional clock disappears, too quick writes seem to
529 void omap_dm_timer_set_load(struct omap_dm_timer
*timer
, int autoreload
,
534 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
536 l
|= OMAP_TIMER_CTRL_AR
;
538 l
&= ~OMAP_TIMER_CTRL_AR
;
539 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
540 omap_dm_timer_write_reg(timer
, OMAP_TIMER_LOAD_REG
, load
);
542 /* REVISIT: hw feature, ttgr overtaking tldr? */
543 while (readl(timer
->io_base
+ (OMAP_TIMER_WRITE_PEND_REG
& 0xff)))
546 omap_dm_timer_write_reg(timer
, OMAP_TIMER_TRIGGER_REG
, 0);
549 /* Optimized set_load which removes costly spin wait in timer_start */
550 void omap_dm_timer_set_load_start(struct omap_dm_timer
*timer
, int autoreload
,
555 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
557 l
|= OMAP_TIMER_CTRL_AR
;
559 l
&= ~OMAP_TIMER_CTRL_AR
;
560 l
|= OMAP_TIMER_CTRL_ST
;
562 omap_dm_timer_write_reg(timer
, OMAP_TIMER_COUNTER_REG
, load
);
563 omap_dm_timer_write_reg(timer
, OMAP_TIMER_LOAD_REG
, load
);
564 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
567 void omap_dm_timer_set_match(struct omap_dm_timer
*timer
, int enable
,
572 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
574 l
|= OMAP_TIMER_CTRL_CE
;
576 l
&= ~OMAP_TIMER_CTRL_CE
;
577 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
578 omap_dm_timer_write_reg(timer
, OMAP_TIMER_MATCH_REG
, match
);
581 void omap_dm_timer_set_pwm(struct omap_dm_timer
*timer
, int def_on
,
582 int toggle
, int trigger
)
586 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
587 l
&= ~(OMAP_TIMER_CTRL_GPOCFG
| OMAP_TIMER_CTRL_SCPWM
|
588 OMAP_TIMER_CTRL_PT
| (0x03 << 10));
590 l
|= OMAP_TIMER_CTRL_SCPWM
;
592 l
|= OMAP_TIMER_CTRL_PT
;
594 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
597 void omap_dm_timer_set_prescaler(struct omap_dm_timer
*timer
, int prescaler
)
601 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
);
602 l
&= ~(OMAP_TIMER_CTRL_PRE
| (0x07 << 2));
603 if (prescaler
>= 0x00 && prescaler
<= 0x07) {
604 l
|= OMAP_TIMER_CTRL_PRE
;
607 omap_dm_timer_write_reg(timer
, OMAP_TIMER_CTRL_REG
, l
);
610 void omap_dm_timer_set_int_enable(struct omap_dm_timer
*timer
,
613 omap_dm_timer_write_reg(timer
, OMAP_TIMER_INT_EN_REG
, value
);
614 omap_dm_timer_write_reg(timer
, OMAP_TIMER_WAKEUP_EN_REG
, value
);
617 unsigned int omap_dm_timer_read_status(struct omap_dm_timer
*timer
)
621 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_STAT_REG
);
626 void omap_dm_timer_write_status(struct omap_dm_timer
*timer
, unsigned int value
)
628 omap_dm_timer_write_reg(timer
, OMAP_TIMER_STAT_REG
, value
);
631 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer
*timer
)
635 l
= omap_dm_timer_read_reg(timer
, OMAP_TIMER_COUNTER_REG
);
640 void omap_dm_timer_write_counter(struct omap_dm_timer
*timer
, unsigned int value
)
642 omap_dm_timer_write_reg(timer
, OMAP_TIMER_COUNTER_REG
, value
);
645 int omap_dm_timers_active(void)
649 for (i
= 0; i
< dm_timer_count
; i
++) {
650 struct omap_dm_timer
*timer
;
652 timer
= &dm_timers
[i
];
657 if (omap_dm_timer_read_reg(timer
, OMAP_TIMER_CTRL_REG
) &
658 OMAP_TIMER_CTRL_ST
) {
665 int __init
omap_dm_timer_init(void)
667 struct omap_dm_timer
*timer
;
670 if (!(cpu_is_omap16xx() || cpu_class_is_omap2()))
673 spin_lock_init(&dm_timer_lock
);
675 if (cpu_class_is_omap1())
676 dm_timers
= omap1_dm_timers
;
677 else if (cpu_is_omap24xx()) {
678 dm_timers
= omap2_dm_timers
;
679 dm_source_names
= (char **)omap2_dm_source_names
;
680 dm_source_clocks
= (struct clk
**)omap2_dm_source_clocks
;
681 } else if (cpu_is_omap34xx()) {
682 dm_timers
= omap3_dm_timers
;
683 dm_source_names
= (char **)omap3_dm_source_names
;
684 dm_source_clocks
= (struct clk
**)omap3_dm_source_clocks
;
687 if (cpu_class_is_omap2())
688 for (i
= 0; dm_source_names
[i
] != NULL
; i
++)
689 dm_source_clocks
[i
] = clk_get(NULL
, dm_source_names
[i
]);
691 if (cpu_is_omap243x())
692 dm_timers
[0].phys_base
= 0x49018000;
694 for (i
= 0; i
< dm_timer_count
; i
++) {
695 timer
= &dm_timers
[i
];
696 timer
->io_base
= (void __iomem
*)io_p2v(timer
->phys_base
);
697 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
698 if (cpu_class_is_omap2()) {
700 sprintf(clk_name
, "gpt%d_ick", i
+ 1);
701 timer
->iclk
= clk_get(NULL
, clk_name
);
702 sprintf(clk_name
, "gpt%d_fck", i
+ 1);
703 timer
->fclk
= clk_get(NULL
, clk_name
);