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drm/r500: add support for AGP based cards.
[linux-2.6/linux-2.6-openrd.git] / drivers / char / drm / radeon_cp.c
blobf5e22bfcc3cbd974f70234501f10c83153d894a5
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
36 #include "r300_reg.h"
37
38 #include "radeon_microcode.h"
39
40 #define RADEON_FIFO_DEBUG 0
41
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
43
44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
45 {
46 u32 ret;
47 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
48 ret = RADEON_READ(R520_MC_IND_DATA);
49 RADEON_WRITE(R520_MC_IND_INDEX, 0);
50 return ret;
51 }
52
53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
54 {
55 u32 ret;
56 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
57 ret = RADEON_READ(RS480_NB_MC_DATA);
58 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
59 return ret;
60 }
61
62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
63 {
64 u32 ret;
65 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
66 ret = RADEON_READ(RS690_MC_DATA);
67 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
68 return ret;
69 }
70
71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
72 {
73 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
74 return RS690_READ_MCIND(dev_priv, addr);
75 else
76 return RS480_READ_MCIND(dev_priv, addr);
77 }
78
79 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
80 {
81
82 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
83 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
84 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
85 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
86 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
87 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
88 else
89 return RADEON_READ(RADEON_MC_FB_LOCATION);
90 }
91
92 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
93 {
94 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
95 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
96 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
97 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
98 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
99 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
100 else
101 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
102 }
103
104 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
105 {
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
107 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
108 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
109 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
110 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
111 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
112 else
113 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
114 }
115
116 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
117 {
118 u32 agp_base_hi = upper_32_bits(agp_base);
119 u32 agp_base_lo = agp_base & 0xffffffff;
120
121 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
122 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
123 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
124 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
125 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
126 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
127 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
128 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
129 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
130 } else {
131 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
132 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
133 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
134 }
135 }
136
137 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
138 {
139 drm_radeon_private_t *dev_priv = dev->dev_private;
140
141 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
142 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
143 }
144
145 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
146 {
147 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
148 return RADEON_READ(RADEON_PCIE_DATA);
149 }
150
151 #if RADEON_FIFO_DEBUG
152 static void radeon_status(drm_radeon_private_t * dev_priv)
153 {
154 printk("%s:\n", __func__);
155 printk("RBBM_STATUS = 0x%08x\n",
156 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
157 printk("CP_RB_RTPR = 0x%08x\n",
158 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
159 printk("CP_RB_WTPR = 0x%08x\n",
160 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
161 printk("AIC_CNTL = 0x%08x\n",
162 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
163 printk("AIC_STAT = 0x%08x\n",
164 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
165 printk("AIC_PT_BASE = 0x%08x\n",
166 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
167 printk("TLB_ADDR = 0x%08x\n",
168 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
169 printk("TLB_DATA = 0x%08x\n",
170 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
171 }
172 #endif
173
174 /* ================================================================
175 * Engine, FIFO control
176 */
177
178 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
179 {
180 u32 tmp;
181 int i;
182
183 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
184
185 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
186 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
187 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
188 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
189
190 for (i = 0; i < dev_priv->usec_timeout; i++) {
191 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
192 & RADEON_RB3D_DC_BUSY)) {
193 return 0;
194 }
195 DRM_UDELAY(1);
196 }
197 } else {
198 /* 3D */
199 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
200 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
201 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
202
203 /* 2D */
204 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
205 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
206 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
207
208 for (i = 0; i < dev_priv->usec_timeout; i++) {
209 if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
210 & RADEON_RB3D_DC_BUSY)) {
211 return 0;
212 }
213 DRM_UDELAY(1);
214 }
215 }
216
217 #if RADEON_FIFO_DEBUG
218 DRM_ERROR("failed!\n");
219 radeon_status(dev_priv);
220 #endif
221 return -EBUSY;
222 }
223
224 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
225 {
226 int i;
227
228 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
229
230 for (i = 0; i < dev_priv->usec_timeout; i++) {
231 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
232 & RADEON_RBBM_FIFOCNT_MASK);
233 if (slots >= entries)
234 return 0;
235 DRM_UDELAY(1);
236 }
237
238 #if RADEON_FIFO_DEBUG
239 DRM_ERROR("failed!\n");
240 radeon_status(dev_priv);
241 #endif
242 return -EBUSY;
243 }
244
245 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
246 {
247 int i, ret;
248
249 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
250
251 ret = radeon_do_wait_for_fifo(dev_priv, 64);
252 if (ret)
253 return ret;
254
255 for (i = 0; i < dev_priv->usec_timeout; i++) {
256 if (!(RADEON_READ(RADEON_RBBM_STATUS)
257 & RADEON_RBBM_ACTIVE)) {
258 radeon_do_pixcache_flush(dev_priv);
259 return 0;
260 }
261 DRM_UDELAY(1);
262 }
263
264 #if RADEON_FIFO_DEBUG
265 DRM_ERROR("failed!\n");
266 radeon_status(dev_priv);
267 #endif
268 return -EBUSY;
269 }
270
271 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
272 {
273 uint32_t gb_tile_config, gb_pipe_sel = 0;
274
275 /* RS4xx/RS6xx/R4xx/R5xx */
276 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
277 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
278 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
279 } else {
280 /* R3xx */
281 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
282 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
283 dev_priv->num_gb_pipes = 2;
284 } else {
285 /* R3Vxx */
286 dev_priv->num_gb_pipes = 1;
287 }
288 }
289 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
290
291 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
292
293 switch (dev_priv->num_gb_pipes) {
294 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
295 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
296 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
297 default:
298 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
299 }
300
301 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
302 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
303 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
304 }
305 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
306 radeon_do_wait_for_idle(dev_priv);
307 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
308 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
309 R300_DC_AUTOFLUSH_ENABLE |
310 R300_DC_DC_DISABLE_IGNORE_PE));
311
312
313 }
314
315 /* ================================================================
316 * CP control, initialization
317 */
318
319 /* Load the microcode for the CP */
320 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
321 {
322 int i;
323 DRM_DEBUG("\n");
324
325 radeon_do_wait_for_idle(dev_priv);
326
327 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
328 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
329 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
330 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
331 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
333 DRM_INFO("Loading R100 Microcode\n");
334 for (i = 0; i < 256; i++) {
335 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
336 R100_cp_microcode[i][1]);
337 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
338 R100_cp_microcode[i][0]);
339 }
340 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
341 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
342 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
343 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
344 DRM_INFO("Loading R200 Microcode\n");
345 for (i = 0; i < 256; i++) {
346 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
347 R200_cp_microcode[i][1]);
348 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
349 R200_cp_microcode[i][0]);
350 }
351 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
352 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
353 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
356 DRM_INFO("Loading R300 Microcode\n");
357 for (i = 0; i < 256; i++) {
358 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
359 R300_cp_microcode[i][1]);
360 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
361 R300_cp_microcode[i][0]);
362 }
363 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
364 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
365 DRM_INFO("Loading R400 Microcode\n");
366 for (i = 0; i < 256; i++) {
367 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
368 R420_cp_microcode[i][1]);
369 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
370 R420_cp_microcode[i][0]);
371 }
372 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
373 DRM_INFO("Loading RS690 Microcode\n");
374 for (i = 0; i < 256; i++) {
375 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
376 RS690_cp_microcode[i][1]);
377 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
378 RS690_cp_microcode[i][0]);
379 }
380 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
381 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
382 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
383 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
384 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
385 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
386 DRM_INFO("Loading R500 Microcode\n");
387 for (i = 0; i < 256; i++) {
388 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
389 R520_cp_microcode[i][1]);
390 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
391 R520_cp_microcode[i][0]);
392 }
393 }
394 }
395
396 /* Flush any pending commands to the CP. This should only be used just
397 * prior to a wait for idle, as it informs the engine that the command
398 * stream is ending.
399 */
400 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
401 {
402 DRM_DEBUG("\n");
403 #if 0
404 u32 tmp;
405
406 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
407 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
408 #endif
409 }
410
411 /* Wait for the CP to go idle.
412 */
413 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
414 {
415 RING_LOCALS;
416 DRM_DEBUG("\n");
417
418 BEGIN_RING(6);
419
420 RADEON_PURGE_CACHE();
421 RADEON_PURGE_ZCACHE();
422 RADEON_WAIT_UNTIL_IDLE();
423
424 ADVANCE_RING();
425 COMMIT_RING();
426
427 return radeon_do_wait_for_idle(dev_priv);
428 }
429
430 /* Start the Command Processor.
431 */
432 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
433 {
434 RING_LOCALS;
435 DRM_DEBUG("\n");
436
437 radeon_do_wait_for_idle(dev_priv);
438
439 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
440
441 dev_priv->cp_running = 1;
442
443 BEGIN_RING(6);
444
445 RADEON_PURGE_CACHE();
446 RADEON_PURGE_ZCACHE();
447 RADEON_WAIT_UNTIL_IDLE();
448
449 ADVANCE_RING();
450 COMMIT_RING();
451 }
452
453 /* Reset the Command Processor. This will not flush any pending
454 * commands, so you must wait for the CP command stream to complete
455 * before calling this routine.
456 */
457 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
458 {
459 u32 cur_read_ptr;
460 DRM_DEBUG("\n");
461
462 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
463 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
464 SET_RING_HEAD(dev_priv, cur_read_ptr);
465 dev_priv->ring.tail = cur_read_ptr;
466 }
467
468 /* Stop the Command Processor. This will not flush any pending
469 * commands, so you must flush the command stream and wait for the CP
470 * to go idle before calling this routine.
471 */
472 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
473 {
474 DRM_DEBUG("\n");
475
476 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
477
478 dev_priv->cp_running = 0;
479 }
480
481 /* Reset the engine. This will stop the CP if it is running.
482 */
483 static int radeon_do_engine_reset(struct drm_device * dev)
484 {
485 drm_radeon_private_t *dev_priv = dev->dev_private;
486 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
487 DRM_DEBUG("\n");
488
489 radeon_do_pixcache_flush(dev_priv);
490
491 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
492 /* may need something similar for newer chips */
493 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
494 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
495
496 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
497 RADEON_FORCEON_MCLKA |
498 RADEON_FORCEON_MCLKB |
499 RADEON_FORCEON_YCLKA |
500 RADEON_FORCEON_YCLKB |
501 RADEON_FORCEON_MC |
502 RADEON_FORCEON_AIC));
503 }
504
505 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
506
507 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
508 RADEON_SOFT_RESET_CP |
509 RADEON_SOFT_RESET_HI |
510 RADEON_SOFT_RESET_SE |
511 RADEON_SOFT_RESET_RE |
512 RADEON_SOFT_RESET_PP |
513 RADEON_SOFT_RESET_E2 |
514 RADEON_SOFT_RESET_RB));
515 RADEON_READ(RADEON_RBBM_SOFT_RESET);
516 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
517 ~(RADEON_SOFT_RESET_CP |
518 RADEON_SOFT_RESET_HI |
519 RADEON_SOFT_RESET_SE |
520 RADEON_SOFT_RESET_RE |
521 RADEON_SOFT_RESET_PP |
522 RADEON_SOFT_RESET_E2 |
523 RADEON_SOFT_RESET_RB)));
524 RADEON_READ(RADEON_RBBM_SOFT_RESET);
525
526 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
527 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
528 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
529 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
530 }
531
532 /* setup the raster pipes */
533 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
534 radeon_init_pipes(dev_priv);
535
536 /* Reset the CP ring */
537 radeon_do_cp_reset(dev_priv);
538
539 /* The CP is no longer running after an engine reset */
540 dev_priv->cp_running = 0;
541
542 /* Reset any pending vertex, indirect buffers */
543 radeon_freelist_reset(dev);
544
545 return 0;
546 }
547
548 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
549 drm_radeon_private_t * dev_priv)
550 {
551 u32 ring_start, cur_read_ptr;
552 u32 tmp;
553
554 /* Initialize the memory controller. With new memory map, the fb location
555 * is not changed, it should have been properly initialized already. Part
556 * of the problem is that the code below is bogus, assuming the GART is
557 * always appended to the fb which is not necessarily the case
558 */
559 if (!dev_priv->new_memmap)
560 radeon_write_fb_location(dev_priv,
561 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
562 | (dev_priv->fb_location >> 16));
563
564 #if __OS_HAS_AGP
565 if (dev_priv->flags & RADEON_IS_AGP) {
566 radeon_write_agp_base(dev_priv, dev->agp->base);
567
568 radeon_write_agp_location(dev_priv,
569 (((dev_priv->gart_vm_start - 1 +
570 dev_priv->gart_size) & 0xffff0000) |
571 (dev_priv->gart_vm_start >> 16)));
572
573 ring_start = (dev_priv->cp_ring->offset
574 - dev->agp->base
575 + dev_priv->gart_vm_start);
576 } else
577 #endif
578 ring_start = (dev_priv->cp_ring->offset
579 - (unsigned long)dev->sg->virtual
580 + dev_priv->gart_vm_start);
581
582 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
583
584 /* Set the write pointer delay */
585 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
586
587 /* Initialize the ring buffer's read and write pointers */
588 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
589 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
590 SET_RING_HEAD(dev_priv, cur_read_ptr);
591 dev_priv->ring.tail = cur_read_ptr;
592
593 #if __OS_HAS_AGP
594 if (dev_priv->flags & RADEON_IS_AGP) {
595 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
596 dev_priv->ring_rptr->offset
597 - dev->agp->base + dev_priv->gart_vm_start);
598 } else
599 #endif
600 {
601 struct drm_sg_mem *entry = dev->sg;
602 unsigned long tmp_ofs, page_ofs;
603
604 tmp_ofs = dev_priv->ring_rptr->offset -
605 (unsigned long)dev->sg->virtual;
606 page_ofs = tmp_ofs >> PAGE_SHIFT;
607
608 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
609 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
610 (unsigned long)entry->busaddr[page_ofs],
611 entry->handle + tmp_ofs);
612 }
613
614 /* Set ring buffer size */
615 #ifdef __BIG_ENDIAN
616 RADEON_WRITE(RADEON_CP_RB_CNTL,
617 RADEON_BUF_SWAP_32BIT |
618 (dev_priv->ring.fetch_size_l2ow << 18) |
619 (dev_priv->ring.rptr_update_l2qw << 8) |
620 dev_priv->ring.size_l2qw);
621 #else
622 RADEON_WRITE(RADEON_CP_RB_CNTL,
623 (dev_priv->ring.fetch_size_l2ow << 18) |
624 (dev_priv->ring.rptr_update_l2qw << 8) |
625 dev_priv->ring.size_l2qw);
626 #endif
627
628 /* Start with assuming that writeback doesn't work */
629 dev_priv->writeback_works = 0;
630
631 /* Initialize the scratch register pointer. This will cause
632 * the scratch register values to be written out to memory
633 * whenever they are updated.
634 *
635 * We simply put this behind the ring read pointer, this works
636 * with PCI GART as well as (whatever kind of) AGP GART
637 */
638 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
639 + RADEON_SCRATCH_REG_OFFSET);
640
641 dev_priv->scratch = ((__volatile__ u32 *)
642 dev_priv->ring_rptr->handle +
643 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
644
645 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
646
647 /* Turn on bus mastering */
648 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
649 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
650
651 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
652 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
653
654 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
655 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
656 dev_priv->sarea_priv->last_dispatch);
657
658 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
659 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
660
661 radeon_do_wait_for_idle(dev_priv);
662
663 /* Sync everything up */
664 RADEON_WRITE(RADEON_ISYNC_CNTL,
665 (RADEON_ISYNC_ANY2D_IDLE3D |
666 RADEON_ISYNC_ANY3D_IDLE2D |
667 RADEON_ISYNC_WAIT_IDLEGUI |
668 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
669
670 }
671
672 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
673 {
674 u32 tmp;
675
676 /* Writeback doesn't seem to work everywhere, test it here and possibly
677 * enable it if it appears to work
678 */
679 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
680 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
681
682 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
683 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
684 0xdeadbeef)
685 break;
686 DRM_UDELAY(1);
687 }
688
689 if (tmp < dev_priv->usec_timeout) {
690 dev_priv->writeback_works = 1;
691 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
692 } else {
693 dev_priv->writeback_works = 0;
694 DRM_INFO("writeback test failed\n");
695 }
696 if (radeon_no_wb == 1) {
697 dev_priv->writeback_works = 0;
698 DRM_INFO("writeback forced off\n");
699 }
700
701 if (!dev_priv->writeback_works) {
702 /* Disable writeback to avoid unnecessary bus master transfer */
703 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
704 RADEON_RB_NO_UPDATE);
705 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
706 }
707 }
708
709 /* Enable or disable IGP GART on the chip */
710 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
711 {
712 u32 temp;
713
714 if (on) {
715 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
716 dev_priv->gart_vm_start,
717 (long)dev_priv->gart_info.bus_addr,
718 dev_priv->gart_size);
719
720 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
721 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
722 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
723 RS690_BLOCK_GFX_D3_EN));
724 else
725 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
726
727 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
728 RS480_VA_SIZE_32MB));
729
730 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
731 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
732 RS480_TLB_ENABLE |
733 RS480_GTW_LAC_EN |
734 RS480_1LEVEL_GART));
735
736 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
737 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
738 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
739
740 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
741 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
742 RS480_REQ_TYPE_SNOOP_DIS));
743
744 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
745 IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
746 (unsigned int)dev_priv->gart_vm_start);
747 IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
748 } else {
749 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
750 RADEON_WRITE(RS480_AGP_BASE_2, 0);
751 }
752
753 dev_priv->gart_size = 32*1024*1024;
754 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
755 0xffff0000) | (dev_priv->gart_vm_start >> 16));
756
757 radeon_write_agp_location(dev_priv, temp);
758
759 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
760 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
761 RS480_VA_SIZE_32MB));
762
763 do {
764 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
765 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
766 break;
767 DRM_UDELAY(1);
768 } while (1);
769
770 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
771 RS480_GART_CACHE_INVALIDATE);
772
773 do {
774 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
775 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
776 break;
777 DRM_UDELAY(1);
778 } while (1);
779
780 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
781 } else {
782 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
783 }
784 }
785
786 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
787 {
788 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
789 if (on) {
790
791 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
792 dev_priv->gart_vm_start,
793 (long)dev_priv->gart_info.bus_addr,
794 dev_priv->gart_size);
795 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
796 dev_priv->gart_vm_start);
797 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
798 dev_priv->gart_info.bus_addr);
799 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
800 dev_priv->gart_vm_start);
801 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
802 dev_priv->gart_vm_start +
803 dev_priv->gart_size - 1);
804
805 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
806
807 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
808 RADEON_PCIE_TX_GART_EN);
809 } else {
810 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
811 tmp & ~RADEON_PCIE_TX_GART_EN);
812 }
813 }
814
815 /* Enable or disable PCI GART on the chip */
816 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
817 {
818 u32 tmp;
819
820 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
821 (dev_priv->flags & RADEON_IS_IGPGART)) {
822 radeon_set_igpgart(dev_priv, on);
823 return;
824 }
825
826 if (dev_priv->flags & RADEON_IS_PCIE) {
827 radeon_set_pciegart(dev_priv, on);
828 return;
829 }
830
831 tmp = RADEON_READ(RADEON_AIC_CNTL);
832
833 if (on) {
834 RADEON_WRITE(RADEON_AIC_CNTL,
835 tmp | RADEON_PCIGART_TRANSLATE_EN);
836
837 /* set PCI GART page-table base address
838 */
839 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
840
841 /* set address range for PCI address translate
842 */
843 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
844 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
845 + dev_priv->gart_size - 1);
846
847 /* Turn off AGP aperture -- is this required for PCI GART?
848 */
849 radeon_write_agp_location(dev_priv, 0xffffffc0);
850 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
851 } else {
852 RADEON_WRITE(RADEON_AIC_CNTL,
853 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
854 }
855 }
856
857 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
858 {
859 drm_radeon_private_t *dev_priv = dev->dev_private;
860
861 DRM_DEBUG("\n");
862
863 /* if we require new memory map but we don't have it fail */
864 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
865 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
866 radeon_do_cleanup_cp(dev);
867 return -EINVAL;
868 }
869
870 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
871 DRM_DEBUG("Forcing AGP card to PCI mode\n");
872 dev_priv->flags &= ~RADEON_IS_AGP;
873 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
874 && !init->is_pci) {
875 DRM_DEBUG("Restoring AGP flag\n");
876 dev_priv->flags |= RADEON_IS_AGP;
877 }
878
879 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
880 DRM_ERROR("PCI GART memory not allocated!\n");
881 radeon_do_cleanup_cp(dev);
882 return -EINVAL;
883 }
884
885 dev_priv->usec_timeout = init->usec_timeout;
886 if (dev_priv->usec_timeout < 1 ||
887 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
888 DRM_DEBUG("TIMEOUT problem!\n");
889 radeon_do_cleanup_cp(dev);
890 return -EINVAL;
891 }
892
893 /* Enable vblank on CRTC1 for older X servers
894 */
895 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
896
897 switch(init->func) {
898 case RADEON_INIT_R200_CP:
899 dev_priv->microcode_version = UCODE_R200;
900 break;
901 case RADEON_INIT_R300_CP:
902 dev_priv->microcode_version = UCODE_R300;
903 break;
904 default:
905 dev_priv->microcode_version = UCODE_R100;
906 }
907
908 dev_priv->do_boxes = 0;
909 dev_priv->cp_mode = init->cp_mode;
910
911 /* We don't support anything other than bus-mastering ring mode,
912 * but the ring can be in either AGP or PCI space for the ring
913 * read pointer.
914 */
915 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
916 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
917 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
918 radeon_do_cleanup_cp(dev);
919 return -EINVAL;
920 }
921
922 switch (init->fb_bpp) {
923 case 16:
924 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
925 break;
926 case 32:
927 default:
928 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
929 break;
930 }
931 dev_priv->front_offset = init->front_offset;
932 dev_priv->front_pitch = init->front_pitch;
933 dev_priv->back_offset = init->back_offset;
934 dev_priv->back_pitch = init->back_pitch;
935
936 switch (init->depth_bpp) {
937 case 16:
938 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
939 break;
940 case 32:
941 default:
942 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
943 break;
944 }
945 dev_priv->depth_offset = init->depth_offset;
946 dev_priv->depth_pitch = init->depth_pitch;
947
948 /* Hardware state for depth clears. Remove this if/when we no
949 * longer clear the depth buffer with a 3D rectangle. Hard-code
950 * all values to prevent unwanted 3D state from slipping through
951 * and screwing with the clear operation.
952 */
953 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
954 (dev_priv->color_fmt << 10) |
955 (dev_priv->microcode_version ==
956 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
957
958 dev_priv->depth_clear.rb3d_zstencilcntl =
959 (dev_priv->depth_fmt |
960 RADEON_Z_TEST_ALWAYS |
961 RADEON_STENCIL_TEST_ALWAYS |
962 RADEON_STENCIL_S_FAIL_REPLACE |
963 RADEON_STENCIL_ZPASS_REPLACE |
964 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
965
966 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
967 RADEON_BFACE_SOLID |
968 RADEON_FFACE_SOLID |
969 RADEON_FLAT_SHADE_VTX_LAST |
970 RADEON_DIFFUSE_SHADE_FLAT |
971 RADEON_ALPHA_SHADE_FLAT |
972 RADEON_SPECULAR_SHADE_FLAT |
973 RADEON_FOG_SHADE_FLAT |
974 RADEON_VTX_PIX_CENTER_OGL |
975 RADEON_ROUND_MODE_TRUNC |
976 RADEON_ROUND_PREC_8TH_PIX);
977
978
979 dev_priv->ring_offset = init->ring_offset;
980 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
981 dev_priv->buffers_offset = init->buffers_offset;
982 dev_priv->gart_textures_offset = init->gart_textures_offset;
983
984 dev_priv->sarea = drm_getsarea(dev);
985 if (!dev_priv->sarea) {
986 DRM_ERROR("could not find sarea!\n");
987 radeon_do_cleanup_cp(dev);
988 return -EINVAL;
989 }
990
991 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
992 if (!dev_priv->cp_ring) {
993 DRM_ERROR("could not find cp ring region!\n");
994 radeon_do_cleanup_cp(dev);
995 return -EINVAL;
996 }
997 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
998 if (!dev_priv->ring_rptr) {
999 DRM_ERROR("could not find ring read pointer!\n");
1000 radeon_do_cleanup_cp(dev);
1001 return -EINVAL;
1002 }
1003 dev->agp_buffer_token = init->buffers_offset;
1004 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1005 if (!dev->agp_buffer_map) {
1006 DRM_ERROR("could not find dma buffer region!\n");
1007 radeon_do_cleanup_cp(dev);
1008 return -EINVAL;
1009 }
1010
1011 if (init->gart_textures_offset) {
1012 dev_priv->gart_textures =
1013 drm_core_findmap(dev, init->gart_textures_offset);
1014 if (!dev_priv->gart_textures) {
1015 DRM_ERROR("could not find GART texture region!\n");
1016 radeon_do_cleanup_cp(dev);
1017 return -EINVAL;
1018 }
1019 }
1020
1021 dev_priv->sarea_priv =
1022 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1023 init->sarea_priv_offset);
1024
1025 #if __OS_HAS_AGP
1026 if (dev_priv->flags & RADEON_IS_AGP) {
1027 drm_core_ioremap(dev_priv->cp_ring, dev);
1028 drm_core_ioremap(dev_priv->ring_rptr, dev);
1029 drm_core_ioremap(dev->agp_buffer_map, dev);
1030 if (!dev_priv->cp_ring->handle ||
1031 !dev_priv->ring_rptr->handle ||
1032 !dev->agp_buffer_map->handle) {
1033 DRM_ERROR("could not find ioremap agp regions!\n");
1034 radeon_do_cleanup_cp(dev);
1035 return -EINVAL;
1036 }
1037 } else
1038 #endif
1039 {
1040 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1041 dev_priv->ring_rptr->handle =
1042 (void *)dev_priv->ring_rptr->offset;
1043 dev->agp_buffer_map->handle =
1044 (void *)dev->agp_buffer_map->offset;
1045
1046 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1047 dev_priv->cp_ring->handle);
1048 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1049 dev_priv->ring_rptr->handle);
1050 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1051 dev->agp_buffer_map->handle);
1052 }
1053
1054 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1055 dev_priv->fb_size =
1056 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1057 - dev_priv->fb_location;
1058
1059 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1060 ((dev_priv->front_offset
1061 + dev_priv->fb_location) >> 10));
1062
1063 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1064 ((dev_priv->back_offset
1065 + dev_priv->fb_location) >> 10));
1066
1067 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1068 ((dev_priv->depth_offset
1069 + dev_priv->fb_location) >> 10));
1070
1071 dev_priv->gart_size = init->gart_size;
1072
1073 /* New let's set the memory map ... */
1074 if (dev_priv->new_memmap) {
1075 u32 base = 0;
1076
1077 DRM_INFO("Setting GART location based on new memory map\n");
1078
1079 /* If using AGP, try to locate the AGP aperture at the same
1080 * location in the card and on the bus, though we have to
1081 * align it down.
1082 */
1083 #if __OS_HAS_AGP
1084 if (dev_priv->flags & RADEON_IS_AGP) {
1085 base = dev->agp->base;
1086 /* Check if valid */
1087 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1088 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1089 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1090 dev->agp->base);
1091 base = 0;
1092 }
1093 }
1094 #endif
1095 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1096 if (base == 0) {
1097 base = dev_priv->fb_location + dev_priv->fb_size;
1098 if (base < dev_priv->fb_location ||
1099 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1100 base = dev_priv->fb_location
1101 - dev_priv->gart_size;
1102 }
1103 dev_priv->gart_vm_start = base & 0xffc00000u;
1104 if (dev_priv->gart_vm_start != base)
1105 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1106 base, dev_priv->gart_vm_start);
1107 } else {
1108 DRM_INFO("Setting GART location based on old memory map\n");
1109 dev_priv->gart_vm_start = dev_priv->fb_location +
1110 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1111 }
1112
1113 #if __OS_HAS_AGP
1114 if (dev_priv->flags & RADEON_IS_AGP)
1115 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1116 - dev->agp->base
1117 + dev_priv->gart_vm_start);
1118 else
1119 #endif
1120 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1121 - (unsigned long)dev->sg->virtual
1122 + dev_priv->gart_vm_start);
1123
1124 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1125 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1126 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1127 dev_priv->gart_buffers_offset);
1128
1129 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1130 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1131 + init->ring_size / sizeof(u32));
1132 dev_priv->ring.size = init->ring_size;
1133 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1134
1135 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1136 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1137
1138 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1139 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1140 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1141
1142 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1143
1144 #if __OS_HAS_AGP
1145 if (dev_priv->flags & RADEON_IS_AGP) {
1146 /* Turn off PCI GART */
1147 radeon_set_pcigart(dev_priv, 0);
1148 } else
1149 #endif
1150 {
1151 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1152 /* if we have an offset set from userspace */
1153 if (dev_priv->pcigart_offset_set) {
1154 dev_priv->gart_info.bus_addr =
1155 dev_priv->pcigart_offset + dev_priv->fb_location;
1156 dev_priv->gart_info.mapping.offset =
1157 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1158 dev_priv->gart_info.mapping.size =
1159 dev_priv->gart_info.table_size;
1160
1161 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1162 dev_priv->gart_info.addr =
1163 dev_priv->gart_info.mapping.handle;
1164
1165 if (dev_priv->flags & RADEON_IS_PCIE)
1166 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1167 else
1168 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1169 dev_priv->gart_info.gart_table_location =
1170 DRM_ATI_GART_FB;
1171
1172 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1173 dev_priv->gart_info.addr,
1174 dev_priv->pcigart_offset);
1175 } else {
1176 if (dev_priv->flags & RADEON_IS_IGPGART)
1177 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1178 else
1179 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1180 dev_priv->gart_info.gart_table_location =
1181 DRM_ATI_GART_MAIN;
1182 dev_priv->gart_info.addr = NULL;
1183 dev_priv->gart_info.bus_addr = 0;
1184 if (dev_priv->flags & RADEON_IS_PCIE) {
1185 DRM_ERROR
1186 ("Cannot use PCI Express without GART in FB memory\n");
1187 radeon_do_cleanup_cp(dev);
1188 return -EINVAL;
1189 }
1190 }
1191
1192 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1193 DRM_ERROR("failed to init PCI GART!\n");
1194 radeon_do_cleanup_cp(dev);
1195 return -ENOMEM;
1196 }
1197
1198 /* Turn on PCI GART */
1199 radeon_set_pcigart(dev_priv, 1);
1200 }
1201
1202 radeon_cp_load_microcode(dev_priv);
1203 radeon_cp_init_ring_buffer(dev, dev_priv);
1204
1205 dev_priv->last_buf = 0;
1206
1207 radeon_do_engine_reset(dev);
1208 radeon_test_writeback(dev_priv);
1209
1210 return 0;
1211 }
1212
1213 static int radeon_do_cleanup_cp(struct drm_device * dev)
1214 {
1215 drm_radeon_private_t *dev_priv = dev->dev_private;
1216 DRM_DEBUG("\n");
1217
1218 /* Make sure interrupts are disabled here because the uninstall ioctl
1219 * may not have been called from userspace and after dev_private
1220 * is freed, it's too late.
1221 */
1222 if (dev->irq_enabled)
1223 drm_irq_uninstall(dev);
1224
1225 #if __OS_HAS_AGP
1226 if (dev_priv->flags & RADEON_IS_AGP) {
1227 if (dev_priv->cp_ring != NULL) {
1228 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1229 dev_priv->cp_ring = NULL;
1230 }
1231 if (dev_priv->ring_rptr != NULL) {
1232 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1233 dev_priv->ring_rptr = NULL;
1234 }
1235 if (dev->agp_buffer_map != NULL) {
1236 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1237 dev->agp_buffer_map = NULL;
1238 }
1239 } else
1240 #endif
1241 {
1242
1243 if (dev_priv->gart_info.bus_addr) {
1244 /* Turn off PCI GART */
1245 radeon_set_pcigart(dev_priv, 0);
1246 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1247 DRM_ERROR("failed to cleanup PCI GART!\n");
1248 }
1249
1250 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1251 {
1252 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1253 dev_priv->gart_info.addr = 0;
1254 }
1255 }
1256 /* only clear to the start of flags */
1257 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1258
1259 return 0;
1260 }
1261
1262 /* This code will reinit the Radeon CP hardware after a resume from disc.
1263 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1264 * here we make sure that all Radeon hardware initialisation is re-done without
1265 * affecting running applications.
1266 *
1267 * Charl P. Botha <http://cpbotha.net>
1268 */
1269 static int radeon_do_resume_cp(struct drm_device * dev)
1270 {
1271 drm_radeon_private_t *dev_priv = dev->dev_private;
1272
1273 if (!dev_priv) {
1274 DRM_ERROR("Called with no initialization\n");
1275 return -EINVAL;
1276 }
1277
1278 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1279
1280 #if __OS_HAS_AGP
1281 if (dev_priv->flags & RADEON_IS_AGP) {
1282 /* Turn off PCI GART */
1283 radeon_set_pcigart(dev_priv, 0);
1284 } else
1285 #endif
1286 {
1287 /* Turn on PCI GART */
1288 radeon_set_pcigart(dev_priv, 1);
1289 }
1290
1291 radeon_cp_load_microcode(dev_priv);
1292 radeon_cp_init_ring_buffer(dev, dev_priv);
1293
1294 radeon_do_engine_reset(dev);
1295
1296 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1297
1298 return 0;
1299 }
1300
1301 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1302 {
1303 drm_radeon_init_t *init = data;
1304
1305 LOCK_TEST_WITH_RETURN(dev, file_priv);
1306
1307 if (init->func == RADEON_INIT_R300_CP)
1308 r300_init_reg_flags(dev);
1309
1310 switch (init->func) {
1311 case RADEON_INIT_CP:
1312 case RADEON_INIT_R200_CP:
1313 case RADEON_INIT_R300_CP:
1314 return radeon_do_init_cp(dev, init);
1315 case RADEON_CLEANUP_CP:
1316 return radeon_do_cleanup_cp(dev);
1317 }
1318
1319 return -EINVAL;
1320 }
1321
1322 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1323 {
1324 drm_radeon_private_t *dev_priv = dev->dev_private;
1325 DRM_DEBUG("\n");
1326
1327 LOCK_TEST_WITH_RETURN(dev, file_priv);
1328
1329 if (dev_priv->cp_running) {
1330 DRM_DEBUG("while CP running\n");
1331 return 0;
1332 }
1333 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1334 DRM_DEBUG("called with bogus CP mode (%d)\n",
1335 dev_priv->cp_mode);
1336 return 0;
1337 }
1338
1339 radeon_do_cp_start(dev_priv);
1340
1341 return 0;
1342 }
1343
1344 /* Stop the CP. The engine must have been idled before calling this
1345 * routine.
1346 */
1347 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1348 {
1349 drm_radeon_private_t *dev_priv = dev->dev_private;
1350 drm_radeon_cp_stop_t *stop = data;
1351 int ret;
1352 DRM_DEBUG("\n");
1353
1354 LOCK_TEST_WITH_RETURN(dev, file_priv);
1355
1356 if (!dev_priv->cp_running)
1357 return 0;
1358
1359 /* Flush any pending CP commands. This ensures any outstanding
1360 * commands are exectuted by the engine before we turn it off.
1361 */
1362 if (stop->flush) {
1363 radeon_do_cp_flush(dev_priv);
1364 }
1365
1366 /* If we fail to make the engine go idle, we return an error
1367 * code so that the DRM ioctl wrapper can try again.
1368 */
1369 if (stop->idle) {
1370 ret = radeon_do_cp_idle(dev_priv);
1371 if (ret)
1372 return ret;
1373 }
1374
1375 /* Finally, we can turn off the CP. If the engine isn't idle,
1376 * we will get some dropped triangles as they won't be fully
1377 * rendered before the CP is shut down.
1378 */
1379 radeon_do_cp_stop(dev_priv);
1380
1381 /* Reset the engine */
1382 radeon_do_engine_reset(dev);
1383
1384 return 0;
1385 }
1386
1387 void radeon_do_release(struct drm_device * dev)
1388 {
1389 drm_radeon_private_t *dev_priv = dev->dev_private;
1390 int i, ret;
1391
1392 if (dev_priv) {
1393 if (dev_priv->cp_running) {
1394 /* Stop the cp */
1395 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1396 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1397 #ifdef __linux__
1398 schedule();
1399 #else
1400 tsleep(&ret, PZERO, "rdnrel", 1);
1401 #endif
1402 }
1403 radeon_do_cp_stop(dev_priv);
1404 radeon_do_engine_reset(dev);
1405 }
1406
1407 /* Disable *all* interrupts */
1408 if (dev_priv->mmio) /* remove this after permanent addmaps */
1409 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1410
1411 if (dev_priv->mmio) { /* remove all surfaces */
1412 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1413 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1414 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1415 16 * i, 0);
1416 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1417 16 * i, 0);
1418 }
1419 }
1420
1421 /* Free memory heap structures */
1422 radeon_mem_takedown(&(dev_priv->gart_heap));
1423 radeon_mem_takedown(&(dev_priv->fb_heap));
1424
1425 /* deallocate kernel resources */
1426 radeon_do_cleanup_cp(dev);
1427 }
1428 }
1429
1430 /* Just reset the CP ring. Called as part of an X Server engine reset.
1431 */
1432 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1433 {
1434 drm_radeon_private_t *dev_priv = dev->dev_private;
1435 DRM_DEBUG("\n");
1436
1437 LOCK_TEST_WITH_RETURN(dev, file_priv);
1438
1439 if (!dev_priv) {
1440 DRM_DEBUG("called before init done\n");
1441 return -EINVAL;
1442 }
1443
1444 radeon_do_cp_reset(dev_priv);
1445
1446 /* The CP is no longer running after an engine reset */
1447 dev_priv->cp_running = 0;
1448
1449 return 0;
1450 }
1451
1452 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1453 {
1454 drm_radeon_private_t *dev_priv = dev->dev_private;
1455 DRM_DEBUG("\n");
1456
1457 LOCK_TEST_WITH_RETURN(dev, file_priv);
1458
1459 return radeon_do_cp_idle(dev_priv);
1460 }
1461
1462 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1463 */
1464 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1465 {
1466
1467 return radeon_do_resume_cp(dev);
1468 }
1469
1470 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1471 {
1472 DRM_DEBUG("\n");
1473
1474 LOCK_TEST_WITH_RETURN(dev, file_priv);
1475
1476 return radeon_do_engine_reset(dev);
1477 }
1478
1479 /* ================================================================
1480 * Fullscreen mode
1481 */
1482
1483 /* KW: Deprecated to say the least:
1484 */
1485 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1486 {
1487 return 0;
1488 }
1489
1490 /* ================================================================
1491 * Freelist management
1492 */
1493
1494 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1495 * bufs until freelist code is used. Note this hides a problem with
1496 * the scratch register * (used to keep track of last buffer
1497 * completed) being written to before * the last buffer has actually
1498 * completed rendering.
1499 *
1500 * KW: It's also a good way to find free buffers quickly.
1501 *
1502 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1503 * sleep. However, bugs in older versions of radeon_accel.c mean that
1504 * we essentially have to do this, else old clients will break.
1505 *
1506 * However, it does leave open a potential deadlock where all the
1507 * buffers are held by other clients, which can't release them because
1508 * they can't get the lock.
1509 */
1510
1511 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1512 {
1513 struct drm_device_dma *dma = dev->dma;
1514 drm_radeon_private_t *dev_priv = dev->dev_private;
1515 drm_radeon_buf_priv_t *buf_priv;
1516 struct drm_buf *buf;
1517 int i, t;
1518 int start;
1519
1520 if (++dev_priv->last_buf >= dma->buf_count)
1521 dev_priv->last_buf = 0;
1522
1523 start = dev_priv->last_buf;
1524
1525 for (t = 0; t < dev_priv->usec_timeout; t++) {
1526 u32 done_age = GET_SCRATCH(1);
1527 DRM_DEBUG("done_age = %d\n", done_age);
1528 for (i = start; i < dma->buf_count; i++) {
1529 buf = dma->buflist[i];
1530 buf_priv = buf->dev_private;
1531 if (buf->file_priv == NULL || (buf->pending &&
1532 buf_priv->age <=
1533 done_age)) {
1534 dev_priv->stats.requested_bufs++;
1535 buf->pending = 0;
1536 return buf;
1537 }
1538 start = 0;
1539 }
1540
1541 if (t) {
1542 DRM_UDELAY(1);
1543 dev_priv->stats.freelist_loops++;
1544 }
1545 }
1546
1547 DRM_DEBUG("returning NULL!\n");
1548 return NULL;
1549 }
1550
1551 #if 0
1552 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1553 {
1554 struct drm_device_dma *dma = dev->dma;
1555 drm_radeon_private_t *dev_priv = dev->dev_private;
1556 drm_radeon_buf_priv_t *buf_priv;
1557 struct drm_buf *buf;
1558 int i, t;
1559 int start;
1560 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1561
1562 if (++dev_priv->last_buf >= dma->buf_count)
1563 dev_priv->last_buf = 0;
1564
1565 start = dev_priv->last_buf;
1566 dev_priv->stats.freelist_loops++;
1567
1568 for (t = 0; t < 2; t++) {
1569 for (i = start; i < dma->buf_count; i++) {
1570 buf = dma->buflist[i];
1571 buf_priv = buf->dev_private;
1572 if (buf->file_priv == 0 || (buf->pending &&
1573 buf_priv->age <=
1574 done_age)) {
1575 dev_priv->stats.requested_bufs++;
1576 buf->pending = 0;
1577 return buf;
1578 }
1579 }
1580 start = 0;
1581 }
1582
1583 return NULL;
1584 }
1585 #endif
1586
1587 void radeon_freelist_reset(struct drm_device * dev)
1588 {
1589 struct drm_device_dma *dma = dev->dma;
1590 drm_radeon_private_t *dev_priv = dev->dev_private;
1591 int i;
1592
1593 dev_priv->last_buf = 0;
1594 for (i = 0; i < dma->buf_count; i++) {
1595 struct drm_buf *buf = dma->buflist[i];
1596 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1597 buf_priv->age = 0;
1598 }
1599 }
1600
1601 /* ================================================================
1602 * CP command submission
1603 */
1604
1605 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1606 {
1607 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1608 int i;
1609 u32 last_head = GET_RING_HEAD(dev_priv);
1610
1611 for (i = 0; i < dev_priv->usec_timeout; i++) {
1612 u32 head = GET_RING_HEAD(dev_priv);
1613
1614 ring->space = (head - ring->tail) * sizeof(u32);
1615 if (ring->space <= 0)
1616 ring->space += ring->size;
1617 if (ring->space > n)
1618 return 0;
1619
1620 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1621
1622 if (head != last_head)
1623 i = 0;
1624 last_head = head;
1625
1626 DRM_UDELAY(1);
1627 }
1628
1629 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1630 #if RADEON_FIFO_DEBUG
1631 radeon_status(dev_priv);
1632 DRM_ERROR("failed!\n");
1633 #endif
1634 return -EBUSY;
1635 }
1636
1637 static int radeon_cp_get_buffers(struct drm_device *dev,
1638 struct drm_file *file_priv,
1639 struct drm_dma * d)
1640 {
1641 int i;
1642 struct drm_buf *buf;
1643
1644 for (i = d->granted_count; i < d->request_count; i++) {
1645 buf = radeon_freelist_get(dev);
1646 if (!buf)
1647 return -EBUSY; /* NOTE: broken client */
1648
1649 buf->file_priv = file_priv;
1650
1651 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1652 sizeof(buf->idx)))
1653 return -EFAULT;
1654 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1655 sizeof(buf->total)))
1656 return -EFAULT;
1657
1658 d->granted_count++;
1659 }
1660 return 0;
1661 }
1662
1663 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1664 {
1665 struct drm_device_dma *dma = dev->dma;
1666 int ret = 0;
1667 struct drm_dma *d = data;
1668
1669 LOCK_TEST_WITH_RETURN(dev, file_priv);
1670
1671 /* Please don't send us buffers.
1672 */
1673 if (d->send_count != 0) {
1674 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1675 DRM_CURRENTPID, d->send_count);
1676 return -EINVAL;
1677 }
1678
1679 /* We'll send you buffers.
1680 */
1681 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1682 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1683 DRM_CURRENTPID, d->request_count, dma->buf_count);
1684 return -EINVAL;
1685 }
1686
1687 d->granted_count = 0;
1688
1689 if (d->request_count) {
1690 ret = radeon_cp_get_buffers(dev, file_priv, d);
1691 }
1692
1693 return ret;
1694 }
1695
1696 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1697 {
1698 drm_radeon_private_t *dev_priv;
1699 int ret = 0;
1700
1701 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1702 if (dev_priv == NULL)
1703 return -ENOMEM;
1704
1705 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1706 dev->dev_private = (void *)dev_priv;
1707 dev_priv->flags = flags;
1708
1709 switch (flags & RADEON_FAMILY_MASK) {
1710 case CHIP_R100:
1711 case CHIP_RV200:
1712 case CHIP_R200:
1713 case CHIP_R300:
1714 case CHIP_R350:
1715 case CHIP_R420:
1716 case CHIP_RV410:
1717 case CHIP_RV515:
1718 case CHIP_R520:
1719 case CHIP_RV570:
1720 case CHIP_R580:
1721 dev_priv->flags |= RADEON_HAS_HIERZ;
1722 break;
1723 default:
1724 /* all other chips have no hierarchical z buffer */
1725 break;
1726 }
1727
1728 if (drm_device_is_agp(dev))
1729 dev_priv->flags |= RADEON_IS_AGP;
1730 else if (drm_device_is_pcie(dev))
1731 dev_priv->flags |= RADEON_IS_PCIE;
1732 else
1733 dev_priv->flags |= RADEON_IS_PCI;
1734
1735 DRM_DEBUG("%s card detected\n",
1736 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1737 return ret;
1738 }
1739
1740 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1741 * have to find them.
1742 */
1743 int radeon_driver_firstopen(struct drm_device *dev)
1744 {
1745 int ret;
1746 drm_local_map_t *map;
1747 drm_radeon_private_t *dev_priv = dev->dev_private;
1748
1749 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1750
1751 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1752 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1753 _DRM_READ_ONLY, &dev_priv->mmio);
1754 if (ret != 0)
1755 return ret;
1756
1757 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1758 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1759 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1760 _DRM_WRITE_COMBINING, &map);
1761 if (ret != 0)
1762 return ret;
1763
1764 return 0;
1765 }
1766
1767 int radeon_driver_unload(struct drm_device *dev)
1768 {
1769 drm_radeon_private_t *dev_priv = dev->dev_private;
1770
1771 DRM_DEBUG("\n");
1772 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1773
1774 dev->dev_private = NULL;
1775 return 0;
1776 }
linux 2.6 git repository for openrd