2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
13 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
18 #include <linux/types.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/acpi.h>
26 /* The Mellanox Tavor device gives false positive parity errors
27 * Mark this device with a broken_parity_status, to allow
28 * PCI scanning code to "skip" this now blacklisted device.
30 static void __devinit
quirk_mellanox_tavor(struct pci_dev
*dev
)
32 dev
->broken_parity_status
= 1; /* This device gives false positives */
34 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR
,quirk_mellanox_tavor
);
35 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX
,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE
,quirk_mellanox_tavor
);
37 /* Deal with broken BIOS'es that neglect to enable passive release,
38 which can cause problems in combination with the 82441FX/PPro MTRRs */
39 static void __devinit
quirk_passive_release(struct pci_dev
*dev
)
41 struct pci_dev
*d
= NULL
;
44 /* We have to make sure a particular bit is set in the PIIX3
45 ISA bridge, so we have to go out and find it. */
46 while ((d
= pci_get_device(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, d
))) {
47 pci_read_config_byte(d
, 0x82, &dlc
);
49 printk(KERN_ERR
"PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d
));
51 pci_write_config_byte(d
, 0x82, dlc
);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_passive_release
);
57 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
58 but VIA don't answer queries. If you happen to have good contacts at VIA
59 ask them for me please -- Alan
61 This appears to be BIOS not version dependent. So presumably there is a
63 int isa_dma_bridge_buggy
; /* Exported */
65 static void __devinit
quirk_isa_dma_hangs(struct pci_dev
*dev
)
67 if (!isa_dma_bridge_buggy
) {
68 isa_dma_bridge_buggy
=1;
69 printk(KERN_INFO
"Activating ISA DMA hang workarounds.\n");
73 * Its not totally clear which chipsets are the problematic ones
74 * We know 82C586 and 82C596 variants are affected.
76 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_isa_dma_hangs
);
77 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C596
, quirk_isa_dma_hangs
);
78 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371SB_0
, quirk_isa_dma_hangs
);
79 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1533
, quirk_isa_dma_hangs
);
80 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_1
, quirk_isa_dma_hangs
);
81 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_2
, quirk_isa_dma_hangs
);
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC
, PCI_DEVICE_ID_NEC_CBUS_3
, quirk_isa_dma_hangs
);
87 * Chipsets where PCI->PCI transfers vanish or hang
89 static void __devinit
quirk_nopcipci(struct pci_dev
*dev
)
91 if ((pci_pci_problems
& PCIPCI_FAIL
)==0) {
92 printk(KERN_INFO
"Disabling direct PCI/PCI transfers.\n");
93 pci_pci_problems
|= PCIPCI_FAIL
;
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_5597
, quirk_nopcipci
);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_496
, quirk_nopcipci
);
100 * Triton requires workarounds to be used by the drivers
102 static void __devinit
quirk_triton(struct pci_dev
*dev
)
104 if ((pci_pci_problems
&PCIPCI_TRITON
)==0) {
105 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
106 pci_pci_problems
|= PCIPCI_TRITON
;
109 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437
, quirk_triton
);
110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
, quirk_triton
);
111 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439
, quirk_triton
);
112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82439TX
, quirk_triton
);
115 * VIA Apollo KT133 needs PCI latency patch
116 * Made according to a windows driver based patch by George E. Breese
117 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
118 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
119 * the info on which Mr Breese based his work.
121 * Updated based on further information from the site and also on
122 * information provided by VIA
124 static void __devinit
quirk_vialatency(struct pci_dev
*dev
)
129 /* Ok we have a potential problem chipset here. Now see if we have
130 a buggy southbridge */
132 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, NULL
);
134 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
135 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
136 /* Check for buggy part revisions */
137 if (rev
< 0x40 || rev
> 0x42)
140 p
= pci_get_device(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8231
, NULL
);
141 if (p
==NULL
) /* No problem parts */
143 pci_read_config_byte(p
, PCI_CLASS_REVISION
, &rev
);
144 /* Check for buggy part revisions */
145 if (rev
< 0x10 || rev
> 0x12)
150 * Ok we have the problem. Now set the PCI master grant to
151 * occur every master grant. The apparent bug is that under high
152 * PCI load (quite common in Linux of course) you can get data
153 * loss when the CPU is held off the bus for 3 bus master requests
154 * This happens to include the IDE controllers....
156 * VIA only apply this fix when an SB Live! is present but under
157 * both Linux and Windows this isnt enough, and we have seen
158 * corruption without SB Live! but with things like 3 UDMA IDE
159 * controllers. So we ignore that bit of the VIA recommendation..
162 pci_read_config_byte(dev
, 0x76, &busarb
);
163 /* Set bit 4 and bi 5 of byte 76 to 0x01
164 "Master priority rotation on every PCI master grant */
167 pci_write_config_byte(dev
, 0x76, busarb
);
168 printk(KERN_INFO
"Applying VIA southbridge workaround.\n");
172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8363_0
, quirk_vialatency
);
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8371_1
, quirk_vialatency
);
174 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8361
, quirk_vialatency
);
177 * VIA Apollo VP3 needs ETBF on BT848/878
179 static void __devinit
quirk_viaetbf(struct pci_dev
*dev
)
181 if ((pci_pci_problems
&PCIPCI_VIAETBF
)==0) {
182 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
183 pci_pci_problems
|= PCIPCI_VIAETBF
;
186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_viaetbf
);
188 static void __devinit
quirk_vsfx(struct pci_dev
*dev
)
190 if ((pci_pci_problems
&PCIPCI_VSFX
)==0) {
191 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
192 pci_pci_problems
|= PCIPCI_VSFX
;
195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C576
, quirk_vsfx
);
198 * Ali Magik requires workarounds to be used by the drivers
199 * that DMA to AGP space. Latency must be set to 0xA and triton
200 * workaround applied too
201 * [Info kindly provided by ALi]
203 static void __init
quirk_alimagik(struct pci_dev
*dev
)
205 if ((pci_pci_problems
&PCIPCI_ALIMAGIK
)==0) {
206 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
207 pci_pci_problems
|= PCIPCI_ALIMAGIK
|PCIPCI_TRITON
;
210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1647
, quirk_alimagik
);
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M1651
, quirk_alimagik
);
214 * Natoma has some interesting boundary conditions with Zoran stuff
217 static void __devinit
quirk_natoma(struct pci_dev
*dev
)
219 if ((pci_pci_problems
&PCIPCI_NATOMA
)==0) {
220 printk(KERN_INFO
"Limiting direct PCI/PCI transfers.\n");
221 pci_pci_problems
|= PCIPCI_NATOMA
;
224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82441
, quirk_natoma
);
225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_0
, quirk_natoma
);
226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443LX_1
, quirk_natoma
);
227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_0
, quirk_natoma
);
228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_1
, quirk_natoma
);
229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443BX_2
, quirk_natoma
);
232 * This chip can cause PCI parity errors if config register 0xA0 is read
233 * while DMAs are occurring.
235 static void __devinit
quirk_citrine(struct pci_dev
*dev
)
237 dev
->cfg_size
= 0xA0;
239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CITRINE
, quirk_citrine
);
242 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
243 * If it's needed, re-allocate the region.
245 static void __devinit
quirk_s3_64M(struct pci_dev
*dev
)
247 struct resource
*r
= &dev
->resource
[0];
249 if ((r
->start
& 0x3ffffff) || r
->end
!= r
->start
+ 0x3ffffff) {
254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_868
, quirk_s3_64M
);
255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3
, PCI_DEVICE_ID_S3_968
, quirk_s3_64M
);
257 static void __devinit
quirk_io_region(struct pci_dev
*dev
, unsigned region
,
258 unsigned size
, int nr
, const char *name
)
262 struct pci_bus_region bus_region
;
263 struct resource
*res
= dev
->resource
+ nr
;
265 res
->name
= pci_name(dev
);
267 res
->end
= region
+ size
- 1;
268 res
->flags
= IORESOURCE_IO
;
270 /* Convert from PCI bus to resource space. */
271 bus_region
.start
= res
->start
;
272 bus_region
.end
= res
->end
;
273 pcibios_bus_to_resource(dev
, res
, &bus_region
);
275 pci_claim_resource(dev
, nr
);
276 printk("PCI quirk: region %04x-%04x claimed by %s\n", region
, region
+ size
- 1, name
);
281 * ATI Northbridge setups MCE the processor if you even
282 * read somewhere between 0x3b0->0x3bb or read 0x3d3
284 static void __devinit
quirk_ati_exploding_mce(struct pci_dev
*dev
)
286 printk(KERN_INFO
"ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
287 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
288 request_region(0x3b0, 0x0C, "RadeonIGP");
289 request_region(0x3d3, 0x01, "RadeonIGP");
291 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_RS100
, quirk_ati_exploding_mce
);
294 * Let's make the southbridge information explicit instead
295 * of having to worry about people probing the ACPI areas,
296 * for example.. (Yes, it happens, and if you read the wrong
297 * ACPI register it will put the machine to sleep with no
298 * way of waking it up again. Bummer).
300 * ALI M7101: Two IO regions pointed to by words at
301 * 0xE0 (64 bytes of ACPI registers)
302 * 0xE2 (32 bytes of SMB registers)
304 static void __devinit
quirk_ali7101_acpi(struct pci_dev
*dev
)
308 pci_read_config_word(dev
, 0xE0, ®ion
);
309 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "ali7101 ACPI");
310 pci_read_config_word(dev
, 0xE2, ®ion
);
311 quirk_io_region(dev
, region
, 32, PCI_BRIDGE_RESOURCES
+1, "ali7101 SMB");
313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_AL_M7101
, quirk_ali7101_acpi
);
315 static void piix4_io_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
318 u32 mask
, size
, base
;
320 pci_read_config_dword(dev
, port
, &devres
);
321 if ((devres
& enable
) != enable
)
323 mask
= (devres
>> 16) & 15;
324 base
= devres
& 0xffff;
327 unsigned bit
= size
>> 1;
328 if ((bit
& mask
) == bit
)
333 * For now we only print it out. Eventually we'll want to
334 * reserve it (at least if it's in the 0x1000+ range), but
335 * let's get enough confirmation reports first.
338 printk("%s PIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
341 static void piix4_mem_quirk(struct pci_dev
*dev
, const char *name
, unsigned int port
, unsigned int enable
)
344 u32 mask
, size
, base
;
346 pci_read_config_dword(dev
, port
, &devres
);
347 if ((devres
& enable
) != enable
)
349 base
= devres
& 0xffff0000;
350 mask
= (devres
& 0x3f) << 16;
353 unsigned bit
= size
>> 1;
354 if ((bit
& mask
) == bit
)
359 * For now we only print it out. Eventually we'll want to
360 * reserve it, but let's get enough confirmation reports first.
363 printk("%s MMIO at %04x-%04x\n", name
, base
, base
+ size
- 1);
367 * PIIX4 ACPI: Two IO regions pointed to by longwords at
368 * 0x40 (64 bytes of ACPI registers)
369 * 0x90 (16 bytes of SMB registers)
370 * and a few strange programmable PIIX4 device resources.
372 static void __devinit
quirk_piix4_acpi(struct pci_dev
*dev
)
376 pci_read_config_dword(dev
, 0x40, ®ion
);
377 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
, "PIIX4 ACPI");
378 pci_read_config_dword(dev
, 0x90, ®ion
);
379 quirk_io_region(dev
, region
, 16, PCI_BRIDGE_RESOURCES
+1, "PIIX4 SMB");
381 /* Device resource A has enables for some of the other ones */
382 pci_read_config_dword(dev
, 0x5c, &res_a
);
384 piix4_io_quirk(dev
, "PIIX4 devres B", 0x60, 3 << 21);
385 piix4_io_quirk(dev
, "PIIX4 devres C", 0x64, 3 << 21);
387 /* Device resource D is just bitfields for static resources */
389 /* Device 12 enabled? */
390 if (res_a
& (1 << 29)) {
391 piix4_io_quirk(dev
, "PIIX4 devres E", 0x68, 1 << 20);
392 piix4_mem_quirk(dev
, "PIIX4 devres F", 0x6c, 1 << 7);
394 /* Device 13 enabled? */
395 if (res_a
& (1 << 30)) {
396 piix4_io_quirk(dev
, "PIIX4 devres G", 0x70, 1 << 20);
397 piix4_mem_quirk(dev
, "PIIX4 devres H", 0x74, 1 << 7);
399 piix4_io_quirk(dev
, "PIIX4 devres I", 0x78, 1 << 20);
400 piix4_io_quirk(dev
, "PIIX4 devres J", 0x7c, 1 << 20);
402 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82371AB_3
, quirk_piix4_acpi
);
403 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82443MX_3
, quirk_piix4_acpi
);
406 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
407 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
408 * 0x58 (64 bytes of GPIO I/O space)
410 static void __devinit
quirk_ich4_lpc_acpi(struct pci_dev
*dev
)
414 pci_read_config_dword(dev
, 0x40, ®ion
);
415 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH4 ACPI/GPIO/TCO");
417 pci_read_config_dword(dev
, 0x58, ®ion
);
418 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH4 GPIO");
420 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_0
, quirk_ich4_lpc_acpi
);
421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_0
, quirk_ich4_lpc_acpi
);
422 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, quirk_ich4_lpc_acpi
);
423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_10
, quirk_ich4_lpc_acpi
);
424 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
, quirk_ich4_lpc_acpi
);
425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, quirk_ich4_lpc_acpi
);
426 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, quirk_ich4_lpc_acpi
);
427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, quirk_ich4_lpc_acpi
);
428 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, quirk_ich4_lpc_acpi
);
429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
, quirk_ich4_lpc_acpi
);
431 static void __devinit
quirk_ich6_lpc_acpi(struct pci_dev
*dev
)
435 pci_read_config_dword(dev
, 0x40, ®ion
);
436 quirk_io_region(dev
, region
, 128, PCI_BRIDGE_RESOURCES
, "ICH6 ACPI/GPIO/TCO");
438 pci_read_config_dword(dev
, 0x48, ®ion
);
439 quirk_io_region(dev
, region
, 64, PCI_BRIDGE_RESOURCES
+1, "ICH6 GPIO");
441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, quirk_ich6_lpc_acpi
);
444 * VIA ACPI: One IO region pointed to by longword at
445 * 0x48 or 0x20 (256 bytes of ACPI registers)
447 static void __devinit
quirk_vt82c586_acpi(struct pci_dev
*dev
)
452 pci_read_config_byte(dev
, PCI_CLASS_REVISION
, &rev
);
454 pci_read_config_dword(dev
, 0x48, ®ion
);
455 region
&= PCI_BASE_ADDRESS_IO_MASK
;
456 quirk_io_region(dev
, region
, 256, PCI_BRIDGE_RESOURCES
, "vt82c586 ACPI");
459 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_vt82c586_acpi
);
462 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
463 * 0x48 (256 bytes of ACPI registers)
464 * 0x70 (128 bytes of hardware monitoring register)
465 * 0x90 (16 bytes of SMB registers)
467 static void __devinit
quirk_vt82c686_acpi(struct pci_dev
*dev
)
472 quirk_vt82c586_acpi(dev
);
474 pci_read_config_word(dev
, 0x70, &hm
);
475 hm
&= PCI_BASE_ADDRESS_IO_MASK
;
476 quirk_io_region(dev
, hm
, 128, PCI_BRIDGE_RESOURCES
+ 1, "vt82c686 HW-mon");
478 pci_read_config_dword(dev
, 0x90, &smb
);
479 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
480 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 2, "vt82c686 SMB");
482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_vt82c686_acpi
);
485 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
486 * 0x88 (128 bytes of power management registers)
487 * 0xd0 (16 bytes of SMB registers)
489 static void __devinit
quirk_vt8235_acpi(struct pci_dev
*dev
)
493 pci_read_config_word(dev
, 0x88, &pm
);
494 pm
&= PCI_BASE_ADDRESS_IO_MASK
;
495 quirk_io_region(dev
, pm
, 128, PCI_BRIDGE_RESOURCES
, "vt8235 PM");
497 pci_read_config_word(dev
, 0xd0, &smb
);
498 smb
&= PCI_BASE_ADDRESS_IO_MASK
;
499 quirk_io_region(dev
, smb
, 16, PCI_BRIDGE_RESOURCES
+ 1, "vt8235 SMB");
501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_vt8235_acpi
);
504 #ifdef CONFIG_X86_IO_APIC
506 #include <asm/io_apic.h>
509 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
510 * devices to the external APIC.
512 * TODO: When we have device-specific interrupt routers,
513 * this code will go away from quirks.
515 static void __devinit
quirk_via_ioapic(struct pci_dev
*dev
)
520 tmp
= 0; /* nothing routed to external APIC */
522 tmp
= 0x1f; /* all known bits (4-0) routed to external APIC */
524 printk(KERN_INFO
"PCI: %sbling Via external APIC routing\n",
525 tmp
== 0 ? "Disa" : "Ena");
527 /* Offset 0x58: External APIC IRQ output control */
528 pci_write_config_byte (dev
, 0x58, tmp
);
530 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_ioapic
);
533 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
534 * This leads to doubled level interrupt rates.
535 * Set this bit to get rid of cycle wastage.
536 * Otherwise uncritical.
538 static void __devinit
quirk_via_vt8237_bypass_apic_deassert(struct pci_dev
*dev
)
541 #define BYPASS_APIC_DEASSERT 8
543 pci_read_config_byte(dev
, 0x5B, &misc_control2
);
544 if (!(misc_control2
& BYPASS_APIC_DEASSERT
)) {
545 printk(KERN_INFO
"PCI: Bypassing VIA 8237 APIC De-Assert Message\n");
546 pci_write_config_byte(dev
, 0x5B, misc_control2
|BYPASS_APIC_DEASSERT
);
549 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_vt8237_bypass_apic_deassert
);
552 * The AMD io apic can hang the box when an apic irq is masked.
553 * We check all revs >= B0 (yet not in the pre production!) as the bug
554 * is currently marked NoFix
556 * We have multiple reports of hangs with this chipset that went away with
557 * noapic specified. For the moment we assume its the errata. We may be wrong
558 * of course. However the advice is demonstrably good even if so..
560 static void __devinit
quirk_amd_ioapic(struct pci_dev
*dev
)
564 pci_read_config_byte(dev
, PCI_REVISION_ID
, &rev
);
566 printk(KERN_WARNING
"I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
567 printk(KERN_WARNING
" : booting with the \"noapic\" option.\n");
570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_VIPER_7410
, quirk_amd_ioapic
);
572 static void __init
quirk_ioapic_rmw(struct pci_dev
*dev
)
574 if (dev
->devfn
== 0 && dev
->bus
->number
== 0)
577 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI
, PCI_ANY_ID
, quirk_ioapic_rmw
);
581 #define AMD8131_revA0 0x01
582 #define AMD8131_revB0 0x11
583 #define AMD8131_MISC 0x40
584 #define AMD8131_NIOAMODE_BIT 0
585 static void __init
quirk_amd_8131_ioapic(struct pci_dev
*dev
)
587 unsigned char revid
, tmp
;
589 if (dev
->subordinate
) {
590 printk(KERN_WARNING
"PCI: MSI quirk detected. "
591 "PCI_BUS_FLAGS_NO_MSI set for subordinate bus.\n");
592 dev
->subordinate
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
598 pci_read_config_byte(dev
, PCI_REVISION_ID
, &revid
);
599 if (revid
== AMD8131_revA0
|| revid
== AMD8131_revB0
) {
600 printk(KERN_INFO
"Fixing up AMD8131 IOAPIC mode\n");
601 pci_read_config_byte( dev
, AMD8131_MISC
, &tmp
);
602 tmp
&= ~(1 << AMD8131_NIOAMODE_BIT
);
603 pci_write_config_byte( dev
, AMD8131_MISC
, tmp
);
606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
, quirk_amd_8131_ioapic
);
608 static void __init
quirk_svw_msi(struct pci_dev
*dev
)
611 printk(KERN_WARNING
"PCI: MSI quirk detected. pci_msi_quirk set.\n");
613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE
, quirk_svw_msi
);
614 #endif /* CONFIG_X86_IO_APIC */
618 * FIXME: it is questionable that quirk_via_acpi
619 * is needed. It shows up as an ISA bridge, and does not
620 * support the PCI_INTERRUPT_LINE register at all. Therefore
621 * it seems like setting the pci_dev's 'irq' to the
622 * value of the ACPI SCI interrupt is only done for convenience.
625 static void __devinit
quirk_via_acpi(struct pci_dev
*d
)
628 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
631 pci_read_config_byte(d
, 0x42, &irq
);
633 if (irq
&& (irq
!= 2))
636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_acpi
);
637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_acpi
);
640 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
641 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
642 * when written, it makes an internal connection to the PIC.
643 * For these devices, this register is defined to be 4 bits wide.
644 * Normally this is fine. However for IO-APIC motherboards, or
645 * non-x86 architectures (yes Via exists on PPC among other places),
646 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
647 * interrupts delivered properly.
649 * Some of the on-chip devices are actually '586 devices' so they are
652 static void quirk_via_irq(struct pci_dev
*dev
)
656 new_irq
= dev
->irq
& 0xf;
657 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
658 if (new_irq
!= irq
) {
659 printk(KERN_INFO
"PCI: VIA IRQ fixup for %s, from %d to %d\n",
660 pci_name(dev
), irq
, new_irq
);
661 udelay(15); /* unknown if delay really needed */
662 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, new_irq
);
665 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_0
, quirk_via_irq
);
666 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_1
, quirk_via_irq
);
667 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_2
, quirk_via_irq
);
668 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C586_3
, quirk_via_irq
);
669 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686
, quirk_via_irq
);
670 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_4
, quirk_via_irq
);
671 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C686_5
, quirk_via_irq
);
674 * VIA VT82C598 has its device ID settable and many BIOSes
675 * set it to the ID of VT82C597 for backward compatibility.
676 * We need to switch it off to be able to recognize the real
679 static void __devinit
quirk_vt82c598_id(struct pci_dev
*dev
)
681 pci_write_config_byte(dev
, 0xfc, 0);
682 pci_read_config_word(dev
, PCI_DEVICE_ID
, &dev
->device
);
684 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_82C597_0
, quirk_vt82c598_id
);
686 #ifdef CONFIG_ACPI_SLEEP
689 * Some VIA systems boot with the abnormal status flag set. This can cause
690 * the BIOS to re-POST the system on resume rather than passing control
691 * back to the OS. Clear the flag on boot
693 static void __devinit
quirk_via_abnormal_poweroff(struct pci_dev
*dev
)
697 acpi_hw_register_read(ACPI_MTX_DO_NOT_LOCK
, ACPI_REGISTER_PM1_STATUS
,
701 printk("Clearing abnormal poweroff flag\n");
702 acpi_hw_register_write(ACPI_MTX_DO_NOT_LOCK
,
703 ACPI_REGISTER_PM1_STATUS
,
708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
, quirk_via_abnormal_poweroff
);
709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, quirk_via_abnormal_poweroff
);
714 * CardBus controllers have a legacy base address that enables them
715 * to respond as i82365 pcmcia controllers. We don't want them to
716 * do this even if the Linux CardBus driver is not loaded, because
717 * the Linux i82365 driver does not (and should not) handle CardBus.
719 static void __devinit
quirk_cardbus_legacy(struct pci_dev
*dev
)
721 if ((PCI_CLASS_BRIDGE_CARDBUS
<< 8) ^ dev
->class)
723 pci_write_config_dword(dev
, PCI_CB_LEGACY_MODE_BASE
, 0);
725 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, quirk_cardbus_legacy
);
728 * Following the PCI ordering rules is optional on the AMD762. I'm not
729 * sure what the designers were smoking but let's not inhale...
731 * To be fair to AMD, it follows the spec by default, its BIOS people
734 static void __devinit
quirk_amd_ordering(struct pci_dev
*dev
)
737 pci_read_config_dword(dev
, 0x4C, &pcic
);
740 printk(KERN_WARNING
"BIOS failed to enable PCI standards compliance, fixing this error.\n");
741 pci_write_config_dword(dev
, 0x4C, pcic
);
742 pci_read_config_dword(dev
, 0x84, &pcic
);
743 pcic
|= (1<<23); /* Required in this mode */
744 pci_write_config_dword(dev
, 0x84, pcic
);
747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
, quirk_amd_ordering
);
750 * DreamWorks provided workaround for Dunord I-3000 problem
752 * This card decodes and responds to addresses not apparently
753 * assigned to it. We force a larger allocation to ensure that
754 * nothing gets put too close to it.
756 static void __devinit
quirk_dunord ( struct pci_dev
* dev
)
758 struct resource
*r
= &dev
->resource
[1];
762 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD
, PCI_DEVICE_ID_DUNORD_I3000
, quirk_dunord
);
765 * i82380FB mobile docking controller: its PCI-to-PCI bridge
766 * is subtractive decoding (transparent), and does indicate this
767 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
770 static void __devinit
quirk_transparent_bridge(struct pci_dev
*dev
)
772 dev
->transparent
= 1;
774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82380FB
, quirk_transparent_bridge
);
775 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA
, 0x605, quirk_transparent_bridge
);
778 * Common misconfiguration of the MediaGX/Geode PCI master that will
779 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
780 * datasheets found at http://www.national.com/ds/GX for info on what
781 * these bits do. <christer@weinigel.se>
783 static void __init
quirk_mediagx_master(struct pci_dev
*dev
)
786 pci_read_config_byte(dev
, 0x41, ®
);
789 printk(KERN_INFO
"PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg
);
790 pci_write_config_byte(dev
, 0x41, reg
);
793 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX
, PCI_DEVICE_ID_CYRIX_PCI_MASTER
, quirk_mediagx_master
);
796 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
797 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
798 * secondary channels respectively). If the device reports Compatible mode
799 * but does use BAR0-3 for address decoding, we assume that firmware has
800 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
801 * Exceptions (if they exist) must be handled in chip/architecture specific
804 * Note: for non x86 people. You may need an arch specific quirk to handle
805 * moving IDE devices to native mode as well. Some plug in card devices power
806 * up in compatible mode and assume the BIOS will adjust them.
808 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
809 * we do now ? We don't want is pci_enable_device to come along
810 * and assign new resources. Both approaches work for that.
812 static void __devinit
quirk_ide_bases(struct pci_dev
*dev
)
814 struct resource
*res
;
815 int first_bar
= 2, last_bar
= 0;
817 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
820 res
= &dev
->resource
[0];
822 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
823 if (!(dev
->class & 1) && (res
[0].flags
|| res
[1].flags
)) {
824 res
[0].start
= res
[0].end
= res
[0].flags
= 0;
825 res
[1].start
= res
[1].end
= res
[1].flags
= 0;
830 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
831 if (!(dev
->class & 4) && (res
[2].flags
|| res
[3].flags
)) {
832 res
[2].start
= res
[2].end
= res
[2].flags
= 0;
833 res
[3].start
= res
[3].end
= res
[3].flags
= 0;
840 printk(KERN_INFO
"PCI: Ignoring BAR%d-%d of IDE controller %s\n",
841 first_bar
, last_bar
, pci_name(dev
));
843 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, quirk_ide_bases
);
846 * Ensure C0 rev restreaming is off. This is normally done by
847 * the BIOS but in the odd case it is not the results are corruption
848 * hence the presence of a Linux check
850 static void __init
quirk_disable_pxb(struct pci_dev
*pdev
)
855 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &rev
);
856 if (rev
!= 0x04) /* Only C0 requires this */
858 pci_read_config_word(pdev
, 0x40, &config
);
859 if (config
& (1<<6)) {
861 pci_write_config_word(pdev
, 0x40, config
);
862 printk(KERN_INFO
"PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
865 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82454NX
, quirk_disable_pxb
);
869 * Serverworks CSB5 IDE does not fully support native mode
871 static void __devinit
quirk_svwks_csb5ide(struct pci_dev
*pdev
)
874 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
878 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
879 /* need to re-assign BARs for compat mode */
880 quirk_ide_bases(pdev
);
883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE
, quirk_svwks_csb5ide
);
886 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
888 static void __init
quirk_ide_samemode(struct pci_dev
*pdev
)
892 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
894 if (((prog
& 1) && !(prog
& 4)) || ((prog
& 4) && !(prog
& 1))) {
895 printk(KERN_INFO
"PCI: IDE mode mismatch; forcing legacy mode\n");
898 pci_write_config_byte(pdev
, PCI_CLASS_PROG
, prog
);
899 /* need to re-assign BARs for compat mode */
900 quirk_ide_bases(pdev
);
903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_10
, quirk_ide_samemode
);
905 /* This was originally an Alpha specific thing, but it really fits here.
906 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
908 static void __init
quirk_eisa_bridge(struct pci_dev
*dev
)
910 dev
->class = PCI_CLASS_BRIDGE_EISA
<< 8;
912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82375
, quirk_eisa_bridge
);
915 * On the MSI-K8T-Neo2Fir Board, the internal Soundcard is disabled
916 * when a PCI-Soundcard is added. The BIOS only gives Options
917 * "Disabled" and "AUTO". This Quirk Sets the corresponding
918 * Register-Value to enable the Soundcard.
920 * FIXME: Presently this quirk will run on anything that has an 8237
921 * which isn't correct, we need to check DMI tables or something in
922 * order to make sure it only runs on the MSI-K8T-Neo2Fir. Because it
923 * runs everywhere at present we suppress the printk output in most
926 static void __init
k8t_sound_hostbridge(struct pci_dev
*dev
)
930 pci_read_config_byte(dev
, 0x50, &val
);
931 if (val
== 0x88 || val
== 0xc8) {
932 /* Assume it's probably a MSI-K8T-Neo2Fir */
933 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, attempting to turn soundcard ON\n");
934 pci_write_config_byte(dev
, 0x50, val
& (~0x40));
936 /* Verify the Change for Status output */
937 pci_read_config_byte(dev
, 0x50, &val
);
939 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, soundcard still off\n");
941 printk(KERN_INFO
"PCI: MSI-K8T-Neo2Fir, soundcard on\n");
944 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, k8t_sound_hostbridge
);
946 #ifndef CONFIG_ACPI_SLEEP
948 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
949 * is not activated. The myth is that Asus said that they do not want the
950 * users to be irritated by just another PCI Device in the Win98 device
951 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
952 * package 2.7.0 for details)
954 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
955 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
956 * becomes necessary to do this tweak in two steps -- I've chosen the Host
959 * Actually, leaving it unhidden and not redoing the quirk over suspend2ram
960 * will cause thermal management to break down, and causing machine to
963 static int __initdata asus_hides_smbus
;
965 static void __init
asus_hides_smbus_hostbridge(struct pci_dev
*dev
)
967 if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
968 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845_HB
)
969 switch(dev
->subsystem_device
) {
970 case 0x8025: /* P4B-LX */
971 case 0x8070: /* P4B */
972 case 0x8088: /* P4B533 */
973 case 0x1626: /* L3C notebook */
974 asus_hides_smbus
= 1;
976 if (dev
->device
== PCI_DEVICE_ID_INTEL_82845G_HB
)
977 switch(dev
->subsystem_device
) {
978 case 0x80b1: /* P4GE-V */
979 case 0x80b2: /* P4PE */
980 case 0x8093: /* P4B533-V */
981 asus_hides_smbus
= 1;
983 if (dev
->device
== PCI_DEVICE_ID_INTEL_82850_HB
)
984 switch(dev
->subsystem_device
) {
985 case 0x8030: /* P4T533 */
986 asus_hides_smbus
= 1;
988 if (dev
->device
== PCI_DEVICE_ID_INTEL_7205_0
)
989 switch (dev
->subsystem_device
) {
990 case 0x8070: /* P4G8X Deluxe */
991 asus_hides_smbus
= 1;
993 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
994 switch (dev
->subsystem_device
) {
995 case 0x1751: /* M2N notebook */
996 case 0x1821: /* M5N notebook */
997 asus_hides_smbus
= 1;
999 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1000 switch (dev
->subsystem_device
) {
1001 case 0x184b: /* W1N notebook */
1002 case 0x186a: /* M6Ne notebook */
1003 asus_hides_smbus
= 1;
1005 if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
) {
1006 switch (dev
->subsystem_device
) {
1007 case 0x1882: /* M6V notebook */
1008 case 0x1977: /* A6VA notebook */
1009 asus_hides_smbus
= 1;
1012 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_HP
)) {
1013 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1014 switch(dev
->subsystem_device
) {
1015 case 0x088C: /* HP Compaq nc8000 */
1016 case 0x0890: /* HP Compaq nc6000 */
1017 asus_hides_smbus
= 1;
1019 if (dev
->device
== PCI_DEVICE_ID_INTEL_82865_HB
)
1020 switch (dev
->subsystem_device
) {
1021 case 0x12bc: /* HP D330L */
1022 case 0x12bd: /* HP D530 */
1023 asus_hides_smbus
= 1;
1025 if (dev
->device
== PCI_DEVICE_ID_INTEL_82915GM_HB
) {
1026 switch (dev
->subsystem_device
) {
1027 case 0x099c: /* HP Compaq nx6110 */
1028 asus_hides_smbus
= 1;
1031 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_TOSHIBA
)) {
1032 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855GM_HB
)
1033 switch(dev
->subsystem_device
) {
1034 case 0x0001: /* Toshiba Satellite A40 */
1035 asus_hides_smbus
= 1;
1037 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1038 switch(dev
->subsystem_device
) {
1039 case 0x0001: /* Toshiba Tecra M2 */
1040 asus_hides_smbus
= 1;
1042 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_SAMSUNG
)) {
1043 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1044 switch(dev
->subsystem_device
) {
1045 case 0xC00C: /* Samsung P35 notebook */
1046 asus_hides_smbus
= 1;
1048 } else if (unlikely(dev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
)) {
1049 if (dev
->device
== PCI_DEVICE_ID_INTEL_82855PM_HB
)
1050 switch(dev
->subsystem_device
) {
1051 case 0x0058: /* Compaq Evo N620c */
1052 asus_hides_smbus
= 1;
1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845_HB
, asus_hides_smbus_hostbridge
);
1057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82845G_HB
, asus_hides_smbus_hostbridge
);
1058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82850_HB
, asus_hides_smbus_hostbridge
);
1059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82865_HB
, asus_hides_smbus_hostbridge
);
1060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_7205_0
, asus_hides_smbus_hostbridge
);
1061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855PM_HB
, asus_hides_smbus_hostbridge
);
1062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82855GM_HB
, asus_hides_smbus_hostbridge
);
1063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82915GM_HB
, asus_hides_smbus_hostbridge
);
1065 static void __init
asus_hides_smbus_lpc(struct pci_dev
*dev
)
1069 if (likely(!asus_hides_smbus
))
1072 pci_read_config_word(dev
, 0xF2, &val
);
1074 pci_write_config_word(dev
, 0xF2, val
& (~0x8));
1075 pci_read_config_word(dev
, 0xF2, &val
);
1077 printk(KERN_INFO
"PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val
);
1079 printk(KERN_INFO
"PCI: Enabled i801 SMBus device\n");
1082 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
, asus_hides_smbus_lpc
);
1083 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_0
, asus_hides_smbus_lpc
);
1084 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
, asus_hides_smbus_lpc
);
1085 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
, asus_hides_smbus_lpc
);
1086 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
, asus_hides_smbus_lpc
);
1087 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc
);
1089 static void __init
asus_hides_smbus_lpc_ich6(struct pci_dev
*dev
)
1094 if (likely(!asus_hides_smbus
))
1096 pci_read_config_dword(dev
, 0xF0, &rcba
);
1097 base
= ioremap_nocache(rcba
& 0xFFFFC000, 0x4000); /* use bits 31:14, 16 kB aligned */
1098 if (base
== NULL
) return;
1099 val
=readl(base
+ 0x3418); /* read the Function Disable register, dword mode only */
1100 writel(val
& 0xFFFFFFF7, base
+ 0x3418); /* enable the SMBus device */
1102 printk(KERN_INFO
"PCI: Enabled ICH6/i801 SMBus device\n");
1104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
, asus_hides_smbus_lpc_ich6
);
1109 * SiS 96x south bridge: BIOS typically hides SMBus device...
1111 static void __init
quirk_sis_96x_smbus(struct pci_dev
*dev
)
1114 printk(KERN_INFO
"Enabling SiS 96x SMBus.\n");
1115 pci_read_config_byte(dev
, 0x77, &val
);
1116 pci_write_config_byte(dev
, 0x77, val
& ~0x10);
1117 pci_read_config_byte(dev
, 0x77, &val
);
1121 * ... This is further complicated by the fact that some SiS96x south
1122 * bridges pretend to be 85C503/5513 instead. In that case see if we
1123 * spotted a compatible north bridge to make sure.
1124 * (pci_find_device doesn't work yet)
1126 * We can also enable the sis96x bit in the discovery register..
1128 static int __devinitdata sis_96x_compatible
= 0;
1130 #define SIS_DETECT_REGISTER 0x40
1132 static void __init
quirk_sis_503(struct pci_dev
*dev
)
1137 pci_read_config_byte(dev
, SIS_DETECT_REGISTER
, ®
);
1138 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
| (1 << 6));
1139 pci_read_config_word(dev
, PCI_DEVICE_ID
, &devid
);
1140 if (((devid
& 0xfff0) != 0x0960) && (devid
!= 0x0018)) {
1141 pci_write_config_byte(dev
, SIS_DETECT_REGISTER
, reg
);
1145 /* Make people aware that we changed the config.. */
1146 printk(KERN_WARNING
"Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid
, sis_96x_compatible
);
1149 * Ok, it now shows up as a 96x.. The 96x quirks are after
1150 * the 503 quirk in the quirk table, so they'll automatically
1151 * run and enable things like the SMBus device
1153 dev
->device
= devid
;
1156 static void __init
quirk_sis_96x_compatible(struct pci_dev
*dev
)
1158 sis_96x_compatible
= 1;
1160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_645
, quirk_sis_96x_compatible
);
1161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_646
, quirk_sis_96x_compatible
);
1162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_648
, quirk_sis_96x_compatible
);
1163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_650
, quirk_sis_96x_compatible
);
1164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_651
, quirk_sis_96x_compatible
);
1165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_735
, quirk_sis_96x_compatible
);
1167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_503
, quirk_sis_503
);
1169 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1170 * and MC97 modem controller are disabled when a second PCI soundcard is
1171 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1174 static void __init
asus_hides_ac97_lpc(struct pci_dev
*dev
)
1177 int asus_hides_ac97
= 0;
1179 if (likely(dev
->subsystem_vendor
== PCI_VENDOR_ID_ASUSTEK
)) {
1180 if (dev
->device
== PCI_DEVICE_ID_VIA_8237
)
1181 asus_hides_ac97
= 1;
1184 if (!asus_hides_ac97
)
1187 pci_read_config_byte(dev
, 0x50, &val
);
1189 pci_write_config_byte(dev
, 0x50, val
& (~0xc0));
1190 pci_read_config_byte(dev
, 0x50, &val
);
1192 printk(KERN_INFO
"PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val
);
1194 printk(KERN_INFO
"PCI: enabled onboard AC97/MC97 devices\n");
1197 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
, asus_hides_ac97_lpc
);
1200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_961
, quirk_sis_96x_smbus
);
1201 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_962
, quirk_sis_96x_smbus
);
1202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_963
, quirk_sis_96x_smbus
);
1203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI
, PCI_DEVICE_ID_SI_LPC
, quirk_sis_96x_smbus
);
1205 #if defined(CONFIG_SCSI_SATA) || defined(CONFIG_SCSI_SATA_MODULE)
1208 * If we are using libata we can drive this chip properly but must
1209 * do this early on to make the additional device appear during
1213 static void __devinit
quirk_jmicron_dualfn(struct pci_dev
*pdev
)
1218 /* Only poke fn 0 */
1219 if (PCI_FUNC(pdev
->devfn
))
1222 switch(pdev
->device
) {
1223 case PCI_DEVICE_ID_JMICRON_JMB365
:
1224 case PCI_DEVICE_ID_JMICRON_JMB366
:
1225 /* Redirect IDE second PATA port to the right spot */
1226 pci_read_config_dword(pdev
, 0x80, &conf
);
1229 pci_write_config_dword(pdev
, 0x80, conf
);
1230 case PCI_DEVICE_ID_JMICRON_JMB361
:
1231 case PCI_DEVICE_ID_JMICRON_JMB363
:
1232 pci_read_config_dword(pdev
, 0x40, &conf
);
1233 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1234 /* Set the class codes correctly and then direct IDE 0 */
1235 conf
&= ~0x000F0200; /* Clear bit 9 and 16-19 */
1236 conf
|= 0x00C20002; /* Set bit 1, 17, 22, 23 */
1237 pci_write_config_dword(pdev
, 0x40, conf
);
1239 /* Reconfigure so that the PCI scanner discovers the
1240 device is now multifunction */
1242 pci_read_config_byte(pdev
, PCI_HEADER_TYPE
, &hdr
);
1243 pdev
->hdr_type
= hdr
& 0x7f;
1244 pdev
->multifunction
= !!(hdr
& 0x80);
1250 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON
, PCI_ANY_ID
, quirk_jmicron_dualfn
);
1254 #ifdef CONFIG_X86_IO_APIC
1255 static void __init
quirk_alder_ioapic(struct pci_dev
*pdev
)
1259 if ((pdev
->class >> 8) != 0xff00)
1262 /* the first BAR is the location of the IO APIC...we must
1263 * not touch this (and it's already covered by the fixmap), so
1264 * forcibly insert it into the resource tree */
1265 if (pci_resource_start(pdev
, 0) && pci_resource_len(pdev
, 0))
1266 insert_resource(&iomem_resource
, &pdev
->resource
[0]);
1268 /* The next five BARs all seem to be rubbish, so just clean
1270 for (i
=1; i
< 6; i
++) {
1271 memset(&pdev
->resource
[i
], 0, sizeof(pdev
->resource
[i
]));
1275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_EESSC
, quirk_alder_ioapic
);
1278 enum ide_combined_type
{ COMBINED
= 0, IDE
= 1, LIBATA
= 2 };
1279 /* Defaults to combined */
1280 static enum ide_combined_type combined_mode
;
1282 static int __init
combined_setup(char *str
)
1284 if (!strncmp(str
, "ide", 3))
1285 combined_mode
= IDE
;
1286 else if (!strncmp(str
, "libata", 6))
1287 combined_mode
= LIBATA
;
1288 else /* "combined" or anything else defaults to old behavior */
1289 combined_mode
= COMBINED
;
1293 __setup("combined_mode=", combined_setup
);
1295 #ifdef CONFIG_SCSI_SATA_INTEL_COMBINED
1296 static void __devinit
quirk_intel_ide_combined(struct pci_dev
*pdev
)
1302 * Narrow down to Intel SATA PCI devices.
1304 switch (pdev
->device
) {
1305 /* PCI ids taken from drivers/scsi/ata_piix.c */
1315 case 0x2680: /* ESB2 */
1322 case 0x2828: /* ICH8M */
1326 /* we do not handle this PCI device */
1331 * Read combined mode register.
1333 pci_read_config_byte(pdev
, 0x90, &tmp
); /* combined mode reg */
1336 tmp
&= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1337 if (tmp
== 0x4) /* bits 10x */
1338 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1339 else if (tmp
== 0x6) /* bits 11x */
1340 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1342 return; /* not in combined mode */
1344 WARN_ON((ich
!= 6) && (ich
!= 7) && (ich
!= 8));
1345 tmp
&= 0x3; /* interesting bits 1:0 */
1347 comb
= (1 << 2); /* PATA port 0, SATA port 1 */
1348 else if (tmp
& (1 << 1))
1349 comb
= (1 << 0); /* SATA port 0, PATA port 1 */
1351 return; /* not in combined mode */
1355 * Read programming interface register.
1356 * (Tells us if it's legacy or native mode)
1358 pci_read_config_byte(pdev
, PCI_CLASS_PROG
, &prog
);
1360 /* if SATA port is in native mode, we're ok. */
1364 /* Don't reserve any so the IDE driver can get them (but only if
1365 * combined_mode=ide).
1367 if (combined_mode
== IDE
)
1370 /* Grab them both for libata if combined_mode=libata. */
1371 if (combined_mode
== LIBATA
) {
1372 request_region(0x1f0, 8, "libata"); /* port 0 */
1373 request_region(0x170, 8, "libata"); /* port 1 */
1377 /* SATA port is in legacy mode. Reserve port so that
1378 * IDE driver does not attempt to use it. If request_region
1379 * fails, it will be obvious at boot time, so we don't bother
1380 * checking return values.
1382 if (comb
== (1 << 0))
1383 request_region(0x1f0, 8, "libata"); /* port 0 */
1385 request_region(0x170, 8, "libata"); /* port 1 */
1387 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_ANY_ID
, quirk_intel_ide_combined
);
1388 #endif /* CONFIG_SCSI_SATA_INTEL_COMBINED */
1393 static void __devinit
quirk_pcie_mch(struct pci_dev
*pdev
)
1397 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
, quirk_pcie_mch
);
1398 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
, quirk_pcie_mch
);
1399 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
, quirk_pcie_mch
);
1403 * It's possible for the MSI to get corrupted if shpc and acpi
1404 * are used together on certain PXH-based systems.
1406 static void __devinit
quirk_pcie_pxh(struct pci_dev
*dev
)
1408 disable_msi_mode(dev
, pci_find_capability(dev
, PCI_CAP_ID_MSI
),
1412 printk(KERN_WARNING
"PCI: PXH quirk detected, "
1413 "disabling MSI for SHPC device\n");
1415 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_0
, quirk_pcie_pxh
);
1416 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHD_1
, quirk_pcie_pxh
);
1417 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
, quirk_pcie_pxh
);
1418 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
, quirk_pcie_pxh
);
1419 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXHV
, quirk_pcie_pxh
);
1423 * Fixup the cardbus bridges on the IBM Dock II docking station
1425 static void __devinit
quirk_ibm_dock2_cardbus(struct pci_dev
*dev
)
1430 * tie the 2 interrupt pins to INTA, and configure the
1431 * multifunction routing register to handle this.
1433 if ((dev
->subsystem_vendor
== PCI_VENDOR_ID_IBM
) &&
1434 (dev
->subsystem_device
== 0x0148)) {
1435 printk(KERN_INFO
"PCI: Found IBM Dock II Cardbus Bridge "
1436 "applying quirk\n");
1437 pci_read_config_dword(dev
, 0x8c, &val
);
1438 val
= ((val
& 0xffffff00) | 0x1002);
1439 pci_write_config_dword(dev
, 0x8c, val
);
1440 pci_read_config_dword(dev
, 0x80, &val
);
1441 val
= ((val
& 0x00ffff00) | 0x2864c077);
1442 pci_write_config_dword(dev
, 0x80, val
);
1446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI
, PCI_DEVICE_ID_TI_1420
,
1447 quirk_ibm_dock2_cardbus
);
1449 static void __devinit
quirk_netmos(struct pci_dev
*dev
)
1451 unsigned int num_parallel
= (dev
->subsystem_device
& 0xf0) >> 4;
1452 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
1455 * These Netmos parts are multiport serial devices with optional
1456 * parallel ports. Even when parallel ports are present, they
1457 * are identified as class SERIAL, which means the serial driver
1458 * will claim them. To prevent this, mark them as class OTHER.
1459 * These combo devices should be claimed by parport_serial.
1461 * The subdevice ID is of the form 0x00PS, where <P> is the number
1462 * of parallel ports and <S> is the number of serial ports.
1464 switch (dev
->device
) {
1465 case PCI_DEVICE_ID_NETMOS_9735
:
1466 case PCI_DEVICE_ID_NETMOS_9745
:
1467 case PCI_DEVICE_ID_NETMOS_9835
:
1468 case PCI_DEVICE_ID_NETMOS_9845
:
1469 case PCI_DEVICE_ID_NETMOS_9855
:
1470 if ((dev
->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL
&&
1472 printk(KERN_INFO
"PCI: Netmos %04x (%u parallel, "
1473 "%u serial); changing class SERIAL to OTHER "
1474 "(use parport_serial)\n",
1475 dev
->device
, num_parallel
, num_serial
);
1476 dev
->class = (PCI_CLASS_COMMUNICATION_OTHER
<< 8) |
1477 (dev
->class & 0xff);
1481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS
, PCI_ANY_ID
, quirk_netmos
);
1484 static void __devinit
fixup_rev1_53c810(struct pci_dev
* dev
)
1486 /* rev 1 ncr53c810 chips don't set the class at all which means
1487 * they don't get their resources remapped. Fix that here.
1490 if (dev
->class == PCI_CLASS_NOT_DEFINED
) {
1491 printk(KERN_INFO
"NCR 53c810 rev 1 detected, setting PCI class.\n");
1492 dev
->class = PCI_CLASS_STORAGE_SCSI
;
1495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
1498 static void pci_do_fixups(struct pci_dev
*dev
, struct pci_fixup
*f
, struct pci_fixup
*end
)
1501 if ((f
->vendor
== dev
->vendor
|| f
->vendor
== (u16
) PCI_ANY_ID
) &&
1502 (f
->device
== dev
->device
|| f
->device
== (u16
) PCI_ANY_ID
)) {
1503 pr_debug("PCI: Calling quirk %p for %s\n", f
->hook
, pci_name(dev
));
1510 extern struct pci_fixup __start_pci_fixups_early
[];
1511 extern struct pci_fixup __end_pci_fixups_early
[];
1512 extern struct pci_fixup __start_pci_fixups_header
[];
1513 extern struct pci_fixup __end_pci_fixups_header
[];
1514 extern struct pci_fixup __start_pci_fixups_final
[];
1515 extern struct pci_fixup __end_pci_fixups_final
[];
1516 extern struct pci_fixup __start_pci_fixups_enable
[];
1517 extern struct pci_fixup __end_pci_fixups_enable
[];
1520 void pci_fixup_device(enum pci_fixup_pass pass
, struct pci_dev
*dev
)
1522 struct pci_fixup
*start
, *end
;
1525 case pci_fixup_early
:
1526 start
= __start_pci_fixups_early
;
1527 end
= __end_pci_fixups_early
;
1530 case pci_fixup_header
:
1531 start
= __start_pci_fixups_header
;
1532 end
= __end_pci_fixups_header
;
1535 case pci_fixup_final
:
1536 start
= __start_pci_fixups_final
;
1537 end
= __end_pci_fixups_final
;
1540 case pci_fixup_enable
:
1541 start
= __start_pci_fixups_enable
;
1542 end
= __end_pci_fixups_enable
;
1546 /* stupid compiler warning, you would think with an enum... */
1549 pci_do_fixups(dev
, start
, end
);
1552 /* Enable 1k I/O space granularity on the Intel P64H2 */
1553 static void __devinit
quirk_p64h2_1k_io(struct pci_dev
*dev
)
1556 u8 io_base_lo
, io_limit_lo
;
1557 unsigned long base
, limit
;
1558 struct resource
*res
= dev
->resource
+ PCI_BRIDGE_RESOURCES
;
1560 pci_read_config_word(dev
, 0x40, &en1k
);
1563 printk(KERN_INFO
"PCI: Enable I/O Space to 1 KB Granularity\n");
1565 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
1566 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
1567 base
= (io_base_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1568 limit
= (io_limit_lo
& (PCI_IO_RANGE_MASK
| 0x0c)) << 8;
1570 if (base
<= limit
) {
1572 res
->end
= limit
+ 0x3ff;
1576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x1460, quirk_p64h2_1k_io
);
1578 /* Under some circumstances, AER is not linked with extended capabilities.
1579 * Force it to be linked by setting the corresponding control bit in the
1582 static void __devinit
quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev
*dev
)
1585 if (pci_read_config_byte(dev
, 0xf41, &b
) == 0) {
1587 pci_write_config_byte(dev
, 0xf41, b
| 0x20);
1589 "PCI: Linking AER extended capability on %s\n",
1594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA
, PCI_DEVICE_ID_NVIDIA_CK804_PCIE
,
1595 quirk_nvidia_ck804_pcie_aer_ext_cap
);
1597 EXPORT_SYMBOL(pcie_mch_quirk
);
1598 #ifdef CONFIG_HOTPLUG
1599 EXPORT_SYMBOL(pci_fixup_device
);